JP3750722B2 - Liquid crystal device, driving device and driving method thereof, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal device, a driving device and a driving method thereof, and an electronic apparatus.
[0002]
[Background Art and Problems to be Solved by the Invention]
Currently, active matrix liquid crystal devices, particularly TFT (Thin Film Transistor) type liquid crystal devices, are driven by AC voltage drive, such as frame inversion drive, line inversion drive, source line inversion drive, and dot inversion drive. ing. Further, in these driving methods, a counter electrode inversion driving method in which a voltage having a polarity opposite to that applied to the pixel electrode is applied to the counter electrode is used to reduce power consumption. In JP-A-7-160228, as shown in FIG. 10A, a counter electrode A is formed on a counter substrate 110 facing the active matrix substrate through a liquid crystal layer. ₁ ~ A _n ~ A _N It is comprised. In FIG. 10A, scanning lines Y arranged on the active matrix substrate and arranged along the first direction. ₁ ~ Y _m ~ Y _M , And the data line X arranged along the second direction ₁ ~ X _n ~ X _N Each of these is transcribed on the counter substrate 110 and displayed in broken lines. This counter electrode A ₁ ~ A _N Is the source line (data line X ₁ ~ X _N ), And each is insulated. In the liquid crystal device having such a counter substrate 110, low voltage driving of the liquid crystal device is realized by performing source line inversion driving for supplying data signal voltages having different polarities to adjacent data lines.
[0003]
Hereinafter, an operation when the liquid crystal device having the above-described counter substrate 110 is subjected to source line inversion driving and dot inversion driving will be described. Here, the counter electrode A _c And data line X _c C is an odd number (1, 3,..., N−1), the counter electrode A _d And data line X _d , D represents an even number (2, 4,..., N).
[0004]
First, an operation when the liquid crystal device is driven by dot inversion will be described with reference to a timing chart of FIG.
[0005]
Frame period f ₁ Selection period H ₁ Counter electrode A _c Are supplied with a negative voltage -Vcom, and the data line X _c Is supplied with the positive polarity data signal voltage + Vd. At the same time, counter electrode A _d Is supplied with a positive voltage + Vcom. Data line X _d Is supplied with a negative data signal voltage -Vd of the opposite polarity.
[0006]
Frame period f ₁ Selection period H ₂ Counter electrode A _c Are supplied with a positive voltage + Vcom and a data line X _c Is supplied with a negative data signal voltage -Vd of the opposite polarity. At the same time, counter electrode A _d Each is supplied with a negative voltage -Vcom. Data line X _d Is supplied with the positive polarity data signal voltage + Vd.
[0007]
Frame period f ₁ Selection period H _Three ~ Selection period H _M Up to this point, the above operations are alternately performed, and a voltage having a reverse polarity is supplied to each of the adjacent pixels. Frame period f ₂ Then, the previous frame period f ₁ Thus, a voltage having a reverse polarity to the voltage supplied to each pixel is supplied to each of the selected pixels.
[0008]
Thus, each selection period H ₁ ~ H _M The counter electrode A is alternately changed to positive polarity + Vcom or negative polarity -Vcom.
[0009]
Here, a more detailed operation will be described with reference to FIG. 12 showing changes in voltages of pixels corresponding to a certain source line (data line).
[0010]
FIG. 12 shows an M liquid crystal panel composed of M scanning lines. ₁ ~ Y _M The change of the voltage applied to each pixel corresponding to each of these is shown with time. Each selection period during which M scanning lines are selected is represented by H ₁ ~ H _M It is defined as Here, for convenience, an example in which ± 5 V is uniformly applied to the liquid crystal is shown. Scan line Y ₁ In the frame period f ₁ Selection period H ₁ Then, a data signal voltage of +5 V is applied to the data line. Selection period H ₂ Scan line Y selected for ₂ Then, selection period H ₂ During this period, a data signal voltage of −5V is applied to the data line. At this time, the scanning line Y ₁ Selection period H ₂ In, the polarity of the counter electrode is inverted. Thus, for example, when the voltage change due to the parasitic capacitance is set to ± 0.1V, the voltage −0.1V due to the parasitic capacitance accumulated in the TFT 30 and the wiring is added to the pixel, and + 4.9V It becomes. Similarly, the scanning line Y _Three ~ Scanning line Y _M In each of the above, the voltage ± 0.1 V due to the parasitic capacitance is added to +5 V or −5 V, which is the voltage originally applied to the liquid crystal. Since the voltage applied to the liquid crystal changes due to the voltage caused by the parasitic capacitance, it is recognized as flicker.
[0011]
In addition, when the liquid crystal device is driven to invert dots in this way, the counter electrode must be shaken for each selection period, so that the power for driving the counter electrode is increased. In addition to the wiring capacitance floating in the wiring, this parasitic capacitance is a capacitance C generated between the gate G and the drain D of the thin film transistor (TFT) 30 as shown in FIG. _GD And a capacitance C generated between the drain D and the source S. _DS caused by.
[0012]
Next, when the liquid crystal device is driven to invert the source line, M scanning lines Y ₁ ~ Y _M A change in voltage applied to each pixel corresponding to each of these will be described with reference to FIG.
[0013]
Frame period f ₁ Then, a positive polarity data signal is applied. Selection period H ₁ Scan line Y ₁ Is selected, the selected scanning line Y ₁ A voltage of +5 V is applied to the pixels corresponding to. Selection period H ₂ Scan line Y ₂ Is selected, similarly, the selected scanning line Y ₂ A voltage of +5 V is applied to the pixels corresponding to. However, the voltage Vcom of the counter electrode is equal to the frame period f. ₁ Selection period H ₁ Must be changed in sync with For this reason, every time the polarity of the counter electrode changes, a voltage due to parasitic capacitance or the like is applied to the liquid crystal.
[0014]
In FIG. 13, as an example, the voltage change caused by parasitic capacitance or the like is set to ± 0.1V. Therefore, the scanning line Y ₂ Selection period H ₁ In the inside, the voltage + 0.1V resulting from the parasitic capacitance is added to −5V, which is the voltage originally applied to the liquid crystal, to be −4.9V. Similarly, the selection period H _Three Scan line Y selected for _Three Then, selection period H ₂ Even during this period, the parasitic capacitance value + 0.1V is added to −5V, which is the voltage originally applied to the liquid crystal, to be −4.9V. Similarly, the scanning line Y _Four ~ Scanning line Y _M In each of these, a change in the voltage of the liquid crystal due to the parasitic capacitance occurs. Due to this parasitic capacitance, a period in which the voltage applied to the liquid crystal changes occurs. This change in voltage causes display unevenness due to flicker and vertical luminance gradient.
[0015]
An object of the present invention is to provide a liquid crystal device for solving the problem of low power consumption and being recognized as flicker when the voltage to be applied to the liquid crystal changes due to parasitic capacitance or the like, and its driving device And a driving method thereof and an electronic apparatus.
[0016]
[Means for Solving the Problems]
In order to solve the above problem, a liquid crystal device according to one embodiment of the present invention includes M rows (M is an integer of 2 or more) of scanning lines arranged along the first direction,
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction;
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
M × N pixel electrodes respectively connected to one of the M × N switching means;
M × N counter pixel electrodes disposed to face each of the M × N pixel electrodes through a liquid crystal layer;
Scanning line driving means for supplying a scanning signal for selecting at least one of the M rows of scanning lines to the M rows of scanning lines;
Data line driving means for supplying a data signal to each of the N columns of data lines;
Polarity inversion means for inverting the polarity of the voltage applied to the liquid crystal layer;
A first wiring of M rows and a second wiring of M rows arranged corresponding to each of the M rows of scanning lines;
Have
A potential is supplied from each of the M rows of first wirings to odd-numbered counter pixel electrodes in each row corresponding to the M rows of scanning lines,
A potential different from the potential supplied to the first wiring of the M row from each of the M wirings of the second row is applied to the even-numbered counter pixel electrode in each row corresponding to the scanning line of the M rows. Supply
The polarity inverting means synchronizes with the selection period in which the scanning line driving means selects the at least one scanning line, and each of the first wiring and the second wiring corresponding to the selected scanning line. It further has a means for changing the potential supplied to. The invention of claim 5 defines a driving device for a liquid crystal device, and the invention of claim 8 defines a driving method of the liquid crystal device.
[0017]
According to the liquid crystal device, the driving device thereof, and the driving method thereof according to the present invention, when the polarity of the voltage applied to the liquid crystal layer is inverted, the counter pixel is synchronized with the timing when each scanning line is selected. The voltage applied to the electrode is changed. Two wirings are arranged corresponding to one scanning line. In each of the N counter pixel electrodes corresponding to this one scanning line, the odd-numbered and even-numbered counter pixel electrodes are supplied with potentials from different wirings. By synchronizing the timing at which the potential is supplied from the wiring with the selection period, it is possible to suppress flicker due to the influence of the parasitic capacitance accumulated in the switching means and the wiring.
[0018]
In the liquid crystal device according to the present invention, different potentials are supplied to the adjacently arranged wirings in each of the M rows of the first wirings within the frame period. . In this case, for example, when the liquid crystal device is driven by dot inversion, flicker due to the influence of the parasitic capacitance accumulated in the switching means and the wiring can be suppressed as compared with the conventional case. Further, the counter electrode can be driven at a low frequency, and power consumption can be reduced.
[0019]
Further, in the liquid crystal device according to the present invention, the same potential is supplied to each of the adjacent wirings among the first wirings in the M rows within the frame period. . In this case, for example, when the liquid crystal device is driven on the source line, flicker due to the influence of the parasitic capacitance accumulated in the switching means and the wiring can be suppressed as compared with the conventional case.
[0020]
In the liquid crystal device according to the present invention, the polarity inversion means is
A first shift register to which an input signal of the first logic information or the second logic information is supplied and sequentially shifted;
A second shift register which is supplied with an input signal having a logic opposite to that of the input signal supplied to the first shift register and is sequentially shifted;
Based on the first logic information or the second logic information supplied from the first and second shift registers for each selection period, the M row first wiring and the M row second And a potential selection circuit for selecting a potential supplied to each of the wirings.
[0021]
By doing so, when the data signal voltage to the liquid crystal device is changed to AC and driven in polarity inversion, the potential of the counter pixel electrode can be changed at the same time.
[0022]
Further, in the substrate of the liquid crystal device according to the present invention, M rows (M is an integer of 2 or more) scanning lines arranged along the first direction;
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction;
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
A substrate opposed to an active matrix substrate having M × N pixel electrodes respectively connected to one of the M × N switching means, through a liquid crystal layer;
M × N counter pixel electrodes disposed to face each of the M × N pixel electrodes through a liquid crystal layer;
A first wiring of M rows connecting odd-numbered counter pixel electrodes in each of the M scanning lines;
Each of the M rows of scanning lines has M rows of second wirings connecting even-numbered counter pixel electrodes, and each of the M rows of first wirings and the M rows of second wirings. Are insulated from each other.
[0023]
By using the substrate having such a configuration for the liquid crystal device according to the present invention, the potential supplied to the counter pixel electrode can be easily controlled for each scanning line.
[0024]
In addition, the liquid crystal device according to the present invention can be applied to electronic devices.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
(First embodiment)
FIG. 1 is a block diagram of a liquid crystal device according to the present invention.
[0027]
The liquid crystal device includes a liquid crystal panel 10, a signal control circuit unit 12, a gradation voltage circuit unit 14, a power supply circuit unit 16, a scanning line driving circuit 20, a data line driving circuit 22, and a counter electrode driving circuit 24. In FIG. 1, the pixels formed on the liquid crystal panel 10 are defined as P (1,1) to P (m, n) to P (M, N). Each of m, n, and M is a natural number. Each scanning line is represented by Y, and each data line is represented by X. Of these scanning lines Y and data lines X, when specifying only a specific scanning line or data line, Y ₁ , Y ₂ , ... Y _m , ..., Y _M Or X ₁ , X ₂ , ..., X _n , ..., X _N Notation is as follows. The generic name of the counter electrode is represented by C. Among the counter electrodes C, each counter electrode is C ₁ , C ₂ , ..., C _m , ..., C _M When only a specific counter electrode is specified, C _1a , C _1b , C _2a , C _2b , ..., C _ma , C _mb , ..., C _Ma , C _Mb Notation is as follows.
[0028]
The connection relationship between the counter electrode C and the pixel P (m, n) is shown in FIG. FIG. 5A shows a scan line Y formed on the active matrix. ₁ And data line X ₁ The structure of the pixel P (1, 1) provided corresponding to the intersection with is shown. A pixel P (1, 1) on the active matrix substrate has a pixel electrode 32 and a storage capacitor 42 provided at the drain of the TFT 30. Other pixels have the same configuration as the pixel P (1, 1). Further, FIG. 5B shows the counter substrate 100 provided through the active matrix substrate and the liquid crystal layer. On the counter substrate 100, M × N counter pixel electrodes 102 are provided corresponding to each of the M × N pixels. On the counter substrate 100, the pixel P (m, n _c ) (N _c Is an odd number)) and M counter electrodes C wired respectively _ma , And pixel P (m, n _d ) (N _d Is an even number) M counter electrodes C connected and wired _mb Have
[0029]
The liquid crystal panel 10 includes (M × N) pixels. In one pixel (1, 1) in the liquid crystal panel 10, the data line X is connected to the source of the TFT 30. ₁ However, the gate G has a scanning line Y ₁ Are connected to each other. Data line X ₁ ~ X _N Is the data line driving circuit 22 and the scanning line Y ₁ ~ Y _M Are respectively driven by the scanning line driving circuit 20. A pixel electrode 32 is provided on the drain D of the TFT 30. With the pixel electrode 32 as one end, a pixel capacitor 40 charged with a voltage applied to the liquid crystal layer and a storage capacitor 42 for holding data are connected. The other ends of the pixel capacitor 40 and the holding capacitor 42 are connected to the counter electrode C. ₁ It is connected to the. Here, the counter electrode C ₁ Counter electrode C _1a And C _1b The other ends of the pixel capacitor 40 and the holding capacitor 42 are connected to the counter electrode C via the counter pixel electrode 102. _1a It is connected to the.
[0030]
In the liquid crystal panel 10, (M × N) pixels having the same configuration as the pixel P (1, 1) as described above are formed. Note that the pixel P (m, n _c ) (N _c Is the odd number), the other end of the pixel capacitor 40 and the holding capacitor 42 is the counter electrode C. _ma Pixel P (m, n _d ) (N _d Is the even number), the other end of the pixel capacitor 40 and the storage capacitor 42 is the counter electrode C. _mb Are connected to each.
[0031]
The liquid crystal device in FIG. 1 is supplied with a power supply, a data signal, a synchronization signal, and a clock signal from the outside.
[0032]
The signal control circuit unit 12 supplies the clock signal CLK 1, the data signal Da, and the horizontal synchronization signal Hsync to the data line driving circuit 22. The data signal Da is, for example, a digital signal for representing approximately 16.77 million colors with 8-bit RGB signals. The data line driving circuit 22 latches the data signal Da at the timing of the clock signal CLK1. The horizontal synchronization signal Hsync is supplied to the data line driving circuit 22 in synchronization with the latch of the data signal Da for one line. Based on the horizontal synchronization signal Hsync, the latched data signal Da for one line is analog-converted based on the reference voltage from the gradation voltage circuit unit 14, and then impedance-converted and supplied to each of the data lines X. Is done.
[0033]
Further, the signal control circuit unit 12 supplies the clock signal CLK <b> 2 and the vertical synchronization signal Vsync to the scanning line driving circuit 20. The scanning line driving circuit 20 sequentially switches the scanning line Y to be selected at the timing of the clock signal CLK2. In a selection period in which a specific scanning line Y is selected, a scanning signal voltage that turns on the gate of the TFT 30 connected to the scanning line is applied. This scanning signal voltage is defined as a scanning signal S. In addition, the scanning signal S is supplied from the selection period H at the beginning of the frame period. ₁ The scanning signal S supplied to ₁ Sequentially from S ₁ , S ₂ , ..., S _m , ..., S _M Define as follows. In synchronization with the scanning signal S, the data signal voltage Vd output from the data line driving circuit 22 is supplied to each of the data lines X. After one frame period when all the scanning lines X are scanned, the vertical synchronization signal Vsync is supplied to the scanning line driving circuit 20, and again, the first scanning line Y ₁ Are sequentially scanned.
[0034]
Further, as will be described later, the signal control circuit unit 12 supplies the clock signal CLK2 and the polarity inversion signal FR to the counter electrode drive circuit 24.
[0035]
The power supply circuit unit 16 supplies power to the gradation voltage circuit unit 14, the scanning line driving circuit 20, the data line driving circuit 22, and the counter electrode driving circuit 24. For example, the counter electrode driving circuit 24 supplies two types of voltages, for example, positive polarity + Vcom and negative polarity -Vcom, to the counter electrode C based on the supplied power.
[0036]
The counter electrode drive circuit 24 includes, for example, a shift register group 54 and a potential selection circuit 56 as shown in FIG. Although not shown, the potential selection circuit 56 includes a level shifter, a driver, and the like.
[0037]
The shift register group 54 is configured by, for example, M registers connected in series. In each of the shift registers 50 and 52, each register is indicated with a suffix 1 to M.
[0038]
Each time the clock signal CLK2 is supplied to the shift register group 54, the information stored in the shift registers 50 and 52 is shifted. The information stored in the shift register 50 is converted to analog by the potential selection circuit 56, amplified to a required voltage level, and supplied to each of the counter electrodes C.
[0039]
Here, a change with time t to (t + M) when the clock signal CLK2 is input to the shift register group 54 is shown in FIG. In FIG. 3, in the information “0”, the negative voltage −Vcom from the counter electrode driving circuit 24 and the positive voltage + Vcom from the counter electrode driving circuit 24 are applied to the counter electrode C in the information “1”. ₁ ~ C _M Supplied to each. This information “0” or “1” is determined by the polarity inversion signal FR. For example, in this embodiment, since the liquid crystal device is driven by the dot inversion method, the adjacent pixels have different polarities. That is, the counter electrode C _1a And a counter electrode C _1b The pixels connected to each have different polarities. Furthermore, the counter electrode C _1a And a counter electrode C _2a The pixels connected to each have different polarities. Therefore, different information is supplied to the shift register 50 and the shift register 52 by the polarity inversion signal FR.
[0040]
The operation of the counter electrode drive circuit 24 when the liquid crystal device is driven by the dot inversion method will be described below.
[0041]
At time t, information “1” is uniformly input to the shift register 50, and information “0” is uniformly input to the shift register 52. At time (t + 1), the information “1” in the register 50-1 is shifted to the register 50-2 by the clock signal CLK2. The information “0” in the register 52-1 is shifted to the register 52-2 by the clock signal CLK2. At the same time, the inverted information “0” is supplied to the register 50-1 and the inverted information “1” is supplied to the register 52-1 by the polarity inversion signal FR. At time t + 2, the information is further shifted by one stage by the clock signal CLK2, and the information “0” inverted in the register 50-1 and the information inverted in the register 52-1 by the polarity inversion signal FR. Each “1” is supplied. Similarly, the inversion information is supplied to each of the register 50-M and the register 52-M until time (t + M). Eventually, compared to time t, the information of all registers is inverted at time (t + M).
[0042]
Now, the timing chart of FIG. 4 will be described using the liquid crystal device of FIG. FIG. 4 shows a timing chart when the liquid crystal device according to the present invention is driven by the dot inversion method.
[0043]
Frame period f ₁ The scanning signal S supplied at the beginning of ₁ The selection period H ₁ Scan line Y ₁ Is selected. Data line X _c A positive data signal voltage + Vd is supplied to each of (c is an odd number). In synchronization with this, the counter electrode C _1a Is supplied with a negative voltage -Vcom. Data line X _d A negative data signal voltage -Vd is supplied to each of (d is an even number). In synchronization with this, the counter electrode C _1b Is supplied with a positive voltage + Vcom.
[0044]
Next, the scanning signal S ₂ The selection period H ₂ Scan line Y ₂ Is selected. Data line X _c A negative data signal voltage -Vd is supplied to each of (c is an odd number). In synchronization with this, the counter electrode C _2a Is supplied with a positive voltage + Vcom. Data line X _d A positive data signal voltage + Vd is supplied to each of (d is an even number). In synchronization with this, the counter electrode C _2b Is supplied with a negative voltage -Vcom.
[0045]
Similarly, the timing at which the voltage −Vcom is supplied from the counter electrode driving circuit 24 to each of the counter electrodes C is the same as the scanning signal S. _Three ~ S _M Each of them are synchronized. Frame period f ₂ The counter electrode drive circuit 24 is driven at the same timing in FIG.
[0046]
As described above, in the present embodiment, when the polarity of the voltage applied to the liquid crystal layer is inverted and driven, the voltage applied to the counter electrode is changed in synchronization with the timing when each scanning line is selected. Such an operation is performed by using two counter electrodes C for each scanning line. _ma And C _mb This is realized by using the liquid crystal panel 10 in which the counter electrode C of each adjacent pixel is connected to another counter electrode. When this liquid crystal device is driven by dot inversion as described above, it is possible to eliminate voltage fluctuations due to the influence of the parasitic capacitance accumulated in the switching means and wiring compared to the conventional case, and flicker caused by the voltage fluctuations can be eliminated. Can be suppressed. In addition, each driving cycle of the counter electrode can be set to 2 frame periods. For this reason, the counter electrode can be driven at a low frequency, and power consumption can be reduced.
[0047]
(Second Embodiment)
The operation of the liquid crystal device according to the present embodiment will be described with reference to the timing chart of FIG. FIG. 6 shows a timing chart when the liquid crystal device according to the present invention is driven by the source line inversion method. However, FIG. 6 shows the data line X for convenience. ₁ Each change of the pixels connected corresponding to is shown.
[0048]
Frame period f ₁ The scanning signal S supplied at the beginning of ₁ The selection period H ₁ Scan line Y ₁ Is selected. Data line X ₁ Is supplied with a positive data signal voltage + Vd. In synchronization with this, the counter electrode C _1a Is supplied with a negative voltage -Vcom.
[0049]
Next, the scanning signal S ₂ The selection period H ₂ Scan line Y ₂ Is selected. Data line X ₁ Is supplied with a positive data signal voltage + Vd. In synchronization with this, the counter electrode C _2a Is supplied with a negative voltage -Vcom.
[0050]
Similarly, the frame period f ₁ , The counter electrode C from the counter electrode drive circuit 24. _3a ~ C _Ma The timing at which the voltage −Vcom is supplied to each of _Three ~ S _M Are synchronized with each of the. Frame period f ₂ The counter electrode drive circuit 24 is driven at the same timing in FIG.
[0051]
As described above, in the present embodiment, when the polarity of the voltage applied to the liquid crystal layer is inverted and driven, the voltage applied to the counter electrode is changed in synchronization with the timing of selection of each scanning line Y. Such an operation is performed by using two counter electrodes C for each scanning line. _ma And C _mb This is realized by using the liquid crystal panel 10 in which the counter electrode C of each adjacent pixel is connected to another counter electrode. When this liquid crystal device is driven to invert the source line as described above, voltage fluctuation due to the influence of the parasitic capacitance accumulated in the switching means and wiring can be eliminated as compared with the conventional case, and the flicker caused by this voltage fluctuation is eliminated. Can be suppressed.
[0052]
(Third embodiment)
FIG. 7 shows a liquid crystal device according to a third embodiment of the present invention.
[0053]
A data signal, a synchronization signal, and a clock signal are supplied to the signal control circuit unit 112. The signal control circuit unit 112 supplies the clock signal CLKX, the horizontal synchronization signal Hsync1, and the data signal Db to the data line driving circuit 122. Further, the signal control circuit unit 112 supplies the clock signal CLKY and the vertical synchronization signal Vsync1 to the scanning line driving circuit 120. Further, the signal control circuit unit 112 supplies the polarity inversion signal FR and the clock signal CLKY to the counter electrode drive circuit 124.
The gradation voltage circuit unit 114 supplies a reference voltage to the data line driving circuit 122 in the same manner as the gradation voltage circuit unit 14 described above. The power supply circuit unit 116 supplies power to each device for driving the liquid crystal device, similarly to the power supply circuit unit 16 described above.
[0054]
Here, the vertical synchronization signal Vsync1 is a signal for determining each subfield defined by dividing one field (one frame). The polarity inversion signal FR supplies a signal whose level is inverted for each subfield to the counter electrode drive circuit 124. The clock signal CLKY is a signal for defining the horizontal scanning period S. The horizontal synchronization signal Hsync1 is a signal output after each line of RGB data signal Db is latched in the data line driving circuit 122 by the clock signal CLKX. Although not shown, the signal control circuit unit 112 includes a counter that counts the vertical synchronization signal Vsync1, and a signal supplied as the polarity inversion signal FR is determined based on the counter result.
[0055]
Here, the concept of the subfield will be described below.
[0056]
In the present embodiment, for example, it is assumed that the liquid crystal device shown in FIG. That is, the data signal Db is composed of RGB 3 bits. In such a liquid crystal device according to the present embodiment, the voltage applied to the liquid crystal layer is, for example, only binary values of voltage V0 (“L” level) and V7 (“H” level). In the case of a normally white liquid crystal panel, the transmittance is 100% when the voltage V0 is applied to the liquid crystal layer over the entire period of one field, and the transmittance is 0% when the voltage V7 is applied. Furthermore, by controlling the ratio of the period during which the voltage V0 is applied to the liquid crystal layer and the period during which the voltage V7 is applied in one field, a voltage corresponding to a halftone can be applied to the liquid crystal layer. . Therefore, one field f is divided into seven periods in order to separate the period during which the voltage V0 is applied to the liquid crystal layer and the period during which the voltage V7 is applied. This divided period is designated as subfield Sf. ₁ ~ Sf ₇ It is defined as
[0057]
For example, when the gradation data is (001) (when gradation display with a pixel transmittance of 14.3% is performed), if the voltage of the counter electrode C is 0 V, the selected pixel includes a sub-pixel. Field Sf ₁ The voltage V7 is applied. On the other hand, the other subfield Sf ₂ ~ Sf ₇ Then, the voltage V0 is applied. Here, the effective voltage value is obtained as a square root obtained by averaging the square of the instantaneous voltage value over one period (one field). That is, the subfield Sf ₁ Is for one field f (V1 / V7) ² Is set so that the effective voltage value applied to the liquid crystal layer within one field f is V1.
[0058]
Thus, the subfield Sf ₁ ~ Sf ₇ In this way, the voltage corresponding to the gradation data is applied to the liquid crystal layer, so that only the two values of the voltages V0 and V7 are supplied to the liquid crystal layer. Key display is possible.
[0059]
Now, the signal control circuit unit 112 converts the supplied RGB 3-bit data signal into the subfield Sf. ₁ ~ Sf ₇ Every time, it is converted into a binary signal Ds. The binary signal Ds is supplied to the data line driving circuit 122, and either the voltage V0 or V7 is applied to the liquid crystal layer as the data signal voltage Vd.
[0060]
FIG. 8 shows voltage waveforms of gradation data (000) to (111) applied to the liquid crystal layer. Corresponding to each gradation data, subfield Sf ₁ ~ Sf ₇ In each period, the voltage V7 (“H”) or the voltage V0 (“L”) is applied to the liquid crystal layer. For example, in the case of gradation data (001), the subfield Sf ₁ ~ Sf ₇ In this order, (HLLLLLLL) is applied to the liquid crystal layer.
[0061]
FIG. 9 is a diagram showing a timing chart of the operation of the liquid crystal device of FIG.
[0062]
In each subfield, the scanning signal S ₁ ~ S _M Is supplied as a subfield Sf that is set as the shortest subfield period. _Three Is set shorter.
[0063]
Subfield Sf ₁ Then, the scanning signal S ₁ Selection period H during which is supplied ₁ And data line X _c The data signal voltage + Vd is supplied to each of (c is an odd number). From the counter electrode drive circuit 124 to the counter electrode C _1a In addition, a voltage -Vcom having a polarity opposite to that of the data signal voltage + Vd is supplied. At the same time, data line X _d The data signal voltage -Vd is supplied to each of (d is an even number). From the counter electrode drive circuit 124 to the counter electrode C _1b In addition, a voltage + Vcom having a polarity opposite to that of the data signal voltage −Vd is supplied.
[0064]
Scanning signal S ₂ Selection period H during which is supplied ₂ Data line X _c The data signal voltage −Vd is supplied to each of (c is an odd number). From the counter electrode drive circuit 124 to the counter electrode C _2a In addition, a voltage + Vcom having a polarity opposite to that of the data signal voltage −Vd is supplied. At the same time, data line X _d The data signal voltage + Vd is supplied to each (d is an even number). From the counter electrode drive circuit 124 to the counter electrode C _2b In addition, a voltage -Vcom having a polarity opposite to that of the data signal voltage + Vd is supplied.
[0065]
Similarly, the scanning signal S _M Selection period H during which is supplied _M Until then, the polarity of the counter electrode changes in synchronization with the timing. Such an operation is performed in the subfield Sf in the frame period f. ₁ ~ Sf ₇ Is done. Frame period f ₂ Then, the previous frame period f ₁ A voltage is supplied so as to be different from the polarity of each pixel.
[0066]
Even when the liquid crystal device is driven in this way, a voltage applied to the liquid crystal layer due to parasitic capacitance or the like generated when the polarity of the counter electrode C is inverted by the polarity inversion signal FR in synchronization with the beginning of the frame period. The change of can be suppressed.
[0067]
Furthermore, in the related art, when the polarity of the voltage of the counter electrode is inverted, the frame period f is divided into a plurality of subfields, and therefore, the frequency for driving the counter electrode drive circuit 124 is increased in proportion thereto. However, in this embodiment, since the counter electrode C has a structure as shown in FIG. 5, each counter electrode can be driven when a corresponding scanning line is selected. For this reason, the frequency at which the counter electrode driving circuit 124 drives the counter electrode can be suppressed, and power consumption can be reduced.
[0068]
In the above-described embodiment, the scanning line Y is selected one by one. However, when a plurality of scanning lines are selected and driven, the selected scanning line is synchronized with the scanning line selection period. The same effect can be obtained by driving the counter electrode in each row corresponding to.
[0069]
Further, the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described TFT type liquid crystal device, but can also be applied to an image display device using a plasma display device or the like.
[0070]
The present invention can be applied to all electronic devices having a liquid crystal device. For example, various electronic devices such as a mobile phone, a game device, an electronic notebook, a personal computer, a word processor, a television, and a car navigation device can be used.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a liquid crystal device according to a first embodiment.
2 is a diagram illustrating an example of a configuration of a counter electrode driving circuit of the liquid crystal device of FIG. 1;
3 is a diagram for explaining the operation of the counter electrode drive circuit of FIG. 2; FIG.
4 is a timing chart of the operation of the liquid crystal device in FIG. 1. FIG.
FIG. 5A is a diagram showing pixels formed on an active matrix substrate. (B) It is a figure which shows the counter electrode board | substrate utilized by this invention.
FIG. 6 is a diagram illustrating a timing chart of the operation of the liquid crystal device according to the second embodiment.
FIG. 7 is a diagram illustrating a liquid crystal device according to a third embodiment.
8 is a diagram illustrating an example of a data signal Ds generated by a signal control circuit unit of the liquid crystal device of FIG.
9 is a diagram showing a timing chart of the operation of the liquid crystal device of FIG.
FIG. 10 is a diagram showing a configuration of a conventional counter electrode substrate.
11 is a diagram illustrating a timing chart when the liquid crystal device is driven to perform dot inversion using the counter electrode substrate illustrated in FIG. 10;
12 is a diagram showing another timing chart when the liquid crystal device is driven to invert dots using the counter electrode substrate shown in FIG.
13 is a timing chart when the liquid crystal device is driven in a source line inversion using the counter electrode substrate shown in FIG.
FIG. 14 is a diagram for explaining a parasitic capacitance of a TFT.
[Explanation of symbols]
10 LCD panel
12, 112 Signal control circuit section
14,114 gradation voltage circuit
16,116 Power supply circuit section
20, 120 Scan line drive circuit
22, 122 Data line driving circuit
24, 124 Counter electrode drive circuit
30 TFT
32 pixel electrodes
40 pixel capacity
42 Retention capacity
50, 52 shift register
54 Shift register group
56 Potential selection circuit
100, 110 Counter substrate
102 Counter pixel electrode

Claims (7)

Scanning lines of M rows (M is an integer of 2 or more) arranged along the first direction;
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction;
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
M × N pixel electrodes respectively connected to one of the M × N switching means;
M × N counter pixel electrodes disposed to face each of the M × N pixel electrodes through a liquid crystal layer;
Scanning line driving means for supplying a scanning signal for selecting at least one of the M rows of scanning lines to the M rows of scanning lines;
Data line driving means for supplying a data signal to each of the N columns of data lines;
Polarity inversion means for inverting the polarity of the voltage applied to the liquid crystal layer;
A first wiring of M rows and a second wiring of M rows arranged corresponding to each of the M rows of scanning lines;
Have
A potential is supplied from each of the M rows of first wirings to odd-numbered counter pixel electrodes in each row corresponding to the M rows of scanning lines,
A potential different from the potential supplied to the first wiring of the M row from each of the M wirings of the second row is applied to the even-numbered counter pixel electrode in each row corresponding to the scanning line of the M rows. Supply
The polarity inversion means is
A first shift register to which the first input signal of the first logic information or the second logic information is supplied, and the first input signal is sequentially shifted;
A second shift register to which a second input signal having a logic opposite to that of the first input signal supplied to the first shift register is supplied, and the second input signal is sequentially shifted;
Based on the first logic information or the second logic information supplied from the first and second shift registers for each selection period, the M row first wiring and the M row second A potential selection circuit that selects a potential to be supplied to each of the wirings;
Have
The output of the potential selection circuit based on the information from the first shift register is input to the odd number of the first wiring in the M row and the even number of the second wiring in the M row,
The output of the potential selection circuit based on the information from the second shift register is input to the even number of the first wiring in the M row and the odd number of the second wiring in the M row,
Among the first wirings in the M rows, the potentials of adjacent wirings are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. Let
Among the second wirings in the M rows, the potentials of the wirings arranged adjacent to each other are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. a liquid crystal device, characterized in that letting. In claim 1,
  A signal control circuit for converting the data signal into a binary signal for each subfield obtained by dividing one field into a plurality of subfields;
The scanning line driving means supplies a scanning signal including a scanning period for selecting at least one of the M rows of scanning lines to the M rows of scanning lines in each of the subfields,
The data line driving means supplies a binary voltage to the N data lines based on a binary signal from the signal control circuit,
The polarity inverting means changes the voltage supplied to the counter electrode of the row corresponding to the selected scanning line for each subfield, thereby inverting the polarity of the voltage applied to the liquid crystal layer. A liquid crystal device characterized by the above. An electronic apparatus comprising the liquid crystal device according to claim 1. Scanning lines of M rows (M is an integer of 2 or more) arranged along the first direction;
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction;
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
M × N pixel electrodes respectively connected to one of the M × N switching means;
M × N counter pixel electrodes disposed to face each of the M × N pixel electrodes through a liquid crystal layer;
A first wiring of M rows for supplying a potential to odd-numbered counter pixel electrodes in each row of the M scanning lines;
In each row of the M scanning lines, a liquid crystal display panel having an even-numbered counter pixel electrode and an M-row second wiring that supplies a potential different from the potential supplied to the odd-numbered counter pixel electrode. A driving device for driving
Scanning line driving means for supplying a scanning signal for selecting at least one of the M rows of scanning lines to the M rows of scanning lines;
In synchronization with the selection period for selecting by Ri before Symbol least one scanning line to the scanning line drive circuit, it is supplied to each of the first wiring and the second wiring corresponding to the selected scanning line Polarity inversion means for changing the potential;
Have
The polarity inversion means is
A first shift register to which the first input signal of the first logic information or the second logic information is supplied, and the first input signal is sequentially shifted;
A second shift register to which a second input signal having a logic opposite to that of the first input signal supplied to the first shift register is supplied, and the second input signal is sequentially shifted;
Based on the first logic information or the second logic information supplied from the first and second shift registers for each selection period, the M row first wiring and the M row second A potential selection circuit that selects a potential to be supplied to each of the wirings;
Have
The output of the potential selection circuit based on the information from the first shift register is input to the odd number of the first wiring in the M row and the even number of the second wiring in the M row,
The output of the potential selection circuit based on the information from the second shift register is input to the even number of the first wiring in the M row and the odd number of the second wiring in the M row,
Among the first wirings in the M rows, the potentials of adjacent wirings are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. Let
Among the second wirings in the M rows, the potentials of the wirings arranged adjacent to each other are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. A drive device characterized by being caused to. In claim 4,
  A signal control circuit for converting the data signal into a binary signal for each subfield obtained by dividing one field into a plurality of subfields;
The scanning line driving means supplies a scanning signal including a scanning period for selecting at least one of the M rows of scanning lines to the M rows of scanning lines in each of the subfields,
The data line driving means is configured to output the N columns of data based on the binary signal from the signal control circuit. To supply a binary voltage to the wire,
The polarity inversion means changes the voltage supplied to the counter electrode of the row corresponding to the selected scanning line for each subfield, thereby inverting the polarity of the voltage applied to the liquid crystal layer. A drive device. Scanning lines of M rows (M is an integer of 2 or more) arranged along the first direction;
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction;
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
M × N pixel electrodes respectively connected to one of the M × N switching means;
M × N counter pixel electrodes disposed to face each of the M × N pixel electrodes through a liquid crystal layer;
A first wiring of M rows for supplying a potential to odd-numbered counter pixel electrodes in each row of the M scanning lines;
A second wiring of M rows for supplying a potential different from the potential supplied to the odd-numbered counter pixel electrode to the even-numbered counter pixel electrode in each of the M rows of scanning lines;
Polarity inversion means for inverting the polarity of the voltage applied to the liquid crystal layer;
Have
The polarity inversion means is
A first shift register to which the first input signal of the first logic information or the second logic information is supplied, and the first input signal is sequentially shifted;
A second shift register to which a second input signal having a logic opposite to that of the first input signal supplied to the first shift register is supplied, and the second input signal is sequentially shifted;
Based on the first logic information or the second logic information supplied from the first and second shift registers for each selection period, the M row first wiring and the M row second A potential selection circuit that selects a potential to be supplied to each of the wirings;
A method of driving a liquid crystal device having
A scanning signal for selecting at least one of the M rows of scanning lines is supplied to the M rows of scanning lines;
The output of the potential selection circuit based on the information from the first shift register is input to the odd number of the first wiring in the M row and the even number of the second wiring in the M row,
The output of the potential selection circuit based on the information from the second shift register is input to the even number of the first wiring in the M row and the odd number of the second wiring in the M row,
Among the first wirings in the M rows, the potentials of adjacent wirings are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. Let
Among the second wirings in the M rows, the potentials of the wirings arranged adjacent to each other are changed to different potentials in synchronization with the timing for selecting the scanning lines in the M rows within one field period. driving wherein the Rukoto is. In claim 6,
A signal control circuit for converting the data signal into a binary signal for each subfield obtained by dividing one field into a plurality of subfields;
The scanning line driving means supplies a scanning signal including a scanning period for selecting at least one of the M rows of scanning lines to the M rows of scanning lines in each of the subfields,
Based on the binary signal from the signal control circuit, the data line driving means supplies a binary voltage to the N columns of data lines,
By the polarity inverting means, said each subfield, by changing the voltage supplied to the counter electrode of the row corresponding to the selected scanning line, by inverting the polarity of the voltage applied to the liquid crystal layer A driving method characterized by the above.

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