JP3752052B2 - Code phase acquisition circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a code phase acquisition circuit that is used in conjunction with a code phase locked loop that establishes and maintains code phase synchronization for a spread spectrum received signal to narrow the phase of the PN code associated with the received signal.
[0002]
[Prior art and its problems]
GNSS (Global Navigation Satellite System), represented by GPS (Global Positioning System), GLONASS (Global Orbiting Navigation Satellite System), etc., is a vehicle, ship, aircraft, etc. It is a system that has been widely used in recent years. GNSS is generally a space part composed of a predetermined number of positioning satellites in earth orbit, a user part composed of a satellite positioning device mounted on a moving object on the earth or carried by a human, and a system It consists of a control part that manages the operation of The positioning satellite transmits navigation data indicating the orbit and transmission time of the positioning satellite to the earth as a signal that has been spectrum-spread by a pseudo noise (PN) code. The satellite positioning device demodulates the navigation data by despreading the signal received from the positioning satellite with the PN code having the same content as the PN code used for the spectrum spreading by the positioning satellite, and more than the necessary number Navigation data is collected from positioning satellites, and based on the results, its own position and moving speed are obtained.
[0003]
FIG. 5 shows an example configuration of a satellite positioning device. In the apparatus of this figure, prior to the signal processing in the signal processing unit 40, the signal transmitted from the positioning satellite and received by the antenna 10 is subjected to processing such as frequency conversion and amplification by the frequency conversion unit 20, and further A / D The received signal is converted into digital data by the conversion unit 30. The signal processing unit 40 has N reception channels 41-i (i = 1, 2,... N), and each reception channel 41-i demodulates navigation data from a reception signal converted into digital data. . Each reception channel 41-i establishes and further maintains carrier synchronization and code synchronization with respect to a reception signal from one of the positioning satellites that are currently visible and selected by the control / calculation unit 50 for positioning calculation. It is controlled by the control / arithmetic unit 50. Each reception channel 41-i supplies navigation data obtained from the positioning satellite to the control / calculation unit 50 in a state where carrier synchronization and code synchronization are established and maintained. The number N of reception channels 41-i is determined according to the number of positioning satellites necessary for the positioning calculation, that is, the navigation data is collected simultaneously from the positioning satellites more than the number necessary for the control / calculation unit 50 to perform the positioning calculation. It is set to be able to. Based on the navigation data obtained from the signal processing unit 40, the control / calculation unit 50 obtains the distance to the positioning satellite (referred to as a pseudorange because it includes an error) and the positions of the positioning satellites, and obtains the positioning satellites for a predetermined number or more. The position (user position) of the satellite positioning device is obtained from the pseudo distance and the position, and the moving speed (user speed) of the satellite positioning device is obtained based on the information on the Doppler shift obtained in the carrier synchronization control. The output unit 60 outputs the user position and moving speed obtained by this calculation, that is, the positioning calculation, in the form of video or audio.
[0004]
FIG. 6 shows an example configuration of the reception channel 41-i. The configuration shown in this figure is a configuration that can form a synchronized loop (carrier synchronized loop) related to the carrier frequency and / or phase and a synchronized loop (code (phase) synchronized loop) related to the code phase.
[0005]
First, the carrier synchronization loop can be formed by the control / calculation unit 50, the carrier generator 41a, the carrier comparator 41b, and the integration unit 41e. That is, the carrier generator 41a generates an internal carrier having a frequency and / or phase commanded from the control / calculation unit 50, and the carrier comparator 41b compares the frequency and phase of the received signal with the frequency and phase of the internal carrier. Then, the comparison result is fed back to the control / arithmetic unit 50 via the integration unit 41e that stabilizes the loop. In the carrier comparator 41b, information indicating the frequency / phase error of the internal carrier with respect to the carrier related to the received signal is obtained. By doing so, the frequency and phase of the internal carrier can be synchronized with the received signal (carrier synchronization).
[0006]
The code phase locked loop can be formed by the control / arithmetic unit 50, the code generator 41c, the code comparator 41d, and the integration unit 41e. That is, the code generator 41c generates an internal PN code for despreading having the same content as the spreading PN code used in the positioning satellite and having a phase commanded from the control / calculation unit 50, and the code comparator 41d Compares the phase of the received signal with the phase of the internal PN code and feeds back the result to the control / arithmetic unit 50 via the integrating unit 41e. In the code comparator 41d, information indicating the phase error of the internal PN code with respect to the PN code related to the received signal, in other words, information indicating the degree of correlation of the internal PN code with respect to the received signal is obtained. The control / arithmetic unit 50 generates a command for the code generator 41c in a direction in which the degree of correlation increases, whereby the phase of the internal PN code can be synchronized with the received signal (code synchronization). In a state where carrier synchronization and code synchronization are established, the output of the integration unit 41e is a signal indicating navigation data.
[0007]
The carrier synchronization and code synchronization as described above have been established immediately after the power is turned on, or immediately after receiving a signal from a positioning satellite that has been blocked by the building until the user moves. Absent. Therefore, processing for establishing these synchronizations is necessary. FIG. 7 shows an outline of processing executed by the control / calculation unit 50 and the reception channel 41-i for code synchronization. As shown in this figure, the control / arithmetic unit 50 gives an instruction regarding the phase of the internal PN code to the code generator 41c (100), the comparison result in the code comparator 41d (102), and the integration unit 41e. (104). The control / arithmetic unit 50 generates a command to shift the phase of the internal PN code by one chip (106), and repeats the same operation. The chip here means each bit constituting the PN code. For example, in the C / A code among the PN codes used in GPS, one repetition period of the PN code is 1023 chips. Hereinafter, the number of chips included in one repetition period is represented by n (n: a natural number of 2 or more). When the above steps 100 to 106 are repeated n times, that is, when the phase of the internal PN code is rotated once (108), the control / arithmetic unit 50 is the most out of n code comparison results obtained. The phase relating to the one giving a large degree of correlation is selected and detected, and a command is given to the code generator 41c based on this phase (110). The code generator 41c shifts to the state where the code phase synchronization is established with the commanded phase as the initial phase (112). Thereafter, the control state in which the code synchronization loop is held, that is, the tracking state, is set so that the code phase error is suppressed.
[0008]
The problem with the configuration shown in FIGS. 5 to 7 is that the time required for establishing the code phase synchronization is long. That is, when the code phase synchronization is established by using the code synchronization loop and the same or similar procedure as the control in the tracking state, it takes time to obtain the degree of correlation. Specifically, in order to obtain the degree of correlation between the internal PN code of a certain phase value and the received signal, it is necessary to input the received signal for at least one repetition period of the PN code, which is shifted by one chip from the phase value. In order to obtain the degree of correlation with respect to the internal PN code having a phase value, it is necessary to input a reception signal for at least one PN code repetition period, and so on. The received signal is required. This is because the phase difference of the despreading PN code with respect to the received signal must be suppressed to at least one chip in order to obtain a sufficiently high correlation value and to properly demodulate the data. Therefore, all n correlations must be obtained. By not becoming. Here, if the GPS C / A (Coarse Acquisition) code is taken as an example, the chip rate = 1.023 MHz, n = 1023, and therefore 1 repetition period = 1023 / 1.023 MHz = 1 msec. For execution, at least 1 msec × n = 1023 msec is required.
[0009]
SUMMARY OF THE INVENTION
One of the objects of the present invention is to realize a code phase synchronization circuit capable of establishing code phase synchronization with a signal from a positioning satellite or the like at a higher speed than conventional. One of the objects of the present invention is to achieve the above-described object and apply the result to a satellite positioning device to improve the positioning rate, to quickly resume positioning when returning from reception interruption due to the shadow of a building, etc. It is to enable realization of the satellite positioning device.
[0010]
The code phase acquisition circuit according to the present invention sequentially shifts the phase of the despreading PN code having the same content as the spreading PN code so that the correlation value between the received signal and the despreading PN code continues to exceed a predetermined level. By variably setting, it is used together with a code phase locked loop that maintains the phase synchronization of the despreading PN code with respect to the received signal that has been spread spectrum using the spreading PN code during transmission. Its features, when PN code phase of the received signal is not yet identified, while retaining the received signal, a plurality of initial capture PN mutually different phases in the same content as part of any PN code for spreading A code is generated, a plurality of generated initial acquisition PN codes are held in a register, and a correlation value between a plurality of initial acquisition PN codes held in the register and a held reception signal is obtained The initial acquisition unit that selects the maximum initial acquisition PN code, and the initial phase of the despreading PN code for the code phase locked loop based on the phase of the initial acquisition PN code selected by the initial acquisition unit And a control unit that establishes the phase synchronization by instructing the phase.
[0011]
As described above, in the present invention, the received signal is held in the initial acquisition unit, and the initial phase of the despreading PN code is set based on the code phase detected from the received signal. In addition, it is possible to establish code phase synchronization with respect to a received signal transmitted from a positioning satellite or the like. That is, unlike the prior art in which the phase of the despreading PN code is changed and the code phase synchronization with the received signal is established, the number of chips of the despreading PN code as the internal PN code × the despreading PN code A long time of one cycle length is not spent for establishing the code phase synchronization. For example, the code phase synchronization can be established in a short time of two repetition periods of the despreading PN code.
[0012]
Further, when realizing the present invention, the initial acquisition unit executes the calculation of the correlation value between the initial acquisition PN code and the held received signal simultaneously in parallel for a plurality of initial acquisition PN codes. It is desirable to adopt such a configuration. With such a configuration, the time required for detecting the code phase related to the received signal is further shortened. More preferably, the control means provides the initial acquisition unit with the number of initial acquisition PN codes and / or the number of chips for which the correlation value calculation with the held received signal should be executed simultaneously and in parallel. It is desirable to have a configuration that instructs. By adopting such a configuration, it is possible to perform control such that the detection of the code phase related to the received signal and the time required for establishing the code phase synchronization can be shortened as necessary.
[0013]
In the present application, the present invention is expressed as an invention related to a “code phase acquisition circuit”. However, the present invention can also be expressed as, for example, “code phase acquisition method”, “satellite positioning device”, and the like. . Modifications to these representations will be readily apparent to those skilled in the art with reference to the present disclosure. In the following description, GPS is assumed, and a C / A code is assumed as a PN code to be used. However, the present invention can be applied to other types of GNSS and PN codes. Hereinafter, the present invention will be described in detail by presenting embodiments.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of a satellite positioning device according to an embodiment of the present invention. In the apparatus shown in this figure, a signal processing unit 40A including an initial acquisition unit 42 is used in addition to the reception channels 41-1, 41-2,... 41-N. In addition, the control function of the control / arithmetic unit has been partially modified along with the addition of the initial capturing unit 42. Therefore, in FIG. 1, the control / arithmetic unit is represented by reference numeral 50A.
[0015]
FIG. 2 shows an exemplary configuration of the initial capturing unit 42 in this embodiment. In the figure, the carrier generator 42a receives a command regarding the frequency and / or phase from the control / calculation unit 50A, generates an internal carrier for initial acquisition having the commanded frequency and / or phase, and sends it to the carrier comparator 42b. Supply. The carrier comparator 42b compares the frequency and / or phase of the received signal supplied from the A / D converter 30 with the frequency and / or phase of the internal carrier supplied from the carrier generator 42a, and compares the result. A signal representing the signal is supplied to the signal holder 42c. The signal holder 42c is configured by a member such as a shift register or a RAM, and holds data supplied via the carrier comparator 42b for at least one repetition period of the PN code. On the other hand, the code generator 42d generates an initial acquisition PN code having the same contents as the PN code used in the spectrum spreading by the positioning satellite, and supplies it to the code comparator 42e. The code comparator 42e compares the received signal held in the signal holder 42c with the initial acquisition PN code supplied from the code generator 42d, determines the degree of correlation between the two, and obtains the maximum result. Supply to the value detector 42g. The comparison controller 42f finally determines the initial acquisition PN code at the time of comparison in the code comparator 42e so that comparison results can be obtained for n or more initial acquisition PN codes whose phases are shifted by one chip from each other. Shift the phase sequentially. The maximum value detector 42g detects the comparison result Cmax giving the maximum degree of correlation among the n or more comparison results and the code phase Pmax giving the comparison result Cmax, and supplies them to the control / calculation unit 50A.
[0016]
FIG. 3 shows an example functional configuration of the signal holder 42c and the code comparator 42e in this embodiment. As shown in this figure, the signal holder 42c has a pair of registers 42h each having a size of M bits. The register 42h holds signals output from the carrier comparator 42b, that is, I-phase and Q-phase signals related to orthogonal carriers. The size M of the register 42h is a value equal to or greater than the number of chips n included in one repetition period of the PN code used in the positioning satellite, for example, 2n. On the other hand, the code comparator 42e has m registers 42i for holding the initial acquisition PN code supplied from the code generator 42d. The size k of each register 42i is set to satisfy 1 ≦ k ≦ n, and each register 42i holds a k-chip code extracted from the n-chip initial acquisition PN code. Further, the second register 42i is shifted by one chip with respect to the first register 42i, and so on. The contents of the code held in each register 42i are shifted by one chip. As will be described later, in this embodiment, the PN code related to the received signal is compared with the output of the carrier comparator 42b held by the register 42h and the signal related to the initial acquisition PN code held by the register 42i. Therefore, a relationship of km ≧ n is provided between the size k of the register 42i and the number m of the registers 42i. In the present embodiment, the register 42i is configured by m independent registers, but the same function can be realized by using one (k + m) stage shift register.
[0017]
The code comparator 42e further includes a comparator 42j that compares the contents of the register 42h with the contents of the register 42i. For example, the comparator 42j shown at the top in the figure receives a series of k chips of signals held in the register 42h related to the I phase, while being generated by the code generator 42d. A part of a series of k chips held in the first register 42i in the initial acquisition PN code is input and compared. Also, the comparator 42j shown second from the top in the figure is different from the comparator 42j shown first, not from the register 42h related to the I phase but from the register 42h related to the Q phase to k. The signal for the chip is input and compared with the signal held in the first register 42i. An absolute value calculator 42k is provided at the subsequent stage of each comparator 42j. Further, the output of the absolute value calculator 42k related to the pair of comparators 42j receiving signals from the same register 42i is sent to the adder 42l. Are added. Further, the number of sets of the pair of comparators 42j, the pair of absolute value calculators 42k, and the one adder 42l is equal to the number m of the registers 42i. Therefore, the output of each adder 42l represented by C ₁ , C ₂ ,... C _{m in the} figure compares the contents of the corresponding register 42i with the k chip of the I-phase output of the carrier comparator 42b. The absolute value obtained as a result of comparing the contents of the register 42i with the k-chip of the Q-phase output of the carrier comparator 42b is added. Further, the outputs C ₁ , C ₂ ,... C _m of each adder 42l have different values corresponding to the fact that the contents of the corresponding registers 42i are shifted by one chip.
[0018]
Thus, for to seek _{C 1, C 2, ... C} m serving comparison result by adding thereto the absolute values of the results was performed divided into the I-phase and Q-phase, carrier phase This is so that the maximum comparison result Cmax can be suitably specified regardless of any value of 0 to 2π [rad], and a signal that constantly reverses the phase of the navigation data, such as GPS. However, this is because the maximum comparison result Cmax is preferably obtained. Also, the size k of the register 42i used in FIG. 3 determines the number of chips used for simultaneous comparison among the signals held in the register 42h, and the number m of the registers 42i is used for simultaneous comparison. This indicates the number of codes provided that are out of phase with each other by one chip. In the following description, k is the number of simultaneous comparison chips, and m is the number of simultaneous comparison codes.
[0019]
FIG. 4 shows the flow of code phase synchronization establishment in this embodiment. As shown in this figure, first, the signal holder 42c of the initial acquisition unit 42 inputs and holds the I-phase and Q-phase outputs of the carrier comparator 42b for at least one repetition period of the PN code (200) and compares them. The controller 42f receives a command regarding the simultaneous comparison code number m and the simultaneous comparison chip number k from the control / calculation unit 50 (202). Based on the commanded simultaneous comparison code number m and simultaneous comparison chip number k, the comparison controller 42f is shifted in phase by 1 chip to each of the registers 42i in the code comparator 42e, and the width thereof is k chips. A certain number of m initial acquisition PN codes (strictly, a part thereof) are held. The code comparator 42e compares the signal on the register 42h and the signal on the register 42i using the comparator 42j, the absolute value calculator 42k, and the adder 42l under the control of the comparison controller 42f. (204). The code comparator 42e sequentially performs the comparison process for each of the m registers 42i (205), and completes the comparison process for all the registers 42i (206). 207) and steps 204 to 206 are repeatedly executed. As a result of the repetition, when the comparison process is finally completed for (n / k) × (n / m), and therefore, n or more phases (208), the maximum value detector 42g is The above-described Cmax and Pmax are obtained from the collected (n / k) × (n / m) comparison results, and the results are output to the control / arithmetic unit 50A (210). The control / arithmetic unit 50A commands Pmax thus obtained, that is, the code phase related to the received signal, to the code generator 41c constituting the receiving channel 41-i as an initial phase (212). As a result, the reception channel 41-i establishes code phase synchronization and transitions to the tracking state (214).
[0020]
Here, when executing the processing shown in FIG. 4, first, the signal holder 42c spends a time corresponding to one repetition period of the PN code in order to hold the received signal. Next, a comparison process is executed for a total of n or more initial acquisition PN codes having phases different from each other by one chip. Since this comparison process is repeated for the received signal held by the signal holder 42c, the code phase is detected using the code phase locked loop for a long time as in the prior art. Is never needed. Specifically, the process can be completed within a time corresponding to one repetition period of the PN code. Therefore, the time required to establish the code phase synchronization in the procedure of FIG. 4 is as short as 2 msec or less when the GPS C / A code is taken as an example. In particular, when the size M of the register 42h constituting the signal holder 42c is doubled the number n of PN code chips, the register 42h sequentially holds signals for one cycle used for repetition of comparison processing. Since it becomes possible to capture the output of the carrier comparator 42b, the situation where the comparison processing cannot be performed because the signal for one repetition period of the PN code has not yet been input from the carrier comparator 42b is after the start of circuit use. The result of the comparison process can be obtained for each repetition period. Furthermore, by setting the number m of simultaneous comparison codes and the number k of simultaneous comparison chips instructed by the control / calculation unit 50A to the comparison controller 42f to appropriate natural numbers of 2 or more, a plurality of initial values are obtained in step 204. Since the comparison process can be completed for the capture PN code at a time, the time required to complete the process shown in FIG. 3 can be further shortened. For example, taking the GPS C / A code as an example, when k = 1023 and m = 1023, the processing shown in FIG. 3 is performed with the number of executions of step 204 of 1023 / m × 1023 / k = about once. Can be realized. In the above description, the initial acquisition PN code is sequentially shifted by one chip. However, a smaller shift width such as 0.5 chip or 0.1 chip may be used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a satellite positioning device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a processing capturing unit in this embodiment.
FIG. 3 is a block diagram showing an example functional configuration of a signal holder code and a code comparator in this embodiment.
FIG. 4 is a flowchart showing a flow of processing for establishing code phase synchronization in this embodiment.
FIG. 5 is a block diagram showing a configuration of a satellite positioning device according to a conventional technique.
FIG. 6 is a block diagram showing a configuration of each reception channel.
FIG. 7 is a flowchart showing a flow of processing for establishing code phase synchronization in the prior art.
[Explanation of symbols]
40A signal processing unit, 41-1, 41-2, ... 41-N reception channel, 41a, 42a carrier generator, 41b, 42b carrier comparator, 41c, 42d code generator, 41d, 42e code comparator, 41e integration Section, 42f comparison controller, 42g maximum value detector, 50A control / calculation section.

Claims (4)

For the spread at the time of transmission, the phase of the despreading PN code having the same content as the spreading PN code is successively variably set so that the correlation value between the received signal and the despreading PN code continues to exceed a predetermined level. Used with a code phase locked loop that maintains the phase synchronization of the despreading PN code with respect to the received signal being spread spectrum using the PN code;
When PN code phase of the received signal is not yet identified, while retaining the received signal, either to generate a plurality of initial acquisition PN code for the different phases in the same content as the portion of the PN code for spreading The generated plurality of initial acquisition PN codes are held in a register, and the initial correlation value between the received signals held in the register is maximized among the plurality of initial acquisition PN codes held in the register. An initial capture unit for selecting a capture PN code;
Control means for establishing the phase synchronization by commanding the initial phase of the despreading PN code to the code phase locked loop based on the phase of the initial acquisition PN code selected by the initial acquisition unit; ,
A code phase acquisition circuit comprising: The code phase acquisition circuit of claim 1,
A code phase acquisition, wherein the initial acquisition unit executes a calculation of a correlation value between an initial acquisition PN code and a held received signal in parallel for a plurality of initial acquisition PN codes. circuit. The code phase acquisition circuit of claim 2,
A code phase characterized in that the control means instructs the initial acquisition unit the number of PN codes for initial acquisition to be executed simultaneously and in parallel for calculating a correlation value with a held received signal. Capture circuit. The code phase acquisition circuit according to claim 2 or 3,
Code phase acquisition characterized in that the control means instructs the initial acquisition unit the number of PN code chips for initial acquisition to be executed simultaneously and in parallel with calculation of a correlation value with a held received signal circuit.

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