JP3754294B2 - Method for manufacturing silicon carbide single crystal substrate and method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a vapor phase growth technique for 3C (cubic) SiC single crystal, and more particularly, a method for manufacturing a 3C-SiC single crystal substrate having excellent crystallinity, which is desirable for manufacturing a semiconductor element, and the substrate. The present invention relates to a method for manufacturing a used semiconductor device.
[0002]
[Prior art]
Conventionally, SiC (silicon carbide) is grown by bulk crystal growth by a sublimation method and thin film formation by vapor phase epitaxial growth method in which SiC is produced by supplying a raw material gas of a Si compound and a raw material gas of a C compound onto a substrate. And has been classified.
[0003]
In bulk crystal growth by the sublimation method, <0001> growth of hexagonal 6H SiC, which is a polymorph of the high-temperature stable phase, and hexagonal but slightly low-temperature 4H SiC is possible. Such (0001) SiC substrates have been sold. However, the density of defects called microvibration is still high, and it is difficult to expand the substrate area.
[0004]
On the other hand, when the vapor phase epitaxial growth method on a single crystal substrate is used, the controllability of impurity addition is remarkably improved, and an epitaxial growth film having a large area can be easily obtained by expanding the substrate area. The vibration density can be reduced. However, in the vapor phase epitaxial growth method, an increase in defect density due to a difference in lattice constant between the substrate material and the SiC film often becomes a problem. In particular, since Si, which is a general substrate used for growth, has a large lattice constant difference from SiC, twins and anti-phase boundary (APB) are generated in the grown 3C-SiC layer. Remarkably, this hindered the realization of SiC semiconductor devices.
[0005]
As a method of reducing defects in the 3C-SiC film by the vapor phase epitaxial growth method, for example, a step of providing a growth region on a substrate to be grown and a thickness of an SiC single crystal in the growth region in the growth plane orientation of the substrate A technique for reducing the surface defects after the unique thickness has been proposed (Japanese Patent Publication No. 6-41400). However, since the two types of antiphase regions included in 3C-SiC have the property of expanding in directions orthogonal to each other with respect to the increase in film thickness of 3C-SiC, the antiphase region boundary interface is It cannot be reduced effectively. Furthermore, since the orientation of the superstructure formed on the grown 3C-SiC surface cannot be controlled arbitrarily, for example, when discrete growth regions are combined with each other during growth, a new reaction is applied to the joint. A phase region boundary surface is formed, and desired electrical characteristics cannot be realized.
[0006]
As a method for effectively reducing the anti-phase region boundary surface, there is a growth method on a Si (001) plane substrate in which the surface normal axis is slightly tilted from [100] to [110] (introduction of an off angle). Proposed (see Abride Physics Letters, 50, 1987, p. 1888). In this method, since the atomic steps are introduced at equal intervals in one direction by giving a slight tilt to the substrate, a plane defect in a direction parallel to the introduced steps propagates, while the introduced steps are This has the effect of suppressing the propagation of surface defects in the direction perpendicular to the direction (the direction across the step). And, as the film thickness of SiC increases, the antiphase region that expands in the direction parallel to the introduced step out of the two types of antiphase regions included in the film expands in the orthogonal direction Therefore, the antiphase region boundary surface can be effectively reduced. However, this method has a problem that an increase in the step density of the SiC / Si interface causes an unintentional generation of the antiphase region boundary surface, and the antiphase region boundary surface cannot be completely eliminated. .
[0007]
On the other hand, there has been proposed a method in which a plurality of undulations extending in parallel in one direction are provided on all or part of the surface of the substrate to be grown and SiC is grown on the surface of the substrate (Japanese Patent Laid-Open No. 2000-178740). ). In this method, since the surface of the SiC crystal to be grown is introduced at a density in which the steps oriented in a mirror-symmetrical orientation are statistically balanced, the reaction in the SiC layer introduced unintentionally by the step on the surface of the substrate to be grown is introduced. The phase region boundary surfaces are effectively associated with each other, and an SiC film in which the anti-phase region boundary surfaces are completely eliminated is obtained. Furthermore, in this method, since the individual growth regions are all in the same phase region that is expanded in the same direction by introducing the off-angle, even when the discrete growth regions are coupled with each other with growth, the antiphase region is connected to the coupling portion. There is an advantage that no boundary surface occurs.
[0008]
However, desired characteristics cannot be obtained even in a semiconductor device manufactured using a 3C-SiC substrate manufactured using this method. As a result of detailed studies on the reason, the present inventors have concluded that stacking faults on the (111) plane, which are contained in large numbers in 3C-SiC, hinder the characteristics of the semiconductor device. For example, there is a difference in lattice constant of about 20% between a Si single crystal widely used as a substrate to be grown and a 3C-SiC single crystal. Therefore, a 3C-SiC single crystal is grown on a Si substrate by a conventional method. The 3C-SiC thus made has many stacking faults on the (111) plane.
[0009]
[Problems to be solved by the invention]
Thus, conventionally, in order to form a SiC single crystal substrate as an element formation substrate of a semiconductor device, a method of growing an SiC layer on a Si (001) substrate by introducing an off angle, or extending in one direction in parallel. Although a method of growing a SiC layer on a substrate having undulations has been proposed, it is difficult to obtain a 3C-SiC single crystal with reduced stacking faults with good reproducibility by using any method. . Therefore, there is a need for a production method that can stably supply such a 3C—SiC single crystal having excellent crystallinity on an industrial scale.
[0010]
The present invention has been made in view of the above circumstances, and the object thereof is a method for manufacturing a silicon carbide single crystal substrate capable of manufacturing a 3C-SiC single crystal with reduced stacking faults with good reproducibility, Another object of the present invention is to provide a method for manufacturing a semiconductor device using the substrate.
[0011]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0012]
That is, according to the present invention, in a method for manufacturing a silicon carbide single crystal substrate, a bulk crystal substrate (an ingot grown by a melt growth method such as a Si substrate) is cut out with a diamond blade or the like and polished and formed to a predetermined thickness. A plurality of undulations on at least a part of the surface of the wafer), a step of epitaxially growing a cubic SiC layer on the surface of the crystal substrate on which the undulations are formed, and a first SiC Removing the crystal substrate from the layer, and epitaxially growing a cubic second SiC layer on the surface of the first SiC layer exposed by removing the crystal substrate to planarize the surface. It is characterized by that.
[0013]
According to the present invention, in the method for manufacturing a silicon carbide single crystal substrate, a step of epitaxially growing a cubic first SiC layer on the surface of the bulk crystal substrate, and a plurality of at least part of the surface of the first SiC layer are provided. Forming a undulation of the first, a step of removing the crystal substrate from the first SiC layer, and then growing a second SiC layer of cubic system on the surface having the undulation of the first SiC layer. And flattening the surface.
[0014]
Here, preferred embodiments of the present invention include the following.
(1) The bulk crystal substrate is Si, Ge, or SiGe.
[0015]
(2) The plurality of undulations formed on the surface of the crystal substrate is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. thing.
(3) The plurality of undulations formed on the surface of the first SiC layer is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. Be a pattern.
[0016]
(4) The plurality of undulations formed on the surface of the crystal substrate is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. It must be a grid pattern that is orthogonal to each other.
(5) The plurality of undulations formed on the surface of the first SiC layer is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. It is a lattice pattern in which the patterns are orthogonal to each other.
[0017]
(6) The plane orientation of the crystal substrate is (001), and the line and space pattern is tilted several degrees from the <110> direction.
(7) When removing the single crystal substrate, the substrate is mechanically polished halfway, and the remainder is etched using a solution.
[0018]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the step of forming a cubic n ⁺ -type SiC single crystal substrate composed of the first and second SiC layers by any one of the methods described above, and the SiC single crystal. And a step of epitaxially growing a cubic n ⁻ -type SiC layer on the substrate.
[0019]
(Function)
According to the present invention, after epitaxial growth of a cubic first SiC layer on the surface of a bulk crystal substrate on which a plurality of undulations are formed, the crystal substrate is removed from the first SiC layer to A SiC layer having a plurality of undulations can be formed.
[0020]
Here, since the surface layer of the first SiC layer is in contact with the bulk crystal substrate, it contains many crystal defects and strains. However, for example, by removing the oxide film after performing thermal oxidation or removing the outermost surface by reactive ion etching, it is sufficient as a surface of a homoepitaxial substrate for subsequent growth of a high-quality SiC single crystal. Therefore, it can serve as a growth substrate having a desired crystallinity and having a plurality of desired undulations. Since this surface is provided with a plurality of undulations, even if twins, antiphase region boundaries, stacking faults, etc. exist on each undulation slope of the SiC single crystal surface, the off-angle described above Since the introduction effect can be obtained, it is possible to effectively prevent these defects from propagating in the growth direction.
[0021]
Moreover, in the present invention, a plurality of undulations extending in one direction as disclosed in JP 2000-178740 A can be formed on the surface of the first SiC layer. Steps oriented in a mirror-symmetrical orientation are introduced into the surface at a statistically balanced density. For this reason, the antiphase region boundary surfaces in the SiC growth layer introduced unintentionally by the step of the surface of the first SiC layer effectively associate with each other, and the antiphase region boundary surface is almost completely eliminated. SiC layer is obtained. Furthermore, because of the effect of introducing the off-angle, all the growth regions become the same phase region that expands in the same direction, so that even when the discrete growth regions are joined together with growth, there is no step at the joint. There is an advantage that an anti-phase region boundary surface does not occur.
[0022]
Here, when mechanical processing means is used to form a plurality of undulations on the surface of the first SiC layer, processing damage is unexpectedly formed in the depth direction, and it is difficult to remove the crushed layer. There is a case. In this case, undulations are formed in advance on the surface of the bulk crystal substrate, a first SiC layer is grown thereon, and the undulations are formed on the surface exposed by removing the bulk crystal substrate from the grown SiC layer. Is most desirable from the viewpoint of ease of process and good reproducibility. When the crushed layer by the mechanical processing means can be easily removed, the undulations may be formed directly on the first SiC layer.
[0023]
Further, according to the present invention, since the epitaxial growth of the second SiC layer on the first SiC layer having a plurality of undulations is not heteroepitaxy, new defects such as stacking faults due to stress caused by the difference in the lattice constant of the substrate, etc. Therefore, it is possible to manufacture a high-quality, low-defect SiC single crystal substrate that is excellent in reproducibility and does not cause any defects. In addition, since the bulk crystal substrate is removed from the first SiC layer when the second SiC layer is grown, the first SiC layer is not strained due to a difference in lattice mismatch with the bulk crystal substrate. The growth can be performed in a state, and this can also prevent the occurrence of stacking faults due to lattice mismatch.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0025]
(First embodiment)
1 to 3 are diagrams for explaining a method of manufacturing a SiC single crystal substrate according to the first embodiment of the present invention, and FIG. 1 is a cross-sectional view showing a process of forming undulations on the surface of a bulk crystal substrate. FIG. 2 is a plan view showing a resist pattern formed on a bulk crystal substrate, and FIG. 3 is a cross-sectional view showing a step of growing a SiC layer.
[0026]
In this embodiment, a Si (001) substrate is used as the bulk crystal substrate. As shown in FIG. 1 (a), after the surface of the Si substrate 11 is thermally oxidized, the substrate surface is composed of a line and space having a width of 1.5 μm, a length of 90 mm, and a thickness of 1 μm on the substrate surface. A resist pattern 12 was formed. However, the line direction in the resist pattern 12 was parallel to a direction inclined by 2 ° from the <110> direction, as shown in FIG.
[0027]
By heating this substrate on a hot plate at 180 ° C. for 10 minutes, the resist pattern 12 spreads in the direction perpendicular to the line, and as shown in FIG. A resist pattern shape having a wavefront cross section connected by a smooth curve was obtained. Next, as shown in FIG. 1C, the undulating shape and the planar line and space shape of the cross section of the resist pattern 12 ′ were transferred to the Si substrate 11 by dry etching. Specifically, the top and bottom are continuously formed in one direction on the surface of the Si substrate 11 by etching these with the RIE method under conditions where the etching rates of the resist and Si are substantially the same, and the top And the line-and-space-like undulations 13 in which the bottoms are periodically arranged at regular intervals were formed.
[0028]
Here, the resist pattern 12 formed on the Si substrate 11 is not necessarily limited to the line and space pattern as shown in FIG. 2A, but as shown in FIG. An orthogonal grid pattern may be used.
[0029]
Next, after removing the resist remaining on the surface of the Si substrate 11 in a mixed solution of hydrogen peroxide aqueous solution and sulfuric acid, the Si substrate 11 with the undulations 13 formed on the surface is formed as shown in FIG. First, the first 3C—SiC layer 21 was grown. Here, the conductivity type of SiC layer 21 may be either p-type or n-type, but in general, high-concentration n-type (n ⁺ -type) is desirable.
[0030]
The growth of SiC can be divided into a carbonization process on the surface of the Si substrate and a SiC growth process by alternately supplying source gases. First, in the carbonization step, the processed Si substrate 11 was heated from room temperature to 1050 ° C. in about 2 hours in a reduced-pressure acetylene atmosphere with a furnace pressure of 2.7 Pa. At this time, the supply amount of acetylene was 10 sccm. After this carbonization step, while maintaining the temperature at 1050 ° C., dichlorosilane and acetylene were exposed to the substrate surface alternately for 20 seconds each at 20 sccm and each gas supply interval for 5 seconds to grow the 3C—SiC layer 21. Went. At this time, the pressure in the furnace was a minimum of 2.7 Pa and a maximum of 27 Pa.
[0031]
The film thickness of the first 3C—SiC layer 21 was increased by increasing the number of supply cycles of the source gas, and the film was grown to 150 μm. Note that the thickness of the 3C—SiC layer 21 can be changed as appropriate, but is preferably 50 μm or more in order to obtain a good crystal with few defects.
[0032]
Next, the above sample was cooled to room temperature and then taken out, and immersed in a mixed acid of HF and HNO ₃ (HF: HNO ₃ = 7: 1) to obtain the first 3C—SiC as shown in FIG. The Si substrate 11 was removed from the layer 21. Here, when the Si substrate 11 is thick, it may be etched using the above mixed acid after it has been cut by mechanical polishing halfway. Thereafter, reactive ion etching was performed using CF ₄ (40 sccm) and O ₂ (10 sccm) as etching gases in order to remove the defect density layer having the highest outermost surface of the 3C—SiC layer 21 with the undulating shape exposed. Instead of performing this reactive ion etching, the oxide film may be removed after the exposed surface of the 3C—SiC layer 21 is thermally oxidized.
[0033]
Next, the first 3C—SiC layer 21 subjected to such a processing treatment was accommodated in the reaction vessel with the processing surface facing upward, and the second 3C—SiC layer 22 was grown. Since the SiC growth at this stage is homoepitaxy, the carbonization step may be omitted. The 3C—SiC layer 21 was heated from room temperature to 1050 ° C. in about 5 minutes in a reduced pressure acetylene atmosphere with a furnace pressure of 2.7 Pa. At this time, the supply amount of acetylene was 10 sccm. After this carbonization step, while maintaining the temperature at 1050 ° C., dichlorosilane and acetylene were exposed to the substrate surface alternately at 20 sccm for 10 seconds each with an interval of each gas supply of 5 seconds to grow 3C-SiC. went. At this time, the pressure in the furnace was a minimum of 2.7 Pa and a maximum of 27 Pa.
[0034]
Then, the film thickness of the second 3C—SiC layer 22 is increased by increasing the number of supply cycles of the source gas, and when the film is grown to 100 μm, the source supply flow rate is reduced to 5 sccm, and the growth rate is substantially reduced to ¼. In the state, the last 50 μm was grown.
[0035]
Thus, according to this embodiment, a 3C—SiC substrate having a total thickness of 300 μm could be obtained. As a result of measuring the antiphase region boundary surface density by observing the substrate surface grown in this manner by AFM, the presence of the antiphase region boundary surface was not recognized in the observation region. In addition, in order to investigate the occurrence of stacking faults, the grown substrate was cleaved at the (110) plane, and the cross section was observed with a transmission electron microscope. Although it was observed, it did not propagate along the growth direction, and stacking faults were not observed at all at a distance of 5 μm or more from the undulation.
[0036]
As described above, according to the present embodiment, the line-and-space undulations 13 are provided on the surface of the Si substrate 11, and the first 3C-SiC layer 21 is epitaxially grown thereon, whereby the first 3C- The undulations can be transferred to the surface of the SiC layer 21. Then, by growing the second 3C-SiC layer 22 on the surface of the first 3C-SiC layer 21 having such undulations, twins, anti-phase region boundaries, stacking faults, and the like are grown in the growth direction. Propagation can be effectively prevented.
[0037]
In addition, since the steps oriented in the mirror symmetry direction are introduced into the surface of the first 3C-SiC layer 21 at a statistically balanced density, the second 3C-SiC layer 22 has an antiphase region boundary surface. This is almost completely eliminated, and the anti-phase region boundary surface does not occur due to the effect of introducing the off angle. In addition, since the second 3C-SiC layer 22 is grown in a state where the Si substrate 11 is removed, the growth can be performed in a state in which no strain is left due to the difference in lattice mismatch between SiC and Si. Also, it is possible to prevent the occurrence of stacking faults due to lattice mismatch.
[0038]
(Second Embodiment)
FIG. 4 is a cross-sectional view showing a manufacturing process of the SiC single crystal substrate according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 3 and an identical part, and the detailed description is abbreviate | omitted.
[0039]
In the present embodiment, as shown in FIG. 4A, the first 3C—SiC layer 21 is epitaxially grown on the Si substrate 11 having a flat surface. The SiC growth conditions at this time were the same as those in the first embodiment. That is, after heating the Si substrate 11 from room temperature to 1050 ° C. for about 2 hours in a reduced-pressure acetylene atmosphere with a furnace pressure of 2.7 Pa, dichlorosilane and acetylene were kept at 1050 ° C. for 10 seconds each at 20 sccm. Then, the 3C-SiC layer 21 was grown by alternately exposing the surface of the substrate with each gas supply interval being 5 seconds. The film thickness of the SiC layer 21 was 150 μm as in the first embodiment.
[0040]
Next, as shown in FIG. 4B, line and space undulations were formed on the surface of the SiC layer 21. The method of forming the undulations may be the same as that formed on the Si substrate 11 in the first embodiment. That is, after forming a resist pattern composed of line and space on the surface of the SiC layer 21 using a photolithography technique, the resist pattern is deformed by heat treatment to obtain a resist pattern shape having a wavefront cross section. Then, the undulating shape of the cross section of the resist pattern and the planar line and space shape are transferred to the SiC layer 21 by dry etching. Thereafter, the surface is cleaned by solution etching to remove the fractured layer by etching.
[0041]
Next, as illustrated in FIG. 4C, the Si substrate 11 was removed from the 3C—SiC layer 21. For removal of the Si substrate 11, a mixed acid of HF and HNO ₃ was used as in the first embodiment.
[0042]
Next, as illustrated in FIG. 4D, the second 3C—SiC layer 22 was epitaxially grown on the first 3C—SiC layer 21. The growth conditions at this time are the same as in the first embodiment. That is, after the 3C-SiC layer 21 was heated from room temperature to 1050 ° C. in about 5 minutes in a reduced pressure acetylene atmosphere with a furnace pressure of 2.7 Pa, dichlorosilane and acetylene were each 10 sccm at 20 sccm while maintaining the temperature at 1050 ° C. The second 3C—SiC layer 22 was grown by exposing each of the gas supply intervals to the substrate surface alternately at intervals of 5 seconds. The film thickness of the SiC layer 22 was 150 μm as in the first embodiment.
[0043]
According to the present embodiment, the second 3C-SiC layer 22 is epitaxially grown in a state where the surface of the first 3C-SiC layer 21 has line-and-space undulations. Similar effects can be obtained.
[0044]
(Third embodiment)
FIG. 5 is a cross-sectional view showing a Schottky diode manufacturing process according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 3 and an identical part, and the detailed description is abbreviate | omitted.
[0045]
First, in the same manner as in the first embodiment, the first and second 3C—SiC layers 21 and 22 are formed by the steps shown in FIGS. 1 (a) to 1 (c) and FIGS. 3 (a) to 3 (c). A 3C-SiC substrate was prepared. At this time, the SiC substrate was a high-concentration n-type (n ⁺ -type).
[0046]
Next, as shown in FIG. 5A, an n ⁻ -type 3C—SiC layer 25 was epitaxially grown on the 3C—SiC substrate 20. The growth conditions at this time may be the same as in the case of the growth of the second 3C—SiC layer 22 described in the first embodiment. Subsequently, as shown in FIG. 5B, an ion implantation layer 26 was formed on the surface layer of the SiC layer 25 by Ar ion implantation, and an electrode 27 made of TiAl was formed on the layer 26. Further, an electrode made of Pt or Au was provided on the back side of the SiC substrate 20.
[0047]
In the Schottky diode thus formed, since the 3C-SiC substrate 20 is a high-quality crystal having no defects, the 3C-SiC layer 25 formed on the 3C-SiC substrate 20 is also a high-quality crystal, and the device characteristics can be improved. it can.
[0048]
The present invention is not limited to the above-described embodiments. The growth temperature of 3C SiC is not limited to the above embodiment, and can be implemented in the range of 800 to 1200 ° C. In particular, a temperature in the range of 900 to 1100 ° C. is preferable for obtaining good crystals. In the embodiment, the Si substrate is used as the bulk substrate crystal. However, the present invention is not limited to this, and a single crystal substrate of Ge or SiGe can also be used. Further, in the embodiment, the undulation is provided on the entire surface of the bulk substrate crystal or the first SiC layer. However, when the region where the element is formed is not the entire region, the undulation may be provided on a part of the surface. . Furthermore, the shape of the undulation, the method for forming the undulation, and the like can be changed as appropriate according to the specifications.
[0049]
In the manufacture of a semiconductor device using the SiC single crystal substrate of the present invention, the SiC layer formed on the substrate is not necessarily limited to the n ⁻ type layer, and may be a p type layer, depending on the element to be formed. It can be changed as appropriate. Furthermore, it is needless to say that the present invention is applicable not only to Schottky diodes but also to manufacturing various elements. In addition, various modifications can be made without departing from the scope of the present invention.
[0050]
【The invention's effect】
As described above in detail, according to the present invention, when a SiC crystal substrate used as an element formation substrate is manufactured, a plurality of undulations formed on the surface of the bulk crystal substrate are transferred to the first 3C-SiC layer, or the first A plurality of undulations are directly formed in the 3C-SiC layer, and the second 3C-SiC layer is epitaxially grown on the surface of the first 3C-SiC layer having the undulations. A SiC single crystal substrate having a high crystal integrity with significantly reduced stacking faults can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a process for forming undulations on a surface of a bulk crystal substrate, for explaining a method for manufacturing a SiC single crystal substrate according to a first embodiment.
FIG. 2 is a plan view showing a resist pattern formed on the bulk crystal substrate for explaining the method for manufacturing the SiC single crystal substrate according to the first embodiment.
FIG. 3 is a cross-sectional view illustrating a SiC layer growth step for explaining the method of manufacturing the SiC single crystal substrate according to the first embodiment.
FIG. 4 is a cross-sectional view showing a manufacturing process of the SiC single crystal substrate according to the second embodiment.
FIG. 5 is a cross-sectional view showing a manufacturing process of a Schottky diode according to a third embodiment.
[Explanation of symbols]
11 ... Si substrate (bulk crystal substrate)
DESCRIPTION OF SYMBOLS 12 ... Resist pattern 13 ... Uneven 20 ... 3C-SiC single crystal substrate 21 ... 1st 3C-SiC layer 22 ... 2nd 3C-SiC layer 25 ... n < ^- > type SiC layer 26 ... Ion implantation layer 27, 28 ... Electrode

Claims (5)

Forming a plurality of undulations on at least a portion of the surface of the bulk crystal substrate; epitaxially growing a cubic first SiC layer on the surface of the crystal substrate on which the undulations are formed; and a first SiC Removing the crystal substrate from the layer, and epitaxially growing a cubic second SiC layer on the surface of the first SiC layer exposed by removing the crystal substrate to planarize the surface. A method for producing a silicon carbide single crystal substrate, comprising: A step of epitaxially growing a cubic first SiC layer on the surface of the bulk crystal substrate, a step of forming a plurality of undulations on at least a part of the surface of the first SiC layer; Carbonization comprising: removing the crystal substrate; and then growing a cubic second SiC layer on the surface having the undulations of the first SiC layer to planarize the surface. A method for producing a silicon single crystal substrate. The plurality of undulations formed on the surface of the crystal substrate or the first SiC layer is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. The method for manufacturing a silicon carbide single crystal substrate according to claim 1 or 2, wherein the pattern is the following pattern. The plurality of undulations formed on the surface of the crystal substrate or the first SiC layer is a line-and-space pattern in which the top and bottom are continuously formed in one direction, and the top and bottom are periodically arranged at regular intervals. The method of manufacturing a silicon carbide single crystal substrate according to claim 1, wherein the patterns are lattice-like patterns orthogonal to each other. A step of forming a cubic n ⁺ -type SiC single crystal substrate composed of the first and second SiC layers by the method according to any one of claims 1 to 4, and a cubic crystal on the SiC single crystal substrate. And a step of epitaxially growing a n ^- type SiC layer of the system.

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