JP3754685B2 - Display device - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique for reducing power consumption in a standby state.

  Liquid crystal display devices are widely used in portable information devices and the like that operate with battery-supplied power because they are thinner and lighter than CRTs and consume less power.

  However, it is desired to extend the operation time of such a portable information device using a battery. On the other hand, further downsizing of portable information devices is desired. For this purpose, the battery needs to be downsized.

  In order to realize such a proposition, it is desirable to reduce the power consumption of a liquid crystal display device used in information equipment.

  Here, as a conventional technique for reducing the power consumption of a liquid crystal display device, for example, when a keyboard or the like is not operated for a long time on a personal computer, that is, when the device is in a standby state, A technique for shutting off the power supply of the is known.

  In addition, although not related to liquid crystal display devices, as described in NIKKEI ELECTRONICS NO590 (issued on September 13, 1993), when a display device using a CRT is in a standby state, There is known a technique for reducing the power consumption of an apparatus by interrupting the supply of power to a high-voltage circuit.

  According to the respective technologies for reducing the standby power consumption, display on the display device is not performed in the standby state, so that the state of the information device at that time cannot be visually recognized.

  Accordingly, an object of the present invention is to provide a liquid crystal display device that can perform display with low power consumption when in a standby state.

  In order to achieve the above object, according to the present invention, during a period in which standby is instructed, the signal driving unit includes, for each of a plurality of scanning periods, a plurality of liquid crystal cells in a column to which the liquid crystal cell belongs. A method for reducing the power consumption of a liquid crystal display device, wherein a signal voltage corresponding to the content to be displayed in common is applied to and held in a plurality of liquid crystal cells of a plurality of lines to which the scanning voltage is applied during the scanning period provide.

  In order to achieve the above object, according to the present invention, the signal driver has a signal voltage having an amplitude smaller than that in the non-standby state during a period in which standby is instructed, and is determined according to a gradation to be displayed. A method for reducing power consumption of a liquid crystal display device, characterized by applying and holding an oscillation voltage having an amplitude.

  According to the power consumption reduction method of the present invention, the current flowing into and out of the liquid crystal matrix panel can be reduced by lengthening the change period of the signal voltage applied to the liquid crystal matrix panel or reducing the voltage level of the signal voltage. As a result, power consumption is reduced. In addition, even if the change period of the signal voltage is increased or the voltage level of the signal voltage is decreased, a display that can be visually recognized by the user is ensured. You can see the state of the equipment. In this case, the display quality is deteriorated in the standby state period, but the standby state is a period in which the user does not use, so that no problem in use occurs.

  As described above, according to the present invention, the present invention can provide a liquid crystal display device capable of performing display with low power consumption when in a standby state.

  Examples of information equipment according to the present invention will be described below.

  First, the configuration and operation of an information device and a liquid crystal display device common to each embodiment presented below will be described.

  FIG. 1 shows the appearance of the information device according to the present embodiment.

  In the figure, 1000 is an information device, 2 is a display unit of a liquid crystal display device, 3000 is a floppy disk insertion port of a floppy disk driver, 4000 is an input pen, 5000 is a key switch group, 6000 is a power save switch, and 7000. Is a power switch. As shown in the figure, the liquid crystal display device is incorporated in the information device 1000.

  FIG. 2 shows the internal configuration of the information device 1.

  In the figure, 1001 is a CPU, 1002 is a ROM storing a program executed by the CPU 1, 1003 is a RAM used for executing the program, 1004 is a battery, 10 is a liquid crystal display device, and 1005 is a liquid crystal for controlling the display of the liquid crystal display device. A display device, 1006 is a V-RAM storing data defining display contents to be displayed on the display device, 1007 is an interface circuit between the power save switch 6000 and the key switch group 5000, etc., and 1008 is a floppy. An interface circuit for the disk drive, 1009 is an interface circuit for the control signal 2003 for the display control apparatus 10, and 1010 is an interface circuit for the input pen 4000.

  The liquid crystal display device 10 includes a display unit 2, a light source 4, and a drive control circuit 2005.

  In such a configuration, when the input pen 4000 is placed on the display unit 2, the input pen 4000 detects the coordinates on the display unit 2, for example, by detecting the voltage applied to the display unit 2. .

  Further, the CPU 1001 executes a program in accordance with the coordinates detected by the input pen 4000 and the key input of the key switch group 5000, and displays the contents to be displayed on the display unit 2 of the liquid crystal display device 10 according to the execution result. Then, the image data defining the display contents is written into the V-RAM 1006. The display control device 1005 sends the image data 2002 stored in the V-RAM 1006 to the liquid crystal display device 10 together with a synchronization signal group 2001 necessary for display on the liquid crystal display device 10.

  Further, the CPU 1001 detects that the power save switch 6 is turned on via the interface circuit 1007, or detects the coordinates of the input pen 4 or the key of the key switch group 5000 for a certain period or more. When it is detected that there is no input, a power save control signal 2003 for instructing the transition to the power save mode is sent to the liquid crystal display device 10 via the interface circuit 1009. .

  When the power switch is turned on, the battery 1004 supplies power of a predetermined voltage to each part of the information device 1000 including the liquid crystal display device 10.

  Next, FIG. 3 shows an internal configuration of the liquid crystal display device 10.

  As shown in the figure, the signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, the light source 4, the interface circuit 7, and the display unit 2 are configured. The signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, and the interface circuit 7 correspond to the drive control circuit 2005 shown in FIG.

  In this embodiment, a liquid crystal matrix panel is assumed as the display unit 2. As shown in FIG. 4, the liquid crystal matrix panel 2 includes one pixel including a TFT (thin film transistor) 13 and a liquid crystal 14. Further, the scanning lines 12a to 12d are connected to the gate electrode of the TFT 13, and the signal lines 11a to 11c are connected to the drain electrode.

  The interface circuit 7 receives image data 2002 to be displayed on the display unit 2 from the display control device 1005. Further, as a synchronization signal included in the synchronization signal group 2001, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal synchronized with the image data 2002 are input, and a power save control signal 2003 is passed through the interface circuit 1009. Input from the CPU 1001. Here, the image data 2002 is input in the order according to the raster scan method. The vertical synchronization signal is a pulse signal output every frame period of an image to be displayed, and the horizontal synchronization signal is a pulse signal output every line scanning period.

  The interface circuit 7 passes these signals to the display control circuit 5.

  The display control circuit 5 receives from the image data 2002, the synchronization signal 2001, and the power save control signal 2003, image data DATA, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, A save control signal PS is generated, the generated vertical synchronizing signal VSYNC, horizontal synchronizing signal HSYNC, clock signal DCLK, and image data DATA are sent to the signal driving circuit 1, and a horizontal synchronizing signal HSYNC is sent to the scanning driving circuit 3. A vertical synchronizing signal VSYNC is sent, and a synchronizing signal (one or both of VSYNC and HSYNC) and a clock signal DCLK necessary for realizing a polarity inversion driving method to be described later are sent to the voltage control circuit 6, and the voltage control circuit 6 and signal driving are sent. A power control signal PS is sent to the circuit 1, the scanning drive circuit 3, and the light source 4.

  However, depending on the embodiment described below, it may not be necessary to send some signals.

  FIG. 5 shows the timing of the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the clock signal DCLK, and the image data DATA in the normal mode (in the non-power-saving operation mode) (FIG. 5a). The correspondence of the display screen (FIG. 5b) defined thereby will be described. The timing shown in FIG. 5a matches the timing of the vertical synchronizing signal, horizontal synchronizing signal, clock signal, and image data input to the interface circuit 7.

  The voltage control circuit 6 uses the power supplied from the battery 1004 to generate a scan drive voltage and send it to the scan drive circuit 3. Further, a signal driving voltage is generated and sent to the signal driving circuit 1.

  As shown in FIG. 6, the scanning drive circuit 3 sequentially responds to the scanning drive voltage sent from the voltage control circuit 6 to the different scanning lines 12 a to 12 d in the order of the arrangement in synchronization with the horizontal synchronization signal HSYNC. The scanning voltages Vg1 to Vgn are applied. Each time the vertical synchronization signal VSYNC is input, the above operation is repeated from the first scanning line 12a. That is, the scanning voltage sequentially becomes the value Vgh for each line, and the TFT is turned on for each line.

  On the other hand, the signal driving circuit 1 includes two groups of latch groups that can store image data for one line. The signal lines 11a to 11c are provided with the same number of output circuits as the number of image data for one line respectively connected. The first latch group sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and the latched image data DATA for one line in the second latch group in synchronization with the horizontal synchronization signal HSYNC. The data for one line is transferred in parallel, and the transferred image data for one line is held until the image data for the next line is received, and is output in parallel to different output circuits. During this time, the first latch group sequentially captures the image data of the next line in the same manner as the previous line. As a result, as shown in FIG. 6, signal voltages Vd1 to Vdm are applied.

  Each output circuit applies the signal voltages Vd1 to Vdm to the connected signal lines according to the value of the received image data and the signal driving voltage sent from the voltage control circuit 6.

  The configuration and operation of the information equipment and the liquid crystal display device common to the embodiments presented in this embodiment have been described above. Hereinafter, in the liquid crystal display device 10 having such a configuration, each embodiment for reducing power consumption while ensuring display will be described.

  First, the first embodiment will be described.

  In the first embodiment, when the display control device 5 receives the power save signal from the interface circuit 7, the cycle of the horizontal synchronizing signal HSYNC to be output is doubled in the normal mode. The power save operation mode is instructed to the scanning drive circuit 3 and the signal drive circuit 1 by the power save signal PS. Note that such a change in the period of the horizontal synchronization signal HSYNC causes the display control circuit 8 to change the frequency of the horizontal synchronization signal HSYNC to be output to the display control circuit 8 when the power save signal PS indicates ON, as will be described later. This can be realized by providing a frequency dividing circuit that divides the frequency of the horizontal synchronizing signal input from the circuit 7 by half. Alternatively, when the power save signal PS indicates ON, a signal having a frequency ½ of this is output as the horizontal synchronization signal HSYNC in phase with the horizontal synchronization signal input from the interface circuit 7. An oscillator may be provided.

  As shown in FIG. 7, the scanning drive circuit 3 sequentially scans two scanning signals at two scanning signals, such as Vg1 and Vg2, and Vg3 and Vg4, for each period of the horizontal synchronization signal HSYNC output from the display control circuit 3. Apply the value Vgh. For example, the scanning voltage is applied for each of the two scanning signals. For example, the scanning driving circuit 3 counts the number of scanning signals connected to different scanning signal lines and the number of scanning signals, and the HSYNC is reset by the VSYNC. And a decoder that decodes the count value of the counter according to the value of the power save signal PS. The output circuits are sequentially activated according to the decode value of the decoder. It can be realized by making it. Here, the output circuit is a circuit that outputs the scanning voltage supplied from the voltage control circuit 6 to the corresponding scanning signal line when it is validated.

  On the other hand, in the signal driving circuit 1, when the first latch group becomes full by taking in the image data of the odd-numbered lines, the operation of discarding the input image data of the even-numbered lines is repeated. The odd-numbered line image data captured by the first latch group is captured by the second latch group by the horizontal synchronization signal HSYNC input at the end of the input of the next even-numbered line image data. Up to the horizontal synchronization signal HSYNC input is held and output to the output circuit. As a result, the voltage applied to each signal line is updated at a cycle twice that of the normal mode.

  By doing so, the period in which the TFT of the liquid crystal matrix 2 is turned on is doubled. In accordance with this, the cycle in which the levels of the signal voltages Vd1 to Vdm change is also doubled. Accordingly, power consumption of the liquid crystal matrix 2, the signal driving circuit, the voltage control circuit 6 and the like can be reduced.

  On the other hand, the resolution of the image displayed on the liquid crystal matrix 2 is ½ of the normal mode in the vertical direction, but in the power save mode, the period during which the user is not working Therefore, there is no practical problem.

  The display control circuit 8 outputs the input signal from the interface circuit 7 as it is for the vertical synchronization signal VSYNC, the operation clock DCLK, and the image data DATA.

  As shown in FIG. 8, the scanning voltages Vg1, Vg2. . Is applied in the same manner as in the normal mode, and the display control circuit 5 doubles only the period of the horizontal synchronization signal HSYNC given to the signal drive circuit 1, thereby changing the level of only the signal voltage every two lines. You may do it. Even in this case, the cycle in which the level of the signal voltage changes can be doubled, and the same effect as in the first embodiment can be achieved.

  Further, the cycle of the clock signal DCLK is doubled, and in the signal driving circuit 1, the image data is taken into the first latch group every other pixel data, and the second latch from the n-th latch in the first latch group. Data may be transferred in parallel to the 2n-1st and 2nth latches of the latch group in synchronization with the horizontal synchronization signal HSYNC. Such a change in the cycle of the clock signal DCLK is performed by inputting the frequency of the clock signal DCLK to be output from the interface circuit 7 to the display control circuit 8 when the power save signal PS is turned on. This can be realized by providing a frequency dividing circuit that divides the frequency of the operation clock signal to ½. Of course, an oscillator that generates a clock having a frequency half that of the operation clock signal input from the interface circuit 7 in phase with the operation clock signal input from the interface circuit 7 may be provided. Good.

  In this way, the horizontal resolution of the display is also halved. However, as described above, the power save mode is a period in which the user is not working, which is a practical problem. Never become. Further, since the operating frequency of the first latch group of the signal driving circuit 1 is ½ that in the normal mode, power consumption can be reduced.

  In this embodiment, the drive / operation frequency of the scanning drive circuit 3 and the signal drive circuit 1 is changed to 1/2 in the power save mode. A ratio may be used.

  The second embodiment will be described below.

  In the first embodiment, the driving / operating frequency of the scanning driving circuit 3 and the signal driving circuit 1 is lowered, and the image displayed by the image data input to the interface circuit 7 is reduced in resolution and displayed. Reduced power. In the present embodiment, in the power save mode, a predetermined image is generated by the built-in pattern generator without using the image data input to the interface circuit 7, and this is displayed.

  FIG. 9 shows the configuration of the display control circuit 5 according to the second embodiment.

  As shown in the figure, in the second embodiment, the display control circuit 5 includes a selection circuit group 19 including selection circuits 19a to 19d, an oscillation circuit 22, a pattern generator 20, and a control circuit 21.

  The control circuit 21 uses the basic clock output from the oscillation circuit 22 to generate three signals VSYNC (with a frequency ratio equal to the frequency ratio of the direct synchronization signal, horizontal synchronization signal, and operation clock input from the interface circuit. IN), HSYNC (IN), and DCLK (IN). The pattern generator 20 is actually a memory storing image data, and outputs image data indicating a predetermined image pattern as shown in FIG. 10, for example, in synchronization with DCLK (IN). To do.

  In the normal mode, the selection circuits 19a to 19d output the vertical synchronization signal, horizontal synchronization signal, operation clock, and image data input from the interface circuit 7 as they are as VSYNC, HSYNC, DCLK, and DATA. In the save mode, the timing signals VSYNC (IN), HSYNC (IN), and DCLK (IN) input from the control circuit 21 are output as VSYNC, HSYNC, and DCLK, and the pattern generator 20 DATA (IN) input from is output as DATA.

  Here, the frequency of VSYNC (IN), HSYNC (IN), and DCLK (IN) output from the control circuit 21 is determined from the frequency of the direct synchronization signal, horizontal synchronization signal, and operation clock input from the interface circuit. A small frequency can be used to such an extent that the display visibility of the liquid crystal matrix 2 is not significantly impaired. Therefore, the driving / operating frequency of each part can be reduced as compared with the normal mode, so that power consumption can be reduced.

  Of the VSYNC (IN), HSYNC (IN), and DCLK (IN) output from the control circuit 21, the horizontal synchronization signal input from the interface circuit 7 for HSYNC (IN) and DCLK (IN), and the operation The frequency ratio with respect to the clock is set to, for example, 1/2 of the frequency ratio with respect to the vertical synchronizing signal inputted from the interface circuit 7 of VSYNC (IN), and the scan driving circuit 3 is the same as the first embodiment (see FIG. 7). If two scanning signal lines are driven at a time, the resolution in the vertical direction is halved compared to the normal mode. However, as shown in FIG. 7, the scanning drive circuit 3 and the signal drive circuit 1 Drive / operation frequency can be further reduced, and power consumption can be further reduced. In this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance by ½ in the vertical direction.

  Alternatively, the frequency ratio of the HSYNC (IN) and DCLK (IN) input from the interface circuit 7 to the signal driving circuit 1 to the signal drive circuit 1 in the power save mode is set to VSYNC (IN If the frequency ratio of the vertical synchronizing signal input from the interface circuit 7 is 1/2, for example, the driving / operation of the signal driving circuit 1 is the same as that shown in FIG. The frequency can be slowed and the power consumption can be further reduced. Also in this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance by ½ in the vertical direction.

  Furthermore, the frequency ratio of the DCLK (IN) to the operation clock input from the interface circuit 7 is, for example, ½ of the frequency ratio of the horizontal synchronization signal input from the HSYNC (IN) interface circuit 7. As described above, in the signal driving circuit 1, the image data is taken into the first latch group every other pixel data, and the nth latch of the first latch group to the 2n-1th of the second latch group. If data is transferred in parallel to the 2n-th latch in synchronization with the horizontal synchronization signal HSYNC (IN), the horizontal direction and the resolution are halved in the normal mode. The driving / operating frequency of the circuit 1 can be further slowed down, and the power consumption can be further reduced. In this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance to ½ in the vertical direction.

  As described above, in the second embodiment, the predetermined image pattern as shown in FIG. 10 is displayed in the power save operation mode. By sequentially shifting the generation timing of the timing signals HSYNC (IN), VSYNC (IN), and DCLK (IN) with respect to the readout timing of the image pattern, the image pattern moves on the display screen. In this way, the user can easily recognize the power save state. In addition, it is possible to reduce deterioration in image quality such as a change in brightness and an afterimage caused by a change in characteristics of a film constituting a TFT, a change in characteristics of a liquid crystal material, and the like caused by displaying the same position for a long time.

  In the second embodiment, in the display control circuit shown in FIG. 9, switching between VSYNC, HSYNC, and DCLK in the normal mode and the power save operation mode is performed by controlling the oscillator and the control. This is realized by providing the circuit 21 and the selection circuit group 19. However, as shown in FIG. 11, the interface circuit is not divided in the normal mode but in the power save mode as shown in FIG. 7 may be realized by providing a frequency dividing circuit group 23 composed of frequency dividing circuits 23a, 23b, and 23c that respectively divide the horizontal synchronizing signal and the operation clock input from 7 at a predetermined frequency dividing ratio. .

  A third embodiment of the liquid crystal display device will be described below.

  In the third embodiment, the liquid crystal matrix panel 2 is driven by a line-by-line polarity inversion driving method. That is, as shown in FIG. 12, for each horizontal line, the polarity of the signal voltage is inverted and applied to the pixels of the liquid crystal matrix panel. Such application of the signal voltage is realized by inverting the polarity of the voltage supplied to the signal driving circuit for each horizontal line using the input HSYNC and DCLK in the voltage control circuit 6.

  In the third embodiment, a liquid crystal matrix panel 2 that can display gradations is used. The display gradation of each pixel is controlled by the value of the signal voltage supplied from the signal driving circuit 1. The configuration of the liquid crystal matrix panel 2 is the same as that shown in FIG.

  FIG. 13 shows waveforms of the signal voltage Vd corresponding to each gradation applied to the signal line and the voltage Vcom applied to the common electrode by the line-by-line polarity inversion driving method. As shown in the figure, the polarity of the voltage Vcom applied to the common electrode is inverted for each line, and the polarity of the signal voltage Vd is also inverted so as to maintain the absolute value of the voltage difference from the voltage Vcom. Note that the OFF voltage of the scanning voltage is in phase with the common voltage Vcom and has the same amplitude value. Further, the polarity of the signal voltage corresponding to the five gradations from black to white is inverted at the halftone 2.

  In the liquid crystal matrix panel 2 shown in FIG. 4, the potential difference between the signal electrode (drain electrode) and the common electrode is minimum, the potential difference between the signal electrode and the scanning electrode (gate electrode) is minimum, and the common electrode When the three conditions for minimizing the potential difference between the signal electrode and the signal electrode are satisfied, the power consumption is lowest. This is because a transient current flows through the parasitic capacitance due to the parasitic capacitance between the electrodes.

  Here, as understood from FIG. 13, the transient current is minimized in the case of white display. Accordingly, it is desirable that the entire screen is displayed in white when in the power save operation mode. However, this makes it impossible to visually recognize the operation state of the apparatus. Therefore, in this embodiment, a predetermined pattern is displayed as shown in FIG. 14 in the power save operation mode. Then, the background brightness is set to white or a halftone display close to white, and the pattern portion is set to a halftone display having a darker gradation than the background portion. Such pattern display can be performed in the same manner as in the second embodiment.

  In this case, since the background looks bright, the voltage applied to the light source 4 may be reduced, or the current flowing through the light source may be limited to lower the luminance. As a result, the power consumption of the display device can be further reduced. In particular, when the liquid crystal matrix panel 2 is used for both reflection type and transmission type, the power source of the light source 4 may be shut off.

  The third embodiment relates to a normally white mode liquid crystal matrix panel 2 that is brightest when no voltage is applied to the liquid crystal, but it is the most when no voltage is applied to the liquid crystal. When using the normally black mode liquid crystal matrix panel 2 that darkens, the background brightness is displayed in black or near halftone, and the pattern portion is displayed in halftone with a lighter gradation than the background. You just have to do it.

  When the liquid crystal matrix panel 2 capable of color display is used, the pattern may be displayed in a halftone that is brighter than the background of one of the three RGB colors.

  In the third embodiment, not only the polarity inversion driving method for each line but also the driving method for inverting the polarity for each pixel as shown in FIG. 15, the polarity as shown in FIG. The same applies to a driving method in which the polarity is inverted every time, a driving method in which the polarity is inverted every frame, or a driving method in which these are combined. Further, the liquid crystal matrix panel 2 can be similarly applied even if the number of gradations is not five.

  The fourth embodiment of the present invention will be described below.

  In the fourth embodiment, as in the third embodiment, a liquid crystal matrix panel 2 that can display gray scales is used.

FIG. 17 shows the configuration of the voltage control circuit 6 according to this embodiment.
As illustrated, the voltage control circuit 6 includes selection circuits 24 and 25 and a gradation circuit 26.

During the power save mode operation, when the power save control signal PS is input from the display control circuit 5, the selection circuit 24 changes the power supply voltage of the power supply VDR supplied to the gradation circuit 26 from VN1. Switch to VS1. Similarly, the selection circuit 25 switches the power supplied to the signal driving circuit 1 from VN2 to VS2. The relationship between the power supply voltages is VN1> VS1, VN2> VS2. That is, during the power save mode operation, the voltage applied to the gradation circuit 26 and the signal driving circuit 1 is reduced. Note that only one of the gradation circuit 26 and the signal driving circuit 1 may be lowered without simultaneously reducing the power supply.

  The gradation circuit 26 divides the power supply voltage supplied from the selection circuit at a predetermined ratio and outputs voltages V1 to Vk. Since VN1> VS1, the voltages V1 to Vk are reduced at a ratio of VS1 / VN1 during the power save mode operation. Note that the gradation voltages V1 to Vk are set at regular intervals according to the driving method (polarity inversion driving method for each line, polarity inversion driving method for each pixel, and polarity inversion driving method for each frame) described above. The polarity may be reversed.

Next, FIG. 18 shows a configuration of the signal driving circuit 1 according to the fourth embodiment.

As shown in the figure, as described above, the signal driving circuit 1 includes a latch group that sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and the transferred image data for one line for the next line. The output circuit 28 includes a logic circuit unit 27 including a second latch group that holds the image data until it is transferred and outputs the image data in parallel to the output circuit 28.

  Further, as shown in FIG. 19A, each output circuit 28 has a decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27, and a level according to the decode value. A selector unit 2800 having an analog selector for selecting one of the voltages V1 to Vk sent from the adjustment circuit 26, and a voltage selected by the analog selector 2800 are supplied to the power supply voltage VDR (VN2) supplied from the selection circuit 24. Alternatively, a driver circuit 2801 is provided that amplifies the signal using VS2) and applies the signal to the corresponding signal electrode.

As shown in FIG. 19B, the selector section of the output circuit 28 of the signal driving circuit 1 includes a decoder 2810 for decoding the value of the image data sent from the logic circuit section 27, and a decoder. A voltage dividing circuit 2890 that divides the voltages V1 to Vk sent from the gradation circuit 26 according to the threshold value and an analog selector 2800 that selects one of the divided voltages may be provided.

  The output circuit 28 can be configured in various ways. As shown in FIG. 19C, a decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27, and a decoder In accordance with the hold value, the sample hold circuit 2820 for holding the power supply voltage VDR at the timing of each clock signal DCLK, and the held power supply voltage VDR as a control input (for example, a gate voltage) A transistor (for example, FET) 2830 that selectively outputs any one of the voltages V1 to Vk sent from the adjustment circuit 26 can also be used.

  In any case, if the image data values are the same, the output voltage of the output circuit 28 is determined by the voltages V1 to Vk sent from the gradation circuit 26 and the power supply voltage VDR.

With the configuration as described above, the waveforms of the signal voltage Vd applied to the signal electrode and the power supply voltage VDR applied to the signal driving circuit 1 are the same as those in the non-power-saving operation mode and the power supply voltage. It changes as shown in FIG.

  In the figure, (a) shows the non-power-saving operation mode, and (b) shows the power-saving operation mode.

  As shown in the figure, in the power save operation mode, a low signal is caused by the influence of the gradation voltages V1 to Vk and the power supply voltage VDR, which are lowered as compared with the non-power save operation mode. A voltage is applied to the signal electrode. Therefore, the power consumption is also reduced compared to the non-power-saving operation mode.

  In this case, in the power save operation mode, the display is lower or higher in luminance than in the non-power save operation mode, but the power save operation is performed. In the operation mode, there is no problem because the user is not working.

  Normally, the scanning drive circuit 3 is provided with a driver circuit that sequentially drives the scanning lines by using the supplied power supply. Therefore, during the power save mode operation, the power supply supplied to the driver circuit is provided. Even if the voltage is lowered, the power consumption can be reduced as in the fourth embodiment.

  The fifth embodiment of the liquid crystal display device according to the present invention will be described below.

FIG. 21 shows the configuration of the voltage control circuit 6 according to the fifth embodiment.
As illustrated, the voltage control circuit 6 includes a gradation circuit 26, and the gradation circuit 26 includes gradation voltage generation circuits 26a to 26e.

Each of the gradation voltage generation circuits 26a to 26e generates gradation voltages V1 to Vk shown in FIG. 22A in the non-power-saving operation mode. Further, power - Se - Bed operating mode - the time of de generates gradation voltages of V1～V 2 shown in FIG. 22 (b).

  That is, only V1 and V2 are changed, and other output voltages are set to a constant voltage (Vc) so as not to change.

  In the figure, the voltage polarity is changed every horizontal scanning time ta by the line-by-line polarity inversion driving method.

  Further, in the fifth embodiment, a predetermined pattern is displayed on the liquid crystal matrix panel by the display control circuit 5 having the pattern generator 20 shown in FIG.

  For example, in the output circuit 28 shown in FIG. 19 (a), the voltages V1 and V2 are selected for the part displaying the pattern, and any one of the voltages V3 to Vk is selected for the other parts. As described above, the value of the image data output from the pattern generator 20 is given in advance.

  Accordingly, when the pattern shown in FIG. 23 is displayed, as shown in FIG. 24, the background portion 2300 is driven at a constant voltage level, and the portion 2301 for displaying the pattern has the voltages V1 and V2. Driven.

  The voltage control circuit 6 according to the fifth embodiment may be configured as shown in FIG.

  As shown in the figure, the voltage control circuit 6 includes a gradation circuit 26, a gradation circuit 41, a gradation control circuit 42, and a switch circuit 35.

  The gradation circuit 26 generates gradation voltages V1 to Vk whose polarities are inverted every horizontal scanning period shown in FIG. 22A from the supplied power supply voltage and the horizontal synchronization signal HSYNC. The grayscale voltages V1 to Vk whose polarities are inverted every horizontal scanning period shown in FIG. 22B are generated from the supplied power supply voltage and the horizontal synchronization signal HSYNC.

  The gradation control circuit 42 controls the switch circuit 35, selects the output voltage of the gradation circuit 26 and supplies it to the signal driving circuit 1 during the non-power-saving mode operation, and the power-saving mode is selected. During the operation, the output voltage of the gradation circuit 41 is selected and supplied to the signal drive circuit 1.

  The gradation control circuit 42 stops the operation of the gradation circuit 41 during the non-power-saving mode operation, and stops the operation of the gradation circuit 26 during the power-saving mode operation. To do. The operation can be stopped by, for example, stopping the supply of power, or stopping the supply of the horizontal synchronization signal HSYNC and the clock signal DCLK used to invert the polarity of the generated voltage.

  In the fifth embodiment, only V1 and V2 may be changed, and the other output voltages may be voltages having amplitudes smaller than those of V1 and V2.

  Alternatively, only V1 may be changed, the other output voltage may be constant or a voltage having an amplitude smaller than V1, and the character or the like may be simply driven by V1, and the background may be driven by another voltage.

  By doing so, it is possible to reduce the power consumption of a gradation circuit that is generally composed of a differential amplifier, a resistor, a capacitor, and the like. Furthermore, by making the voltage input to the signal driving circuit 1 constant or reducing the amplitude, current due to stray capacitance in the signal driving circuit 1 and the liquid crystal matrix panel 2 can be reduced, and power consumption can be reduced.

  As described above, according to the embodiments of the liquid crystal display device of the present invention, it is possible to reduce the power consumption in the power save operation mode while performing a constant display.

  In the above embodiment, the liquid crystal display device in which the signal driving circuit 1 drives the liquid crystal matrix panel according to the image data which is digital data has been described. However, the signal driving circuit 1 directly corresponds to the analog image signal. In an apparatus for driving a panel, the signal driving circuit 1 in the fourth embodiment may be configured as shown in FIG.

  That is, the input analog image signal 2850 is sequentially circulated based on the sample hold circuit 2803 for the number of signal electrodes sampled and held in synchronization with the sample clock signal 2804 corresponding to the data clock, and the sample clock signal. In particular, a logic circuit unit 2805 for providing a sampling operation permission signal of each sample hold circuit 2803 and a power supply voltage provided for each sample hold circuit and supplying the sample held voltage from the selection circuit 24. The driver circuit 2801 may be configured to amplify using (VN2 or VS2) and apply the signal to the corresponding signal electrode. In the case where the signal driving circuit 1 drives the liquid crystal matrix panel directly according to the analog image signal as described above, when the polarity is inverted for each line or frame, the polarity is inverted. In synchronization with the timing, a circuit for inverting the polarity of the analog image signal applied to the driving method signal driving circuit 1 and shifting the analog image signal voltage by the amount corresponding to the common voltage may be provided.

  In the sixth embodiment, when the signal driving circuit 1 directly drives the liquid crystal matrix panel according to the analog image signal using the signal driving circuit 1 shown in FIG. 26, the signal voltage shown in FIG. The pattern generator 20 may be configured to generate an analog image signal that is output from the signal driving circuit 1.

  In the above embodiment, when the liquid crystal display device 10 receives the power save control signal 2003 from the CPU 1001, the liquid crystal display device 10 shifts to the power save operation mode. The usage status of the device 1000 may be determined to automatically shift to the power save operation mode. For example, a frame buffer for storing one frame of image data in the liquid crystal display device 10 is provided, and the image data in the frame buffer and the input image data are determined to match to thereby determine two consecutive frames. -When the change between frames is obtained sequentially, and there is no change in the number of frames, it is determined that it is not currently used by the user and automatically enters the power save mode. This can be realized by making a transition. Alternatively, the state of the power switch may be directly read to shift to the power save operation mode.

It is a figure which shows the external appearance of the information equipment which concerns on the Example of this invention. It is a block diagram which shows the structure of the information equipment which concerns on the Example of this invention. It is a block diagram which shows the structure of the liquid crystal display device based on the Example of this invention. It is a block diagram which shows the structure of a liquid crystal matrix panel. It is a figure which shows the operation | movement at the time of normal mode of the liquid crystal display device based on the Example of this invention. FIG. 6 is a timing chart showing a driving voltage waveform in a normal mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 3 is a timing diagram showing a first drive voltage waveform in a power save mode of a liquid crystal display device according to an embodiment of the present invention. FIG. 6 is a timing chart showing a second drive voltage waveform in the power save mode of the liquid crystal display device according to the first embodiment of the present invention. It is a block diagram which shows the structure of the 1st display control circuit based on 2nd Example of this invention. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the 2nd display control circuit based on 2nd Example of this invention. It is a figure which shows the polarity of the voltage applied to a pixel by the polarity reversal drive method for every line. FIG. 5 is a timing diagram showing signal voltages corresponding to respective gradations applied to signal lines by a line-by-line polarity inversion driving method. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 3rd Example of this invention. It is a figure which shows the polarity of the voltage applied to a pixel by the polarity inversion drive method for every pixel. It is a figure which shows the polarity of the voltage applied to a pixel by the drive method which combined the polarity inversion drive method for every pixel and the polarity inversion drive method for every line. It is a block diagram which shows the structure of the voltage control circuit which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the signal drive circuit which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the output circuit which concerns on 4th Example of this invention. It is a timing diagram which shows the signal drive voltage waveform which concerns on 4th Example of this invention. It is a block diagram which shows the 1st structure of the voltage control circuit which concerns on 5th Example of this invention. It is a timing diagram which shows the output voltage waveform of the voltage control circuit which concerns on 5th Example of this invention. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 5th Example of this invention. FIG. 10 is a timing diagram showing drive voltage waveforms in a power save mode of a liquid crystal display device according to a fifth embodiment of the present invention. It is a block diagram which shows the 2nd structure of the voltage control circuit which concerns on 5th Example of this invention. It is a block diagram which shows the other structure of the output circuit based on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal drive circuit 2 Liquid crystal matrix panel 3 Scan drive circuit 4 Light source 5 Display control circuit 6 Voltage control circuit 7 Interface circuit

Claims (8)

A matrix panel having a plurality of scanning lines and a plurality of signal lines arranged to intersect the plurality of scanning lines, and supplying a signal voltage to each of the plurality of signal lines of the matrix panel In a display device comprising: a signal driver; and a voltage controller that generates a gradation voltage value for generating the signal voltage supplied by the signal driver.
The signal driver is
A gradation voltage value is selected according to image data for selecting a gradation voltage value from k (k is a natural number of 2 or more) gradation voltage values supplied by the voltage control unit, A first mode for generating the signal voltage based on the selected gradation voltage value and supplying the signal voltage to each of the plurality of signal lines of the matrix panel;
A gradation voltage value is selected from m (m is a natural number smaller than k) gradation voltage values supplied by the voltage control unit according to image data for selecting the gradation voltage value. And a second mode in which the signal voltage is generated based on the selected gradation voltage value and is supplied to each of the plurality of signal lines of the matrix panel.   The display device according to claim 1, wherein the gradation voltage value has a polarity that is inverted every certain period.   The display device according to claim 2, wherein the gradation voltage value is one in which the polarity is inverted at a constant period in accordance with a polarity inversion driving method for each frame of the matrix panel.   The display device according to claim 2, wherein the gradation voltage value is one in which the polarity is inverted at a constant period in accordance with a polarity inversion driving method for each pixel of the matrix panel.   The display device according to claim 2, wherein the grayscale voltage value is one in which the polarity is inverted at regular intervals in accordance with the polarity inversion driving method for each line of the matrix panel.   The display device according to claim 1, wherein the voltage control unit divides a power supply voltage to generate the gradation voltage value.   The display device according to claim 1, wherein the signal driving unit includes a voltage dividing circuit that divides a gradation voltage value supplied from the voltage control unit. The voltage control unit includes k grayscale voltage value generation units,
In the first mode, k gradation voltage values are generated from the k gradation voltage value generation units,
8. The display device according to claim 1, wherein in the second mode, m grayscale voltage values are generated from the k grayscale voltage value generation units. 9.