JP3755909B2 - Signal processing device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a signal processing device, and more particularly to a signal processing device for processing an audio signal to broaden a sound field feeling.
[0002]
[Prior art]
In recent years, in the field of audio / video products, surround playback systems have become popular. For example, a 5.1 channel independent digital compressed audio signal recorded in advance on a recording medium such as a disk, such as the “AC-3” system of Dolby Laboratories, Inc. The reverberation of a hall or the like that has been measured in advance, such as the “DSP (Digital Sound Processor)” method of Yamaha's “DSP (Digital Sound Processor)” method. There are things that reverberate audio signals are arithmetically synthesized using characteristics and output from the rear channel. In the above description, the 5.1 channel of 0.1 channel refers to a subwoofer audio signal with only ultra-low sounds.
[0003]
Each of these methods requires an extra speaker and amplifier for outputting rear channel audio signals during playback, and the configuration becomes large. For example, in products such as TVs, minicomponents, and radio cassettes, two-channel mains are required. In many cases, a surround effect is obtained in a pseudo manner only with a speaker.
[0004]
FIG. 6 shows a block schematic diagram of a conventional signal processing apparatus for artificially obtaining the surround effect using only such two-channel main speakers. In the figure, 1 and 2 are input terminals, 3 and 4 are buffer circuits, 5 and 9 are subtraction circuits, 10 is an addition circuit, 11 and 12 are output terminals, and 6 is an analog-digital conversion circuit (hereinafter abbreviated as "ADC"). ), 7 is a delay circuit, 8 is a digital-analog conversion circuit (hereinafter abbreviated as “DAC”), and 13 is a memory.
[0005]
The operation of the conventional signal processing apparatus configured as described above will be described below. The left audio signal S _LI input from the input terminal 1 is input to the _minus terminal of the subtraction circuit 5 and input to the buffer circuit 3. The output of the buffer circuit 3 is input to the + terminal of the subtracting circuit 9 and sent from the output terminal 11 to the outside of the apparatus as an output left audio signal _SLO . The right audio signal _SRI input from the input terminal 2 is input to the + terminal of the subtraction circuit 5 and input to the buffer circuit 4. The output of the buffer circuit 4 is input to one + terminal of the adder circuit 10 and sent from the output terminal 12 to the outside of the apparatus as an output right audio signal _SRO .
[0006]
These signal paths are main signal paths when the surround effect is not applied. Here, the buffer circuits 3 and 4 are circuits that simply perform impedance conversion and amplification, but may perform tone control, for example.
[0007]
Now, audio signal sent to the subtraction circuit 5 S _LI and the right audio signal S _RI is taken the difference is output as a differential audio signal S _DI. The purpose of this subtraction process is to simplify the subsequent circuits by combining the signal paths into one. The differential audio signal S _DI is quantified in ADC 6, it is sent to a delay circuit 7 as the difference audio data D _DI. In the delay circuit 7, accumulated the difference audio data D _DI temporarily in the memory 13, read after holding 30m seconds, sends the DAC8 as delayed speech data D _DL. DAC8 In mended again analog voltage delay audio data D _DL, and outputs the delayed audio signal S _DE.
[0008]
The delayed audio signal S _DE is subtracted from the output of the buffer circuit 3 in the subtracting circuit 9, and added to the output of the buffer circuit 4 in the adding circuit 10, and is output from the output terminals 11 and 12 to the outside of the apparatus, respectively. . At this time, the amplitude when the delayed audio signal _SDE is subtracted and added is made smaller than the outputs of the buffer circuits 3 and 4.
[0009]
When a signal subjected to such a series of processing is output from a speaker, the following effects are produced. First, since the left audio signal _SLI and the right audio signal _SRI are output in the positive phase (no polarity inversion) in the subtraction circuit 9 and the addition circuit 10, they are not adversely affected by this signal processing device. On the other hand, the delayed audio signal S _DE generated from the left audio signal S _LI and the right audio signal S _RI is delayed and attenuated, so that an echo effect is obtained at the time of output. In addition, the subtracting circuit 9 outputs the signal in the opposite phase (with polarity inversion) and is output from the output terminal 11, and the adding circuit 10 outputs the signal in the normal phase from the output terminal 12. Will do. Due to the loss of the echo effect and the sense of localization, it is possible to obtain an effect as if the sound field spread (hereinafter referred to as “surround effect”).
[0010]
[Problems to be solved by the invention]
However, the conventional signal processing apparatus as described above has a problem in that the memory 13 has a large capacity, and a large amount of elements are required for integration into an integrated circuit, resulting in an obstacle to downsizing and cost reduction.
[0011]
That is, the conversion rate in the above-described ADC 6 is normally about 14 ksps (samples per second) and the delay time in the delay circuit 7 is 30 milliseconds, so 420 pieces of differential audio data _DDI are required. . In order to store this in the memory 13, if 1 data is 12 bits, 5040 memory cells are required. In audio video products, it is common to use SRAM (Static Random Access Momery) to avoid unwanted radiation due to high-speed refresh operation of DRAM (Dynamic Random Access Memory). Over 20,000. Therefore, if the conventional signal processing apparatus as described above is made into one chip, it becomes a large-scale integrated circuit (hereinafter abbreviated as “LSI”), which makes it extremely difficult to reduce the cost and size.
[0012]
The present invention has been made in view of the above problems, and an object thereof is to provide a signal processing apparatus that can be configured with a small number of elements while maintaining the surround effect.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the signal processing apparatus of the present invention is configured to synthesize the audio signal and output a synthesized signal in order to widen the sound field feeling by processing the pair of left and right audio signals; Digitizing means for digitizing the signal and outputting a digitized synthesized signal, period changing means for changing the period of the digitized synthesized signal, voltageizing means for converting the output of the period changing means into voltage, and the voltage A signal processing apparatus comprising: mixing means for mixing the output of the converting means into the audio signal ,
The period changing means includes a storage means for storing the digitized synthesized signal, a periodic signal generating means for outputting a periodic signal having two different periods, and the digitized synthesized signal for the storage means according to the periodic signal. Control means for controlling writing and reading of
The control means controls writing to the storage means with a periodic signal having a shorter period among the periodic signals, and controls reading from the storage means with a longer periodic signal. The writing starts from address 0 to write to the full address, and when it reaches the full address, the writing address is returned to the address 0 again. During that time, reading starts at the address 0 and does not reach the full address. A part of the digitized synthesized signal written in the storage means is discarded by interrupting and returning to address 0.
[0016]
[Action]
The left and right audio signals are synthesized by the synthesizing means to be a synthesized signal. The synthesized signal is converted into a digitized synthesized signal by the digitizing means, and the period of the digitized synthesized signal is changed by the period changing means. By correcting the voltage and mixing the sound signal again with the mixing means, a pseudo sound field spread is obtained.
[0017]
Further, the number of elements of the storage means is obtained by performing writing to the storage means constituting the period changing means by using the shorter period signal output from the signal generation means and using the longer period signal at the time of reading. Will be suppressed.
[0018]
【Example】
The signal processing apparatus of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a signal processing apparatus of the present invention. In the figure, input terminals 1 and 2, buffer circuits 3 and 4, subtraction circuits 5 and 9, ADC 6, DAC 8, adder circuit 10, and output terminals 11 and 12 are the same as those in the conventional example, and the description thereof is omitted. .
[0019]
Output differentially audio data D _DI of ADC6 is sent to pitch conversion circuit 21, temporarily stored in the memory 22, sent to DAC8 is sequentially read as a change audio data D _P. As described above, the rough processing for obtaining the surround effect is similar to that of the conventional example, but the operation of the pitch conversion circuit 21 which is the main part for generating the surround effect is significantly different. The operation of the pitch conversion circuit 21 and its peripheral circuits will be described with reference to FIG.
[0020]
2, the clock generator 21a outputs a write clock C _W and the read clock C _R with two different periods, as shown in FIG. These write clock C _W and the read clock C _R is sent to the memory control circuit 21b, the write address signal AW and reading address signal AR in synchronization with the write clock C _W shown in FIG. 3, and the read clock C _R The signals are converted into four types of signals: synchronized write signal WE and read signal RD.
[0021]
Differential sound data D _DI is input to the input port P _I of the memory 22, the write signal WE is written in the period of the high to the address An of the memory 22 indicated to the write address signal AW. (Here, n represents a non-negative integer) data on the memory 22 is read signal RD is read out during the period of high from the address An indicated by the read address signal AR, from the output port P _O of the memory 22 change is output as the audio data D _P.
[0022]
Here, the address names A0 to A4 of the write address signal AW in FIG. 3 represent the same addresses as the address names A0 to A4 of the read address signal AR. In view of the range shown in the figure, the read address signal AR is only described up to A2. Also, in the figure, the delay in the output timing from the differential audio data _DDI to the changed audio data D _P is only a process for preventing an undefined data read operation during writing to the memory 22. Absent.
[0023]
As apparent from FIG. 3, the read clock C _R, since the period in comparison with the write clock C _W is set as long, the data Dn from the difference audio data D _DI to change the audio data D _P Propagation Will gradually be delayed. As a result, as shown in FIG. 4, the changed sound data D _P is obtained by extending the period of the difference sound data _DDI itself. 4, each point A~D on differential sound data D _DI corresponds to each point of the a'-d 'on change the audio data D _P.
[0024]
On the other hand, the writing and reading operations with respect to the storage capacity of the memory 22 by the processing as described above are schematically represented by FIG. The write operation starts from address 0 and is written up to the full address. When the full address is reached, the write address is returned to address 0 again as shown by the dashed line in the figure. During this time, the reading operation starts from address 0, is interrupted at address R in the middle, and returns to address 0 again as shown by the broken line in the figure. These write / read operations are performed in parallel in time. Here, “▼” in the figure represents the same time.
[0025]
By such processing, for example, in the differential audio data _DDI of FIG. 4, the hatched waveform surrounded by the dotted line in the figure is discarded, and depending on the signal waveform, the difference audio data _DDI and the next differential audio data _DDI are discarded. There may be discontinuities in the connection. However, the change audio data D _P is inherently very small compared to the outputs of the buffer circuits 3 and 4, and by including an appropriate low-pass filter (not shown) in the DAC 8, there is no problem in hearing. They confirmed.
[0026]
By the above series of processes, it changes the audio data D _P is converted to a change audio signal S _P with a voltage level at DAC 8, delays in the prior art speech signal S _DL and the buffer circuit 3 by the subtraction circuit 9 and the adder circuit 10 as well And 4 are mixed and output from the output terminals 11 and 12.
[0027]
Thus, change in intonation speech signal S _P which is shifted to the low frequency side is mixed into the main audio, improved sound field feeling apparent as in the conventional example, the spaciousness only output from two speakers The inventors experimentally confirmed that it can be obtained.
[0028]
As described above, according to this embodiment, the sound field feeling can be improved only by shifting the differential audio data _DDI to the low frequency side in the pitch conversion circuit 21. Therefore, the capacity of the memory 22 attached to the pitch conversion circuit 21 can be smaller than the case where the differential audio data _DDI is delayed, and according to experiments by the inventors, the capacity is reduced to 1/2 to 1/5. Even so, it has been confirmed that the same surround effect as the conventional example can be obtained.
[0029]
In the above description, the output signals of the memory control circuit 21b are four, AW, WE, AR, and RD. For example, the memory 22 is a FIFO (First In First Out) and only two input / output pointers are provided. It may be. In addition, the present invention can be variously modified.
[0030]
【The invention's effect】
As described above, according to the present invention , the left and right audio signals are synthesized by the synthesizing unit to be a synthesized signal, and the synthesized signal is converted into the digitized synthesized signal by the digitizing unit, and the digitized synthesized signal is then converted by the period changing unit. The sound field can be broadened by changing the period of the sound signal and adjusting the voltage by the voltage converting means and mixing the sound signal again with the mixing means.
[0031]
In addition, writing to the storage means constituting the period changing means is performed by using the shorter cycle signal output from the signal generating means, and by using the longer cycle signal for reading, the memory cell of the storage means is used. The number and the number of transistor elements can be reduced to 1/2 to 1/5 of the conventional one.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a signal processing apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a main part in the same embodiment.
FIG. 3 is a signal waveform diagram of main parts in the same example.
FIG. 4 is a diagram showing input / output waveforms of main parts in the same example.
FIG. 5 is a schematic diagram showing the operation of the main part in the same embodiment.
FIG. 6 is a block schematic diagram of a signal processing apparatus in a conventional example of the present invention.
[Explanation of symbols]
1, 2 Input terminals 3, 4 Buffer circuit 5, 9 Subtraction circuit 6 ADC
8 DAC
10 adder circuit 11, 12 output terminal 21 pitch conversion circuit 22 memory

Claims (3)

To broaden the sound field feeling by processing a pair of left and right audio signals, synthesizing means for outputting a synthesized signal by synthesizing the speech signal, and digitizing means for outputting the digitized composite signal by digitizing the combined signal comprises a period changing means for changing the period of the digitized composite signal, and the voltage means for converting the output of the period changing means into a voltage, and a mixing means for mixing the output of the voltage reduction means to the speech signal A signal processing device comprising:
The period changing means includes a storage means for storing the digitized synthesized signal, a periodic signal generating means for outputting a periodic signal having two different periods, and the digitized synthesized signal for the storage means according to the periodic signal. Control means for controlling writing and reading of
The control means controls writing to the storage means with a periodic signal having a shorter period among the periodic signals, and controls reading from the storage means with a longer periodic signal. The writing starts from address 0 to write to the full address, and when it reaches the full address, the writing address is returned to the address 0 again. During that time, reading starts at the address 0 and does not reach the full address. A signal processing apparatus characterized by discarding a part of the digitized synthesized signal written in the storage means by interrupting and returning to address 0 . 2. The signal processing apparatus according to claim 1, wherein the mixing unit adds the output of the voltage converting unit to one of the audio signals and subtracts the other . The signal processing apparatus according to claim 1, wherein the voltage converting unit includes a low-pass filter .

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