JP3756655B2 - Manufacturing method of build-up multilayer substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention includes a core substrate, an insulating layer formed on one side or both sides thereof, and a wiring layer. Rubi The present invention relates to a method for manufacturing a rolled-up multilayer substrate.
[0002]
[Prior art]
Various methods are known as a method for manufacturing a build-up multilayer substrate using a core substrate, and a forming method by a semi-additive method, which is one of them, will be described below with reference to FIGS. .
In order to form the build-up multilayer substrate 200, the core substrate 100 for build-up multilayer substrate is prepared in advance (see FIG. 8A). The core substrate 100 includes a core substrate body 101 made of a glass-resin composite material, for example, a glass fiber-BT (bismaleimide-triazine) resin composite material, and a through hole 101h is provided between the front and back surfaces 101a and 101b. Is formed. In addition, wiring layers 103a and 103b having predetermined patterns are formed on the front surface 101a and the back surface 101b, respectively, and the wiring layers 103a and 103b are electrically connected through the through-hole wiring layer 103h formed in the through hole 101h. . These wiring layers 103a, b, h are all made of Cu.
[0003]
First, as shown in FIG. 8 (b), a photosensitive epoxy resin paste is applied and semi-dried in the front and back surfaces 101a, 101b and the through holes 101h of the core substrate body 101, cured after exposure and development, A resin layer 104 is formed. The resin layer 104 includes a first surface resin layer 104a, a first back surface resin layer 104b, and an in-hole resin layer 104h. Via holes 104av and 104bv are provided at predetermined positions on the first front and back surface resin layers 104a and 104b, respectively. The wiring layers 103a, 103b are exposed at the bottom surfaces of the via holes 104av, bv.
Further, in order to improve the adhesion with the electroless plating described below, a roughening agent containing an oxidizing agent such as potassium permanganate or chromic acid is used to form the first and back resin layers 104a and 104b. The surface is roughened and catalyst nuclei are added.
[0004]
Next, as shown in FIG. 8C, the electroless plating layers 105a and 105b are formed thinly (about 1 to 3 μm) on the entire surface of the first front and back resin layers 104a and 104b by Cu electroless plating. . The electroless plating layers 105a and 105b provide conductivity to the entire surface of the first front and back resin layers 104a and 104b.
Thereafter, as shown in FIG. 8 (d), a photosensitive plating resist is formed on the electroless plating layers 105a and 105b, and further exposed and developed to form a predetermined pattern, thereby forming resist layers S1a and S1b. To do.
[0005]
Further, as shown in FIG. 9A, a voltage is applied using the electroless plating layers 105a and 105b as common electrodes, and the electroless plating layers 105a and 105b where the resist layers S1a and S1b are not formed by Cu electrolytic plating. An electrolytic plating layer (thickness of about 10 to 20 μm) is deposited on the exposed portion of the substrate to increase the thickness, thereby forming the first front and back wiring layers 106a and 106b. Needless to say, the thickness of the electroless plating layers 105a and 105b does not increase below the resist layers S1a and S1b.
Next, as shown in FIG. 9B, the resist layers S1a and S1b are removed, and the electroless plating layers 105a and 105b located below the resist layers S1a and S1b are removed by soft etching to remove each wiring. The layers 106a and 106b are separated and made independent.
[0006]
Thereafter, by repeating the steps described with reference to FIGS. 8B to 9B, as shown in FIG. 9C, the second front and back resin layers 114a, 114b and the second resin layer 114 Front / back wiring layers 116a, 116b are formed. Thereafter, the resin layer and the wiring layer can be formed in the same manner.
Then, for example, three wiring layers (for example, 103a, 106a, and 116a) are formed on the front and back sides, respectively, and a third front and back resin layer (front and back solder) is formed as shown in FIG. Resist layers) 124a and b are formed. Further, the connection pads 127a, b are formed on the second front / back wiring layers 116a, b exposed in the openings 124av, bv, thereby completing the build-up multilayer substrate 200.
[0007]
[Problems to be solved by the invention]
By the way, in forming the build-up multilayer substrate 200 by such a method or the like, in actuality, the core substrate 100 is handled in the upper, lower, right and left or the periphery in addition to the region where the product (build-up multilayer substrate) is formed. In order to facilitate positioning, etc., it is usual to provide a portion (abandonment area, abandonment allowance) that is finally removed without being a product.
For example, as shown in FIG. 10A, the core substrate body 101 of the core substrate 100 has a substantially square shape in plan view, and a product formation region in which a build-up multilayer substrate as a product is scheduled to be formed. 101S and a surrounding area, which is a final disposal area 101T that is removed without becoming a product. In this example, four small product formation regions 101S1, 101S2, 101S3, and 101S4 surrounded by a solid line and a two-dot chain line in FIG. 10A are adjacent so that four build-up multilayer substrates can be manufactured in the final product. Thus, they are gathered in a square shape (two steps and two rows) to constitute one product formation region 101S. The discard area 101T is formed in a square shape so as to surround the product formation area 101S.
[0008]
Among these, the structure of the core substrate 100 in the product formation region 101S (for example, the small product formation region 101S3) is a partial enlarged cross-sectional view of the B portion in the XX ′ cross section in FIG. As can be seen from b), it is the structure of the core substrate described above (see FIG. 8A). That is, a through hole 101h is formed between the front and back surfaces 101a and b of the core substrate body 101, and wiring layers 103a and 103b are formed on the front and back surfaces 101a and 101b, respectively, and are formed in the through hole 101h. The wiring layers 103a and 103b are electrically connected via the through-hole wiring layer 103h.
[0009]
On the other hand, as can be seen from FIG. 10C, the cross-sectional structure of the core substrate 100 in the discarding area 101T is the same as that of the core substrate body 101 except for portions where marks such as positioning marks and product number display marks (not shown) are formed. The front and back surfaces 101a and 101b are exposed. As described above, when forming the resin layers 104a, 104b, 114a, 114b, etc., buffing or the like may be performed to flatten the surface of the resin layer. At this time, in order to process the resin layer 104a and the like flatly over the entire product formation region 101S, a rectangular shape surrounding the product formation region 101S is formed in the disposal region 101T, for example, as indicated by a broken line in FIG. A dummy pattern 102 made of a metal layer may be formed.
[0010]
Actually, the build-up multilayer substrate 200 is manufactured by using the core substrate 100 by the above-described method or the like. In this case, it has been found that the following problems occur.
That is, when the first front / back surface resin layers 104a and 104b are formed in the product formation region 101S of the core substrate 100 shown in FIG. 10 and Cu electroless plating is performed, the product formation region 101S has the structure shown in FIG. As shown, electroless plating layers 105a, 105b are formed over the entire upper surface of the first front / back resin layers 104a, 104b. This is as described above (see FIG. 8C). On the other hand, in the discarded region 101T, as shown in FIG. 11B, the electroless plating layers 105A and 105B are directly formed on the front and back surfaces 101a and 101b of the core substrate body 101.
[0011]
By the way, in the product formation region 101S, prior to the electroless plating, the surfaces of the first front and back resin layers 104a and 104b are roughened with an oxidizing agent to improve the adhesion with the electroless plating layers 105a and 105b. Done. For this reason, the electroless plating layers 105a and 105b are not peeled off thereafter.
[0012]
On the other hand, in the disposal area 101T, similarly, the electroless plating layers 105A and 105B are formed directly after contacting the oxidant with the front and back surfaces 101a and 101b of the core substrate body 101. However, the glass fiber-BT resin composite The front and back surfaces 101a and 101b of the core substrate made of material are not easily roughened by the oxidizing agent as described above. This is because the core substrate body 1 is made of a material having higher chemical resistance than the first front / back surface resin layer 104 and the like because it is repeatedly exposed to a plating solution, an etching solution, an oxidant, and the like.
[0013]
Therefore, after that, for example, in the electroless plating process, the subsequent resist coating, exposure, development process, electrolytic plating process, etching process, and the upper resin paste coating process, as shown in FIG. Part of the electrolytic plating layers 105A and 105B (including the case where the thickness is increased by electrolytic plating) may become a metal flake (hereinafter also simply referred to as a flake) 105p and peel off. When this thin piece 105p is generated, for example, there are cases where the wiring is short-circuited or the insulation resistance is lowered, or when light is blocked by the thin piece 105p during exposure, resulting in a defective exposure pattern of the resist or resin layer. The problem occurs.
[0014]
The present invention has been made in view of such problems, and an object of the present invention is to form a build-up multilayer substrate using a core substrate having a product formation region and a discard region in a discard region. Core board for build-up multilayer boards that suppresses and prevents problems due to metal flakes that have been peeled off from the electroless plating layer Used The object is to provide a method for manufacturing a build-up multilayer substrate.
[0015]
[Means, actions and effects for solving the problems]
First, As core substrate , Having a substantially plate shape having a front surface and a back surface, having a core substrate body having a product formation region and a discard region, and a metal layer that is well adhered to the front surface and the back surface in the discard region, The core layer for a build-up multilayer board, wherein the metal layer is formed on at least substantially the entire surface of the area where the resin layer is not to be formed, among the front and back surfaces of the core board body in the discard area. It is preferable to use .
[0016]
Has the above configuration Rubi The core substrate for a rolled-up multilayer substrate includes a metal layer that is well adhered to the front and back surfaces in the disposal area of the core substrate body, and the metal layer is formed on substantially the entire area where the resin layer is not formed. ing.
As described above, an insulating resin layer is formed on at least one of the front surface and the back surface of the core substrate in the manufacturing process of the build-up multilayer substrate, and then an electroless plating layer is formed. At this time, not only the electroless plating layer is formed on the insulating resin layer, but also the electroless plating layer is formed on the front and back surfaces in the discarded area where the insulating resin layer is not formed.
here, This In this core substrate, since the metal layer is provided on substantially the entire surface of the resin non-formation area in the disposal region, the electroless plating layer is deposited on the metal layer in addition to the insulating resin layer. The electroless plating layer deposited on this metal layer has higher adhesion strength with its base (ie, metal layer) than that deposited on the front and back surfaces of the core substrate without the metal layer. In the plating process and subsequent processes such as application of the resin paste and the like, the occurrence of metal flakes due to peeling of the electroless plating layer is suppressed / prevented. Therefore, the peeled metal flakes do not cause problems such as a short circuit and an exposure pattern defect.
[0017]
Here, the state in which the metal layer is in good contact refers to a state in which the metal layer is in close contact with the core substrate with a strength that does not peel off in plating, etching, resin paste application, and other processes.
In addition, the metal layer may be formed by any method as long as it is in good contact with the disposal region of the core substrate body, for example, specifically, on one or both sides of the uncured prepreg. Examples of the metal foil include a metal foil that is stacked and cured by hot pressing or the like, and is stuck to one or both sides of the core substrate body, or a panel that is further plated to increase the thickness.
[0018]
In addition, it is preferable that the metal layer is formed over the entire surface at least in the area where the resin layer is not formed, on the front surface and the back surface of the core substrate body in the disposal region. However, in consideration of the risk of flakes occurring in each part such as the core board positioning through-hole, positioning mark, part number display mark, and the peripheral part of the core board, the front and back surfaces of the core board It is sufficient to expose a part of the metal layer and set a part without the metal layer so that the metal layer is provided on the substantially entire surface.
Further, the material of the metal layer is preferably made of substantially the same metal component as the electroless plating layer scheduled to be formed later. This is because the electroless plating layer is in close contact with the metal layer, and is more difficult to peel off. The material of the metal layer may be selected in consideration of easiness of formation, resistivity, and the like. Specifically, for example, when a Cu electroless plating layer is used for the electroless plating layer, a metal is used. It is mentioned that Cu is used for the layer.
[0019]
Furthermore, the product formation region refers to a region where a build-up multilayer substrate that will eventually become a product is formed, but is not limited to the case where one build-up multilayer substrate is formed within one product formation region. A plurality of build-up multilayer substrates may be formed in one product formation region. Also, there may be a plurality of product formation regions such as islands scattered within one core substrate body.
Further, the resin layer non-formation planned area (hereinafter also simply referred to as non-schedule area) is an area that is virtually set to at least one of the front surface and the back surface of the core substrate body, In the manufacturing process, it refers to an area other than an area where an insulating resin layer is planned to be formed (resin layer formation scheduled area, hereinafter also simply referred to as a scheduled area). Therefore, the boundary line between the planned area and the non-scheduled area is not formed on the actual core substrate. Since the insulating resin layer is formed on at least one of the front surface and the back surface, the resin layer formation planned area also exists on at least one of the front and back surfaces correspondingly. Therefore, when the insulating resin layer is scheduled to be formed only on one side (for example, the front surface), there is no planned area on the other surface (for example, the back surface), and only the non-scheduled area. Therefore, on this other surface (for example, the back surface), a metal layer is formed on substantially the entire back surface of the core substrate body in the discarded region.
[0020]
The material of the core substrate body may be made of a material that is less likely to be roughened than the material of the insulating resin layer that is planned to be formed later. In manufacturing the build-up multilayer substrate, the insulating resin layer is repeatedly roughened in order to form the insulating resin layer in multiple layers. For this reason, if the material is harder to roughen than the insulating resin layer, even if the roughening process is repeated, the core substrate body is repeatedly roughened, resulting in extreme roughening and reduced strength. It is because it can prevent. Therefore, as the material of the core substrate body, it is preferable to use a material made of an easily roughened material to which no filler is added. Specifically, for example, glass fiber-BT resin composite material, glass fiber-PPE resin are used. Examples include composite materials.
[0021]
further, As the core substrate, the above A core substrate for a buildup multilayer substrate, comprising a product adjacent portion in which at least one of a front surface and a back surface of the core substrate body is exposed in a portion adjacent to the product formation region in the discarding region. Core board for build-up multilayer boards characterized by It is preferable to use .
[0022]
Has the above configuration Rubi In the core substrate for a rolled-up multilayer substrate, a product adjacent portion where at least one of the front surface and the back surface of the core substrate body is exposed is provided at a portion adjacent to the product formation region.
As described above, after the build-up multilayer substrate, which is a product, is completed, both are cut at the boundary portion between the discard area and the product formation area, and the discard area is removed, but on the cutting line (part to be cut) When there is a metal layer, a part of the metal layer becomes a metal cutting waste such as a whisker at the time of cutting, and is likely to cause a short circuit or the like.
This In the core substrate for buildup multilayer substrate, at least one of the front and back surfaces of the core substrate body is exposed in the product adjacent area adjacent to the product formation area in the discarded area, so that metal cutting scraps are generated. Therefore, it is possible to suppress a short circuit caused by metal cutting waste.
In particular, it is more preferable to expose both the front surface and the back surface of the core substrate body in the adjacent part of the product, because the metal layer is not cut at the time of cutting.
[0023]
Here, the product adjacent portion refers to a portion adjacent to the product formation region in the disposal region, and at least one of the front surface and the back surface of the core substrate body is exposed. In addition, when the product formation regions are scattered in an island shape within the substrate plane of the core substrate body, the product adjacent portions adjacent to each product formation region may be adjacent and integrated. That is, a plurality of product formation regions may exist in one product adjacent portion.
[0024]
More preferably, Above A core substrate for a buildup multilayer substrate, wherein a portion adjacent to the product formation region in the discarded region is provided with a product adjacent portion where both the front surface and the back surface of the core substrate body are exposed. It is preferable to use a core substrate for a buildup multilayer substrate.
The core substrate for a buildup multilayer substrate thus configured includes a product adjacent portion where both the front surface and the back surface of the core substrate body are exposed. Therefore, when cutting both at the boundary portion between the disposal region and the product formation region, metal cutting waste is not generated, and short circuit due to metal cutting waste can be prevented.
[0025]
And Claim 1 or claim 2 The solution described in Above A build-up multilayer substrate manufacturing method using a core substrate for a build-up multilayer substrate, comprising: a resin layer forming step of forming an insulating resin layer of a predetermined pattern in a resin layer formation scheduled area; And an electroless plating step of forming an electrolytic plating layer.
[0026]
The manufacturing method of the build-up multilayer substrate of the present invention having the above-described configuration is as follows. Above Using the core substrate for a build-up multilayer substrate, an insulating resin layer having a predetermined pattern is formed in a resin layer formation scheduled area, and an electroless plating layer is formed on the insulating resin layer.
Since this core substrate is formed with a metal layer on substantially the entire surface of the resin layer non-formation planned area, if the electroless plating layer is formed after forming the insulating resin layer in the planned area, the non-planned area of the discarded area An electroless plating layer is deposited on the metal layer. In the discarded area, the electroless plating deposited on the insulating resin layer is difficult to peel off from the insulating resin layer. Furthermore, unlike the case where the electroless plating layer deposited on the metal layer is deposited on the front and back surfaces of the core substrate body, the electroless plating layer adheres well to the metal layer and is not easily peeled off. In the process, resin paste application, and other processes, the electroless plating layer deposited on the metal layer is not peeled off. For this reason, generation | occurrence | production of a metal flake is prevented by the metal layer, or generation | occurrence | production of a metal flake is suppressed by the part in which the metal layer is formed.
Therefore, a highly reliable build-up multilayer substrate can be manufactured with a high yield without causing or suppressing problems such as a short circuit or an exposure pattern defect by the metal flakes.
[0027]
And claims 3 The solution described in (1) is a method for manufacturing a build-up multilayer substrate, which has a substantially plate shape having a front surface and a back surface, has a core substrate body having a product formation region and a discard region, and the above-mentioned in the discard region. Forming a resin layer having a predetermined pattern on at least one of the front and back surfaces of the core substrate body including the product formation region, using a core substrate having a metal layer that is well adhered to the front and back surfaces, respectively. And an electroless plating step of forming an electroless plating layer on the insulating resin layer, and in the resin layer forming step, an exposure in which the front and back surfaces of the core substrate body are exposed in the discarded region. A method for producing a build-up multilayer substrate, wherein the surface is covered with the insulating resin layer over substantially the entire surface.
[0028]
In the manufacturing method of the build-up multilayer substrate of the present invention having the above-described configuration, an insulating resin layer is formed in the resin layer forming step, and an electroless plating layer is further formed in the electroless plating step. In this resin layer forming step, In the discarded area, the exposed surface where the front and back surfaces of the core substrate body are exposed is covered with an insulating resin layer over substantially the entire surface.
Thereby, the part which was not covered with the insulating resin layer in the discarded area is in a state where the metal layer is substantially exposed. Thereafter, an electroless plating layer is formed on the insulating resin layer and the metal layer by an electroless plating process. In addition to the electroless plating layer on the insulating resin layer, the electroless plating layer on the metal layer is also in close contact with the metal layer and hardly peels off.
Accordingly, it is possible to suppress / prevent the occurrence of metal flakes due to peeling of the electroless plating layer in the discarded area.
Therefore, the metal flakes can produce a highly reliable build-up multilayer substrate with a high yield without causing or suppressing problems such as short circuits and defective exposure patterns.
[0029]
And claims 4 The solution described in claim 3 The build-up multilayer substrate manufacturing method according to claim 1, wherein the core substrate is exposed to at least one of a front surface and a back surface of the core substrate body in a portion adjacent to the product formation region in the discarding region. A buildup multilayer substrate manufacturing method characterized by comprising a product adjacent portion to be manufactured.
[0030]
The manufacturing method of the build-up multilayer substrate of the present invention having the above-described configuration includes a product adjacent portion in which at least one of the front surface and the back surface of the core substrate body is exposed in a portion adjacent to the product forming region in the discarded region.
For this reason, when the build-up multilayer wiring board is completed, for example, when the product formation region and the disposal region are cut and separated, generation of metal cutting scraps due to cutting the metal layer is suppressed. Accordingly, it is possible to suppress problems such as a short circuit due to metal cutting waste.
In particular, if the core substrate body is exposed on both the front and back surfaces of the core substrate body in the adjacent part of the product, the metal layer is not cut at the time of cutting, so the occurrence of metal cutting waste is reliably prevented, More preferred.
[0031]
And claims 5 The solution described in claim 3 Or claims 4 The buildup multilayer substrate manufacturing method according to claim 1, wherein the electroless plating layer is made of substantially the same metal component as the metal layer.
[0032]
In the method for manufacturing a buildup multilayer substrate of the present invention having the above-described configuration, the material of the electroless plating layer is composed of substantially the same metal component as the metal layer.
For this reason, when the electroless plating layer is deposited on the metal layer, since it is the same component as the metal layer, the adhesion is particularly good and it is difficult to peel off, and the generation of metal flakes can be prevented more reliably.
The material of the electroless plating layer may be selected in consideration of the ease of plating, the resistivity of the electroless plating layer, and the like. For example, specifically, when Cu is used for the metal layer, The case where a Cu electroless plating layer is formed also in the electroless plating layer is mentioned.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings. As shown in FIGS. 1B and 1C, the core substrate 10 shown in FIG. 1 includes a core substrate body made of a glass fiber-BT resin composite material. The core substrate body 1 has a square plate shape in plan view having a size of 250 × 250 mm and a plate thickness of 1.0 mm. In the plane of the core substrate body 1, four small product formation regions (for example, 1SA1, 1SA1, etc.) on which build-up multilayer substrates (hereinafter also simply referred to as products) having a size of 40 × 40 mm are scheduled to be formed. 1SA2, 1SA3, 1SA4) are adjacent to each other and gathered in a square shape (two steps and two rows) to form one product formation region (for example, 1SA). Further, the four product formation regions 1SA, 1SB, 1SC, 1SD are arranged in two rows and two rows with a slight gap (20 mm) therebetween.
[0034]
Further, between and around each product formation region 1SA is a discarding region 1T that is removed after the product is completed. In the discarded area 1T, the product adjacent portion 1TP is formed in a square shape (frame shape) with a width of 5 mm in the vicinity of the boundary with each product forming area 1SA, 1SB, 1SC, 1SD in FIG. The front and back surfaces 1a and 1b (only the front surface 1a is shown in FIG. 1A) of the core substrate body 1 are exposed, which are portions adjacent to the region 1SA and the like. Further, in the present embodiment, the remaining portion 1TZ of the discard area 1T has a substantially square shape in FIG.
Further, the remaining portion 1TZ has a substantially cross-shaped intermediate remaining portion 1TZm positioned between each product adjacent portion 1TP in FIG. 1A and a remaining portion of the intermediate substrate 1TZm having a width of 25 mm positioned on the periphery of the core substrate. It consists of an approximately square-shaped (frame-shaped) peripheral remaining portion 1TZp.
[0035]
Further, of the core substrate main body surface 1a, each of the product forming regions 1SA, 1SB, 1SC, 1SD, each product adjacent portion 1TP, and the intermediate remaining portion 1TZm is included, and the outer peripheral edge shown by a one-dot chain line in FIG. The substantially square (200 × 200 mm) area is a resin layer formation scheduled area 1Ua where the insulating resin layer 4a is scheduled to be formed, as will be described later. Conversely, the area outside the one-dot chain line is the resin layer non-formation planned area 1Na. Therefore, the insulating resin layer 4a is formed not only on each product formation region 1SA and the like but also on each product adjacent portion 1TP and the intermediate remaining portion 1TZm (see FIG. 2A). In the present embodiment, since the insulating resin layers 4a and 4b are formed on the front surface 1a side and the back surface 1b side, although not shown, the insulating resin layer 4b is scheduled to be formed similarly. Region 1Ub and resin layer non-formation planned area 1Nb are also set.
However, the planned areas 1Ua and 1Ub and the non-scheduled areas 1Na and 1Nb are virtually set areas, and a boundary line between the planned areas and the non-scheduled areas is formed on the core substrate 10. Do not mean.
Similarly, for the convenience of explanation, the remaining portion 1TZ is divided into an intermediate remaining portion 1TZm and a surrounding remaining portion 1TZp. However, in the actual core substrate 10, no boundary line or the like is formed between them.
[0036]
Here, the structure of the core substrate 10 in the product formation region 1SA or the like (for example, the product formation region 1SC) is a partially enlarged cross-sectional view of a portion D in the YY ′ cross section in FIG. As can be seen from b), the structure is the same as that of the conventional core substrate (see FIG. 8A). That is, a through hole 1h is formed between the front and back surfaces 1a and b of the core substrate body 1, and wiring layers 3a and b (thickness 30 μm) made of Cu are formed on the front and back surfaces 1a and b, respectively. The wiring layers 3a and 3b are electrically connected to each other through a through-hole wiring layer 3h made of Cu, which is formed in the inner 1h.
[0037]
On the other hand, the remaining portion 1TZ of the discarded region 1T is the portion of the core substrate body 1 as can be seen from FIG. 1C which is a partially enlarged sectional view of the E portion of the YY ′ cross section in FIG. Metal layers 3A and 3B (thickness 30 μm) made of Cu are formed on the front and back surfaces 1a and 1b. Moreover, as shown in FIG. 1A, the metal layers 3A and 3B are formed on the entire surface of the remaining portion 1TZ excluding the product adjacent portion 1TP in the discarded region 1T.
Therefore, in the present embodiment, the metal layers 3A and 3B are formed on the front and back surfaces 1a and 1b of the core substrate body 1 even in the square-shaped peripheral remaining portion 1TZp that enters the resin layer non-formation planned area 1Na in the disposal region 1T. Is formed.
[0038]
Using the core substrate 10, a build-up multilayer substrate is formed in the same manner as the conventional method described above. Insulating resin layers 4 (4a, 4b) are respectively formed as planned in the resin layer formation scheduled areas 1Ua, 1Ub, which are indicated by a one-dot chain line in FIG. That is, a photosensitive resin paste containing epoxy resin as a main component is applied to the core substrate body surface 1a including each product forming region 1SA and the like and surrounding each product adjacent portion 1TP and intermediate remaining portion 1TZm, and exposed and developed. Further, the insulating resin layer 4 (4a, 4b) is formed by further curing and forming vias through which the wiring layers 3a, 3b are exposed in openings at predetermined positions. In FIG. 2A, the first surface resin layer 4a on the core substrate body surface 1a side is displayed. As can be seen from FIG. 2A, the core substrate body surface 1a exposed in the product adjacent portion 1TP in the discarded region 1T is entirely covered with the first surface resin layer 4a. In the electrolytic plating process, the electroless plating layer is not deposited directly on the core substrate surface 1a. The intermediate remaining portion 1TZm is also covered with the first surface resin layer 4a.
Although not shown, on the core substrate main body back surface 1b side, the back surface 1b exposed in the product adjacent portion 1TP is similarly covered with the first back surface resin layer 4b.
[0039]
After forming the insulating resin layer 4 (first and rear resin layers 4a and 4b) in this way, the surface of the insulating resin layer 4 (4a and 4b) is roughened with an oxidizing agent containing potassium permanganate, Then, after activating treatment and providing catalyst nuclei on the surface, Cu electroless plating is performed.
Then, as can be seen from FIG. 2B, which is a partial enlarged cross-sectional view of the D portion, among the cross sections on the YY ′ line shown in FIGS. 1A and 2A, the product formation region 1S. In the case of (for example, 1SC), the electroless plating layers 5a and 5b are formed over the entire surface of the first surface resin layer 4a and the first back surface resin layer 4b as in the conventional case (see FIGS. 8C and 11B). (Thickness 2 μm) is formed.
Although not shown, since the first front and back resin layers 4a and 4b are also formed in the product adjacent portion 1TP and the intermediate remaining portion 1TZm as described above, the electroless plating layers 5a and 5b are formed on the first front and back resin layers 4a and 4b. It is formed. Since the electroless plating layers 5a and 5b are formed after the first front and back resin layers 4a and 4b are roughened in advance, the electroless plating layers 5a and 5b have high adhesion and can be peeled off during or after the electroless plating process. Needless to say, no metal flakes are generated.
[0040]
On the other hand, as can be seen from FIG. 2C which is a partially enlarged sectional view of the E portion, the electroless plating layers 5A and 5B (thicknesses) are respectively formed on the metal layers 3A and 3B in the surrounding remaining portion 1TZp in the discarded region 1T. 2 μm) is formed.
That is, in the above-described conventional core substrate 100, the electroless plating layers 105A and 105B are directly formed on the front and back surfaces 101a and b of the core substrate body that are difficult to adhere (see FIG. 11B). The electroless plating layers 5A and 5B in the present embodiment are formed on the metal layers 3A and 3B made of Cu.
[0041]
In general, the electroless plating layer and the metal layer have high adhesion. Further, in the present embodiment, the material of the electroless plating layers 5A and 5B is the same as that of the metal layers 3A and 3B made of Cu. Cu, which is a metal component, was selected. That is, since the metal layers 3A and 3B are made of Cu that is substantially the same material as the electroless plating layers 5A and 5B deposited thereon, higher adhesion can be obtained. For this reason, the electroless plating layers 5A and 5B are not peeled off from the metal layers 3A and 3B, and conventional metal flakes are not generated.
Therefore, during this electroless plating process, the peeled flakes do not adhere to other portions, and the thickness of the electroless plating layers 5a and 5b does not become uneven. In addition, as will be described later, in subsequent processes such as resist coating, exposure development process, etching process, and resin paste coating process, the occurrence of defects such as short circuit and exposure failure due to the occurrence of metal flakes. It can be lost.
[0042]
Next, in the case where a build-up multilayer substrate is formed in the same manner as in the conventional process described above, refer to FIGS. 3 and 4 for the states of the product formation region 1SA and the like and the remaining portion 1TZp around the discard region 1T in the subsequent steps. However, it will be explained. 3 and 4, the right side in each drawing shows the cross-sectional structure of the D portion in FIG. 1A, that is, the product formation region 1S (1SC), and the left side in each drawing similarly shows the E portion. The structure of the surrounding remaining portion 1TZp around the discarded region 1T is shown in an enlarged manner.
[0043]
First, using the core substrate 10 (see FIGS. 2B and 2C) on which the electroless plating layers 5a, 5b, 5A, and 5B are formed, as shown in FIG. The resist layers R2a, R2b, R2A, and R2B are formed by applying on the electrolytic plating layers 5a, 5b, 5A, and 5B, and further exposing and developing to a predetermined pattern.
At this time, in the D portion, that is, in the product formation region 1S (right side in FIG. 3A), resist layers R2a and R2b having a predetermined pattern are formed on the electroless plating layers 5a and 5b, and there are no openings in the openings. Electrolytic plating layers 5a and 5b are exposed.
[0044]
On the other hand, in the E portion, that is, the remaining remaining portion 1TZp (left side in FIG. 3A), the resist layers R2A and R2B are formed on the entire surface of the electroless plating layers 5A and 5B, respectively. This is to prevent the unnecessary electrolytic plating layer from being deposited by preventing the electrolytic plating layer from being formed on the remaining portion 1TZ, which is an unnecessary portion, in the electrolytic plating step described below. Also in this step, the electroless plating layers 5A and 5B are in good contact with the underlying metal layers 3A and 3B, so that they do not peel off to produce metal flakes. Therefore, flakes are mixed in the paste-like resist at the time of applying the resist, shadows due to the flakes are not generated at the time of exposure, and pattern defects of the resist layers R2a and R2b are not caused.
Although not shown, the resist layers R2a and R2b are formed on the electroless plating layers 5a and b in the product adjacent portion 1TP and the intermediate remaining portion 1TZm. This is to prevent deposition of an unnecessary electrolytic plating layer. Of course, metal flakes are not generated in these portions 1TP and 1TZp.
[0045]
Next, a voltage is applied using the electroless plating layer 5a or the like as a common electrode to perform Cu electrolytic plating. As a result, as shown on the right side in FIG. 3B, in part D, electrolytic plating (thickness 15 μm) is deposited on the exposed parts of the electroless plating layers 5a and 5b where the resist layers R2a and R2b are not formed. The first front and back wiring layers 6a and 6b made of an electroless plating layer and an electrolytic plating layer are formed respectively. Needless to say, the thickness of the electroless plating layers 5a and 5b does not increase below the resist layers R2a and R2b.
On the other hand, as shown on the left side in FIG. 3B, the electrolytic plating layer is not formed in the peripheral remaining portion 1TZp (E portion) covered with the resist layers R2A and R2B. Also in this electrolytic plating process, since the electroless plating layers 5A and 5B are not peeled off, there is no problem such that the thin pieces adhere and the thickness of the electrolytic plating layers 6a and 6b is not uniform.
Although not shown, no electrolytic plating layer is formed on the product adjacent portion 1TP and the intermediate remaining portion 1TZm, and no metal flakes are generated.
[0046]
Next, each resist layer R2a and the like is dissolved and removed, and further, soft etching is performed with an etching solution (for example, sulfuric acid / hydrogen peroxide) over a thickness of about 3 μm which is slightly thicker than the thickness (2 μm) of the electroless plating layer 5a and the like.
Then, in the D part, that is, the product formation region 1S, as shown on the right side in FIG. 3C, the portion where the electrolytic plating layer is not formed on the upper part by the resist layers R2a and b, that is, electroless plating. The portions of only the layers 5a and 5b are removed, and the lower first front and back resin layers 4a and 4b are exposed. Thereby, each 1st front and back surface wiring layer 6a, 6b is isolate | separated and independent, respectively. The wiring layers 6a and 6b are also soft etched to reduce the thickness by about 3 μm, so that the thickness becomes about 14 μm.
[0047]
On the other hand, in the E portion, that is, the remaining portion 1TZp around the discarded region 1T, as shown on the left side in FIG. 3C, the electroless plating layers 5A and 5B are removed by soft etching, and the metal layers 3A and 3B are exposed again. To do. Also in this step, the peeled thin piece overlaps the wiring layers 6a, 6b, the electroless plating layer 5a, etc., and the portion becomes thick, and the overlapped portion is incompletely etched, resulting in a short circuit or insulation failure. It does not occur.
Although not shown, in the product adjacent portion 1TP and the intermediate remaining portion 1TZm, the electroless plating layers 5a and 5b are removed by soft etching, and the first front and back resin layers 4a and 4b are exposed. Also, no metal flakes are generated.
[0048]
Thereafter, by repeating the steps described with reference to FIGS. 1 to 3C, as shown in FIG. 4A, the second front and back resin layers 14a and 14b and the second front and back surfaces are formed. Wiring layers 16a and 16b are formed. Also in these steps, Cu electroless plating is applied to form the second front / back surface wiring layers 16a, 16b on the second front / back surface resin layers 14a, 14b, but the remaining 1TZ has front and back surfaces of the core substrate body 1. Metal layers 3A and 3B are formed on 1a and 1b. For this reason, the electroless plating layer (not shown) deposited on the remaining portion 1TZ does not peel off due to good adhesion to the metal layers 3A and 3B, so that no defects due to the flakes are caused as described above.
Although not shown, in the product adjacent portion 1TP and the intermediate remaining portion 1TZm, the first front / back surface resin layers 4a, b and the second front / back surface resin layers 14a, 14b are formed to overlap each other.
[0049]
Thereafter, the resin layer and the wiring layer can be formed in the same manner. However, in this embodiment, three layers of wiring layers 3a, 6a, and 16a are provided on the front surface side and three layers are provided on the back surface side as the center of the core substrate body 1. Wiring layers 3b, 6b, and 16b were formed. Further, as shown in FIG. 4 (b), third front / back surface resin layers (front / back surface solder resist layers) 24a, 24b are formed, and the second front / back surface wiring layers exposed in the openings 24av, 24bv. Connection pads 27a and 27b made of Ni plating were formed on 16a and 16b to complete the build-up multilayer substrate 20.
In the manufacturing process of the build-up multilayer substrate 20 of the present embodiment as described above, the entire surface outside the resin layer formation scheduled areas 1Ua, b among the front and back surfaces 1a, 1b of the core substrate body 1 in the disposal region 1T, that is, Metal layers 3A and 3B were formed on the entire surface of the surrounding remainder 1TZp. As a result, the electroless plating layers 5A and 5B deposited on the surrounding remaining portion 1TZp are not peeled off to form a thin piece, so that a short circuit or a defective pattern due to the thin piece does not occur.
Further, in the product adjacent portion 1TP and the intermediate remaining portion 1TZm, the electroless plating layers 5a and 5b are deposited on the roughened first and rear resin layers 4a and 4b, so that metal flakes are generated. There is nothing.
[0050]
In addition, since the discarded area 1T is not removed, the build-up multilayer board 20 corresponds to the discarded area 1T by cutting in order to make a build-up multilayer board (planar dimension 40 × 40 mm: not shown) as a product. It is necessary to remove the portion so that only the portion corresponding to the product formation region 1SA or the like is obtained. In the present embodiment, it is necessary to further subdivide into parts corresponding to the small product shape area 1SA1 and the like.
At this time, as described with reference to FIG. 1A, the metal layers 3A and 3B are not formed around the product formation region 1SA in the disposal region 1T, and the core substrate main body surface 1a and the back surface are not formed. A square-shaped product adjacent portion 1TP where 1b is exposed is formed. In this way, if the core substrate body 1 is exposed at the boundary between the product formation region 1SA and the like and the disposal region 1T, generation of metal cutting scraps by cutting the metal layers 3A and 3B at the time of cutting is prevented. Thus, it is possible to eliminate problems such as a short circuit due to cutting waste.
[0051]
As a comparative form, a build-up multilayer substrate formed by the same method as described above is prepared using a conventional core substrate in which a metal layer is not formed in the discarded region of the core substrate body, and the build-up multilayer of the above embodiment is prepared. Along with the substrate, each circuit wiring was subjected to open short inspection. Then, in the substrate according to the present embodiment, the short circuit occurrence rate was 15%, whereas in the substrate according to the comparative embodiment, the short circuit occurrence rate reached 70%.
Further, when the cause of the short circuit of the substrate in which these short circuits occurred was investigated, the short circuit due to the copper flakes was not found in the substrate of this embodiment, whereas in the comparative substrate, about 80% of the shorted substrates were It was confirmed that the short circuit caused by the copper flakes was the cause. As can be seen from this, it was confirmed that the substrate according to the present embodiment has a remarkable effect even when only the short-circuit defect is observed, as compared with the substrate according to the comparative embodiment.
[0052]
Next, a method for manufacturing the core substrate 10 according to the present embodiment will be described with reference to FIG. In each drawing of FIG. 5, a partial enlarged view of a portion corresponding to the D portion (product formation region 1S) in FIG. 1 on the right side and a portion corresponding to the E portion (remaining portion 1TZ of the discarding region 1T) on the left side is shown. .
First, as shown in FIG. 5 (a), double-sided copper-clad with 18 μm thick Cu foils Pa and Pb bonded to both the front and back surfaces 1a and 1b of the core substrate body 1 made of a glass fiber-BT resin composite material. Prepare a laminate.
Next, as shown on the right side in FIG. 5B, a through hole 1h penetrating between the front and back surfaces 1a and 1b is drilled in a predetermined portion in the product formation region 1S (D portion). In this step, no through hole is formed in the E portion.
[0053]
Furthermore, after applying catalyst nuclei to the entire surface including the inner surface of the through-hole 1h by activation treatment, an electroless plating layer is formed on the entire surface including the inner peripheral surface of the through-hole 1h by Cu electroless plating. A Cu electroplating layer is deposited on the entire surface. As a result, as shown in FIG. 5C, the panel metal layers Qa and Qb made of Cu having a thickness of 30 μm are formed on the front and back surfaces 1a and 1b of the core substrate body 1, and the inner surface of the through hole 1h is A through-hole metal layer Qh made of Cu having a thickness of 12 μm is formed.
[0054]
Thereafter, the photosensitive film resists Ra and Rb are attached on the panel metal layers Qa and Qb, and further exposed and developed. As shown on the right side in FIG. 5 (d), the product forming region 1S (D portion) is predetermined. Openings Ora and Orb are formed at the positions. In the remaining portion 1TZ (E portion) of the discard region 1T, as shown on the left side in FIG. 5D, resists Ra and Rb are formed on the entire surface of the panel metal layers Qa and Qb, and no opening is formed.
Thereafter, the panel metal layers Qa and Qb exposed in the openings Ora and Orb are dissolved and removed by etching to expose the front and back surfaces 1a and 1b of the core substrate body 1 in the openings. Further, when the resists Ra and Rb are removed, as shown on the right side in FIG. 5E, the panel metal layers Qa and Qb are separated and independently according to each pattern at a predetermined position in the product formation region 1S (D portion). Thus, the wiring layers 3a and 3b are formed, and the through-hole wiring layer 3h is connected between the wiring layers 3a and 3b. On the other hand, in the remaining portion 1TZ (E portion) of the discard region 1T, as shown on the left side in FIG. 5D, metal layers 3A and 3B made of Cu are formed on the entire front and back surfaces 1a and 1b of the core substrate body 1. Structure. In this way, the above-described core substrate 10 (see FIG. 1) was completed.
[0055]
In the above, the present invention has been described with reference to the embodiment. However, the present invention is not limited to the above embodiment, and it is needless to say that the present invention can be appropriately modified within the scope of the invention.
For example, in the core substrate 10 of the above-described embodiment, the core substrate main body front and back surfaces 1a and 1b are exposed in the product adjacent portion 1TP, and the metal layers 3A and 3B are formed on the entire surface of the intermediate remaining portion 1TZm. . However, the present invention is not limited to such a configuration. For example, the core substrate main body surface 1a and the back surface 1b may be exposed in a part of the intermediate remaining portion 1TZm. Further, as shown in FIG. The core substrate main body surface 1a and back surface 1b may be exposed as a whole to form a core substrate 10 ′. This is because the resin layer formation scheduled area 1Ua indicated by the alternate long and short dash line is covered with the insulating resin layers 4a and 4b before the electroless plating process, and thus is not related to the occurrence of flakes regardless of the presence or absence of the metal layer 3A or the like. Accordingly, the pattern of the metal layers 3A and 3B formed in the remaining portion 1T in the resin layer formation planned area 1Ua and b, that is, the region of the product adjacent portion 1TP and the intermediate remaining portion 1TZm, in other words, the exposure of the front and back surfaces 1a and b. It will be readily understood that the pattern may have other shapes. In other words, the exposed surface of the discarded region 1T where the front and back surfaces 1a and 1b are exposed may be covered with the insulating resin layers 4a and 4b in the resin layer forming step.
On the other hand, in the remaining portion 1T, in the resin layer non-formation planned areas 1Na, b, that is, the surrounding remaining portion 1TZp in the above embodiment, the metal layers 3A, B are formed over the entire front and back surfaces 1a, b. preferable. However, a part of the peripheral remaining portion 1TZm may be exposed due to positioning of the core substrate, formation of a product number indication mark, and other reasons.
[0056]
In addition, in the case of the core substrate 10 ″ in which the boundary between the resin layer formation planned area 1Ua and the resin layer non-formation planned area 1Na indicated by the alternate long and short dash line is positioned near the outside of each product adjacent portion 1TP as shown in FIG. Similarly, it is clear that no metal flakes are generated.
In the above embodiment, the first front and back resin layers 4a and 4b and the in-hole resin layer 4h are made of the same material, but the in-hole resin layer 4h is made of a material different from that of the first front and back resin layers 4a and 4b. For example, a thermosetting resin having no photosensitivity, a resin mixed with metal particles, a plating catalyst, or the like may be used.
Further, although not mentioned in the above embodiment, it is more preferable to form a metal layer on the outer surface of the core substrate body. This is because a slight electroless plating layer is deposited on the outer surface. Alternatively, a plating resist layer may be formed on the outer surface instead of the metal layer to prevent deposition of the electroless plating layer.
Moreover, in the manufacturing method of the buildup multilayer substrate in the above-described embodiment, the first front and back wiring layers and the like are formed by a so-called semi-additive method, but part or all of the wiring layers are formed by using an electroless plating method. If it is formed, it may be formed by another method. Specifically, for example, the first front / back wiring layer and the like may be formed by a full additive method or a subtractive method.
[Brief description of the drawings]
FIG. 1 shows a core substrate for a buildup multilayer substrate according to an embodiment of the present invention, wherein (a) is a plan view, and (b) is a D part (product formation region) of a YY ′ cross section thereof. (C) is a partial expanded sectional view of E section (discarded area).
2A is a plan view showing a state in which a resin layer is formed on the front and back surfaces of the core substrate shown in FIG. 1, and FIGS. 2B and 2C are views in which an electroless plating layer is further formed thereon. FIG. 2B is a partially enlarged cross-sectional view in the state of FIG. 1B, in which FIG. 1B corresponds to a portion D shown in FIG. 1B and FIG. 1C corresponds to a portion E shown in FIG.
FIG. 3 is a partially enlarged cross-sectional view for explaining a process until a first front / back wiring layer is formed in a process of further forming a buildup multilayer substrate based on the core substrate according to the embodiment; The right side of the drawing corresponds to the D portion shown in FIG. 1B, and the left side shows the portion corresponding to the E portion shown in FIG.
FIG. 4 is a partial enlarged cross-sectional view for explaining a process up to completion among processes for further forming a build-up multilayer substrate based on the core substrate according to the embodiment, and the right side of each figure is FIG. The left side shows a portion corresponding to the E portion shown in FIG. 1 (c).
FIG. 5 is a partial enlarged cross-sectional view for explaining a manufacturing process of the core substrate according to the embodiment, in which the right side of each figure corresponds to the D portion shown in FIG. 1B, and the left side is shown in FIG. The part corresponding to E part is shown.
FIG. 6 is a plan view of a core substrate according to another embodiment.
FIG. 7 is a plan view of a core substrate according to still another embodiment.
FIG. 8 is a partially enlarged cross-sectional view for explaining the steps up to the step of forming a resist layer having a predetermined pattern on the electroless plating layer in the build-up multilayer substrate manufacturing method.
FIG. 9 is a partially enlarged cross-sectional view for explaining steps after electrolytic plating in the buildup multilayer substrate manufacturing method.
10A shows a conventional core substrate, FIG. 10A is a plan view, and FIG. 10B is a partially enlarged cross-sectional view of a B portion (product formation region), and FIG. It is a partial expanded sectional view of the C section (discarded area).
11 shows a state where electroless plating is applied to the core substrate shown in FIG. 10, (a) is a partially enlarged cross-sectional view corresponding to part B shown in FIG. 10 (b), and (b) shows FIG. It is a partial expanded sectional view corresponding to the C section shown in (c).
[Explanation of symbols]
1 Core board body
1a Surface
1b Back side
1SA, 1SB, 1SC, 1SD Product formation area
1SA1,1SA2,1SA3,1SA4 Small product formation area
1T discard area
1TP product adjacent part
1TZ remaining
1TZm intermediate balance
1TZp Surrounding remainder
1Ua Resin layer formation planned area
1Na resin layer non-formation planned area
3 Wiring layer
3a Front side wiring layer
3b Back side wiring layer
3h Through-hole wiring layer
4 Resin layer
4a First surface resin layer
4b First back surface resin layer
4h Resin layer in the hole
5a, 5b, 5A, 5B Electroless plating layer
6a First surface wiring layer
6b First backside wiring layer
10, 10 ', 10 ", 100 core substrate
20,200 Build-up multilayer board

Claims (5)

Core plate body having a substantially plate shape having a front surface and a back surface, having a product formation region and a disposal region,
A metal layer that adheres well to each of the front and back surfaces in the discarded area;
Have
The metal layer is formed on substantially the entire surface of the area where the resin layer is not to be formed, of the front and back surfaces of the core substrate body in the discard area.
A method of manufacturing a build-up multilayer substrate using a core substrate for build-up multi-layer substrate,
A resin layer forming step of forming an insulating resin layer of a predetermined pattern in the resin layer formation planned area;
An electroless plating step of forming an electroless plating layer on the insulating resin layer;
including
A method for producing a build-up multilayer substrate, characterized in that: Core plate body having a substantially plate shape having a front surface and a back surface, having a product formation region and a disposal region,
A metal layer that adheres well to each of the front and back surfaces in the discarded area;
Have
The metal layer is formed on substantially the entire surface of the area where the resin layer is not to be formed, of the front and back surfaces of the core substrate body in the discard area.
A core substrate for a build-up multilayer substrate ,
A product adjacent portion in which at least one of the front surface and the back surface of the core substrate body is exposed at a portion adjacent to the product forming region in the discarding region.
A method of manufacturing a build-up multilayer substrate using a core substrate for build-up multi-layer substrate,
A resin layer forming step of forming an insulating resin layer of a predetermined pattern in the resin layer formation planned area;
An electroless plating step of forming an electroless plating layer on the insulating resin layer;
including
A method for producing a build-up multilayer substrate, characterized in that: A method of manufacturing a build-up multilayer board,
A core substrate having a substantially plate shape having a front surface and a back surface, a core substrate body having a product formation region and a discard region, and a metal layer that is well adhered to the front and back surfaces in the discard region, respectively. Use
A resin layer forming step of forming an insulating resin layer having a predetermined pattern on at least one of the front and back surfaces of the core substrate body including the product formation region;
An electroless plating step of forming an electroless plating layer on the insulating resin layer, and in the resin layer formation step, an exposed surface in which the front surface and the back surface of the core substrate body are exposed in the discarded region, A method for producing a build-up multilayer substrate, characterized by covering the substantially entire surface with the insulating resin layer. It is a manufacturing method of the buildup multilayer substrate according to claim 3 ,
The core substrate includes a product adjacent portion in which at least one of a front surface and a back surface of the core substrate body is exposed in a portion adjacent to the product formation region in the discard region. A method for manufacturing a substrate. It is a manufacturing method of the buildup multilayer substrate according to claim 3 or 4 ,
A method for manufacturing a buildup multilayer substrate, wherein a material of the electroless plating layer is composed of substantially the same metal component as the metal layer.

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