JP3757252B2 - Digital signal processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal processing device such as a digital signal processor (DSP) or a microprocessor, and in particular, increases and decreases the supply voltage and the number of instruction cycles in accordance with the operating rate to save power and to improve operational stability and processing. The present invention relates to a digital signal processing apparatus for improving efficiency.
[0002]
[Prior art]
In order to save energy in a digital signal processing device (hereinafter referred to as a processor), it is effective to reduce the operating voltage. However, in general, when the operating voltage is reduced, the operation speed of the constituent circuits is reduced, and instructions for executing the processing of the processor ( There is a disadvantage that a part of the (instruction) does not end within a predetermined number of machine cycles (instruction cycles). On the contrary, when the operating voltage is increased, the constituent circuits are increased in speed and efficiency, but there is a problem that power consumption increases and energy saving is significantly impaired.
[0003]
As a countermeasure, it was considered to change the clock frequency for driving the synchronous circuit frequently used in the processor by following the operating voltage. However, this method allows the input / output data to be exchanged with the peripheral IC. There is a problem that the operation speed is inconsistent and the stable operation of the entire system becomes difficult.
[0004]
Therefore, conventionally, as shown in FIG. 3, a supply voltage to the internal circuit 22 of the processor core unit 21 is supplied from the external power supply terminal 23 via the voltage converter 24, and the voltage converter 24 is connected to the internal circuit 22. In accordance with the result monitored by the operation speed monitor (operation monitor) unit 25 for monitoring the operation speed of the system, control is performed so that operation instability due to speed deterioration does not occur. Reference numeral 26 denotes an I / O circuit for exchanging data with the outside.
[0005]
[Problems to be solved by the invention]
However, in the conventional method, the operating voltage cannot be sufficiently reduced from the viewpoint of avoiding unstable operation, and the energy saving effect is insufficient. When the operating voltage is increased, the effect of speeding up the constituent circuits can be expected, but the processing efficiency is not sufficiently improved for the increase in power consumption.
[0006]
The present invention has been made in view of the above points. The purpose of the present invention is to monitor the operating rate and set the optimum operating voltage and the number of instruction cycles according to the monitoring result. It is an object of the present invention to provide a digital signal processing apparatus that improves processing efficiency.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention for achieving the above object, there is provided a data converter including a voltage converter for inputting an external power supply voltage and outputting an internal operating voltage, a clock driver for supplying a clock therein, and an instruction controller. In the digital signal processing apparatus comprising the above, the operating current supplied to the clock driver unit and the operating current supplied to the data path unit are detected, increase / decrease in the ratio of both currents, increase / decrease in individual absolute amounts of both currents, Alternatively, the operating rate of the data path unit is determined based on the increase / decrease of the total amount of both currents, and the output voltage of the voltage conversion unit is controlled to increase / decrease according to the determination result, and the command control unit A current monitoring unit that increases or decreases part or all of the number of execution cycles is provided.
According to a second invention, in the first invention, a parity check signal is held in the signal of the data path unit, and the result of the parity check is controlled to increase / decrease the output voltage of the voltage converter and / or increase / decrease the number of execution cycles. It was configured to be reflected in
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 1 denotes a processor core unit, which has an internal circuit 2 and an I / O circuit 3 as main components. The internal circuit 2 includes a clock driver unit 4 that supplies a clock to the whole and a data path unit 5 that executes data arithmetic processing and the like. The data path unit 5 includes an instruction controller 6. Reference numeral 7 denotes a voltage converter that boosts or lowers the voltage (VDD) supplied to the external power supply terminal 8 and supplies the voltage to the internal circuit 2. Reference numeral 9 denotes an operating current supplied from the voltage converter 7 to the clock driver unit 4. An ammeter 10 for measuring the operating current supplied from the voltage converter 7 to the data path unit 5, and 11 for the voltage converter 7 based on the current values measured by both ammeters 9 and 10. This is a current monitoring unit that sends a control signal to the command control unit 6 of the data path unit 5. The voltage VDD supplied to the I / O circuit 3 is directly supplied from the external power supply terminal 8 so that the I / O circuit 3 can operate in a manner compatible with the signal voltage of the external circuit. ing.
[0009]
Now, assuming that the supply current to the clock driver unit 4 monitored by the current monitor unit 11 is Ic and the supply current to the data path unit 5 is Id, the operation rate γ of the data path unit 5 is expressed by the following equation.
γ = Id / (Id + Ic) (1)
= 1-Ic / It
= 1-Pc / Pt
However, It = Id + Ic. Pc is the power consumption of the clock driver unit 4, and Pt is the overall power consumption of the internal circuit 2.
Pc = Ic · (VDD ± ΔV)
Pt = Ic · (VDD ± ΔV) + Id · (VDD ± ΔV)
It is. (VDD ± ΔV) is a voltage commonly supplied from the voltage conversion unit 7 to the clock driver unit 4 and the data path unit.
[0010]
When the operating rate γ is sufficiently small and close to 0, it indicates that most of the current consumption is consumed by the clock driver unit 4 and the effective operating rate of the data path unit 5 is small. In this case, the current monitor unit 11 instructs the voltage conversion unit 7 to set the voltage (VDD ± ΔV) supplied to the internal circuit 2 low. At the same time, it instructs the instruction control unit 6 in the data path unit 5 to increase the number of instruction cycles (the number of clocks of one instruction cycle) of a part or all of the instruction set executed by the processor by about 1 or 2. That is, normally, one instruction cycle is executed with, for example, 2 clocks or 3 clocks, but the number of clocks is increased.
[0011]
FIG. 2 shows how the number of instruction cycles is increased or decreased. Reference numeral 12 denotes the number of cycles during low-voltage operation, 13 denotes the number of cycles during high-voltage operation, and 14 denotes an increase in cycle time due to a reduction in operating voltage. A, B, and C are instruction types.
[0012]
As described above, when the operation rate is small, the power supply is reduced by reducing the internal supply voltage, and the instruction processing can be afforded by increasing the number of instruction cycles, so that stable instruction processing is performed. It becomes like this. That is, energy saving and stable operation are achieved.
[0013]
On the other hand, when the operation rate γ is sufficiently larger than 0, the ratio of the power consumed by the internal circuit 2 to the data path unit 5 increases, and the effective operation rate of the data path unit 5 is large. It shows that. In this case, the current monitoring unit 11 instructs the voltage conversion unit 7 to set the voltage (VDD ± ΔV) supplied to the internal circuit 2 high. At the same time, it instructs the instruction control unit 6 in the data path unit 5 to reduce the number of instruction cycles of some or all of the instructions executed by the processor by about 1 or 2.
[0014]
When the operating rate is high, high-speed operation can be realized by increasing the internal supply voltage, and the number of instruction cycles is set small so that this high-speed operation can be utilized, so that high processing efficiency is achieved. The
[0015]
The timing for setting the increase / decrease in the number of instruction cycles described above may be set by dynamic setting for executing resetting between instructions or by static setting for executing resetting only when there is no possibility that the instruction will be executed. It may be set.
[0016]
In the calculation of the operating rate, the ratio (= Ic) other than the ratio {= Id / (Id + Ic)} of the current Ic to the clock driver unit 4 and the current Id to the data path unit 4 shown in Expression (1). / Id), the operating rate γ at this time is inversely proportional to (Ic / Id). It can also be performed based on the absolute values of Ic and Id, and the operating rate γ at this time is proportional to Id. Further, it can be performed based on the total amount of currents Ic and Id (= Ic + Id), and the operating rate γ at this time is proportional to (Ic + Id).
[0017]
Further, in the above description, if a parity check part is added to the main signal of the data path unit 5, the parity check is always executed, and, for example, a parity error is determined based on the check result, thereby causing unstable operation of the processor. Therefore, the detection result can be reflected in the optimization of the power supply voltage supplied to the internal circuit 2 and the number of instruction cycles.
[0018]
For example, if a parity error is determined in the parity check as a result of setting the supply voltage based on the result of the operation rate γ, the supply voltage is too low, so that the supply voltage is increased. Recalculate with correction. Moreover, if the parity error is determined by the parity check as a result of operating with the instruction cycle number decreased based on the result of the operation rate γ, the instruction cycle number is too small, so the instruction cycle number is increased. Make corrections and recalculate.
[0019]
【The invention's effect】
As described above, according to the present invention, since it can be realized by adding a voltage conversion unit, a current monitoring unit, and the like and determining the operation rate, the configuration of the existing digital signal processing apparatus is not changed, that is, the gate It is possible to set an optimum operating voltage and the number of instruction cycles while suppressing an increase in the number and chip area, and it is possible to improve the energy saving effect and the processing efficiency.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a digital signal processing apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the number of instruction cycles.
FIG. 3 is an explanatory diagram showing a configuration of a conventional digital signal processing apparatus.
[Explanation of symbols]
1: processor core unit, 2: internal circuit, 3: I / O circuit, 4: clock driver unit, 5: data path unit, 6: instruction control unit, 7: voltage conversion unit, 8: external power supply terminal, 9, 10 : Ammeter, 11: Current monitor unit.

Claims (2)

In a digital signal processing apparatus comprising a voltage conversion unit that inputs an external power supply voltage and outputs an internal operating voltage, a clock driver unit that supplies a clock therein, and a data path unit that includes a command control unit,
The operating current supplied to the clock driver unit and the operating current supplied to the data path unit are detected, based on increase / decrease in the ratio of both currents, increase / decrease in individual absolute amount of both currents, or increase / decrease in total amount of both currents. The operation rate of the data path unit is determined, and the output voltage of the voltage conversion unit is controlled to increase or decrease according to the determination result, and the number of execution cycles of a part or all of the instruction set is increased or decreased with respect to the instruction control unit. A digital signal processing apparatus comprising a current monitoring unit to be controlled. The parity check signal is held in the signal of the data path unit, and the result of the parity check is reflected in the increase / decrease control of the output voltage of the voltage converter and / or the increase / decrease control of the number of execution cycles. A digital signal processing apparatus according to 1.

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