JP3757973B2 - Signal transmission device - Google Patents

Description

  The present invention relates to a signal transmission technique between components (integrated circuits are typical ones) mounted in an apparatus such as a workstation or a personal computer, and particularly to a technique effective for high-speed signal transmission.

  An example of a memory circuit used in a current workstation or personal computer is shown in FIG.

  Reference numeral 30 denotes a memory module on which a plurality of memory LSIs 31 are mounted. Reference numeral 32 denotes a memory controller that controls the memory LSI 31, transmits write data to the memory LSI 31, receives read data from the memory LSI 31, and the like.

  In some memory controllers 32, a part for controlling the memory LSI 31 and a part for transmitting write data and receiving read data are performed in separate integrated circuits.

  The memory LSI here is assumed to be a clock synchronous memory. An example of a clock synchronous memory is SDRAM (Synchronous Dynamic Random Access Memory).

  The memory controller is mounted on the mother board 33, and the memory module 30 is mounted on the mother board by the connector 34.

  In FIG. 3, the number of memory modules mounted on the motherboard is eight, but the number of modules is determined at any time according to the scale of the system, the specifications, the purpose of the user, and the like.

  The simple circuit operation of this memory circuit is as follows. Control signals and data signals for writing output from the memory controller pass through the signal wiring 35 on the mother board, the connector 34, the contact 36 on the memory module, and the wiring 37 on the memory module to the memory LSI 31 on each module. It is told. Further, in the case of reading data, the data is input from the memory LSI 31 to the memory controller 32 through the module wiring 37, the contact 36, the connector 34, and the wiring 35 on the motherboard.

  Such wiring 35 is called a memory bus. FIG. 3 shows only one of a plurality of memory buses.

  Note that, in addition to the control signal and data signal, a clock signal is also supplied to the SDRAM, but the clock wiring is not shown in FIG. The clock wiring is distributed to the memory LSI in the memory controller or memory module directly from the clock source or from a frequency dividing / distributing destination.

  There is a single-phase clock system method using a flip-flop in a signal transmission line between integrated circuit components in such a memory system.

  This technology is described in detail, for example, on pages 356 to 360 of VLSI system design circuit and basics of mounting (Maruzen Publishing, 1995).

  The simplest example of the single phase clock system is shown in FIG. FIG. 2 shows a transmission circuit in which an output circuit and an input circuit are connected at a ratio of 1: 1. Here, the circuit block 21 includes a flip-flop 24 and an output circuit 26, and the circuit block 22 includes an input circuit 27 and a flip-flop 25. Reference numeral 23 denotes a transmission line for transmitting a signal output from the circuit block 21 to the circuit block 22.

  The flip-flops 24 and 25 are supplied with clocks directly from the clock source or distributed and divided. Although not shown in FIG. 2, the input signal of the flip-flop 24 is generally generated in the circuit block 21, and the output of the flip-flop 25 is generally input to another circuit in the circuit block 25. Is.

  In the above description, the input signal of the flip-flop 24 is generated in the circuit block 21, but it may be generated in another circuit block and directly input to the flip-flop. Similarly, the output of the flip-flop 25 is not limited to the input circuit in the circuit block 22 and may be directly wired to the input circuit in another circuit block.

  The basic operation of the circuit shown in FIG. 2 is as follows.

  It is assumed that a clock is supplied to the flip-flops 24 and 25. The flip-flop 24 outputs the data latched by the clock of the previous cycle in synchronization with the clock, transmits the data to the input unit of the output circuit 26, and outputs the data from the output unit to the transmission line 23. The data transmitted through the transmission line 23 is transmitted to the data input section of the flip-flop 25 through the input circuit 27, and is latched in synchronization with the clock.

  In the case of a single-phase clock system, the clocks input to the flip-flops are designed so that the phases are in phase with each other. The technology to match the phase is to adjust the wiring length by matching the signal wiring length from the clock source or its distribution destination and frequency dividing destination to the clock input section of each circuit block, or by matching the capacitive load of the clock signal wiring. The method of matching is widely used.

In this single-phase clock system, a technique widely used as a method for efficiently transmitting a signal is a transmission system in which the signal is latched on the receiving side in the cycle following the cycle in which the signal is output. In this scheme, the cycle time tcycle must satisfy the following formula:
t cycle> t delay (max) + t pd (max) + t setup (max) + t skew (max)
here,
t delay (max) is the clock access time of the circuit block 21, that is, the time from when the clock is input to the circuit block 21 until the data is output from the circuit block 21,
t pd (max) is the propagation time until the signal output from the circuit block 21 is input to the circuit block 22;
t setup (max) is the setup time of the circuit block 22, that is, the time during which the logical value (High or Low) of the signal input to the circuit block 22 must be determined prior to the clock input to the circuit block 22. ,
Finally, t skew is a skew between clocks input to the circuit blocks 21 and 22, respectively.

  (Max) in the equation means the maximum value taking into account variations in each temperature and process.

  In the memory circuit shown here, when the connection wiring between the circuit blocks (here, the memory controller and the memory module) is long, the propagation time and tpd described above have a large value. For example, when the connector pitch is 400 mil (about 1 cm) and the number of memory modules is 16, tpd is 3 to 4 ns.

When tpd (mux) is 4 ns, when the number of cycles is 33 MHz, the ratio of the tpd to the period, 30 ns is only about 10%.
t cycle> t delay (max) + t pd (max) + t setup (max) + t skew (max)
It is possible to satisfy.

However, for example, if the number of cycles is increased to 250 MHz, the period is 4 ns, which is the same as tpd (max), and this system cannot be realized no matter how fast the circuit block is made. Even if it doesn't go up to 250MHz, t delay (max), t setup (max), t skew (max) speedup is largely due to miniaturization of the device. In reality, even with the number of cycles around 100MHz,
t cycle <t delay (max) + t pd (max) + t setup (max) + t skew (max)
Therefore, further increase in speed is impossible in design.

  In addition, when considering the realization of high speed, there is a method of examining window securing in addition to the delay calculation as described above. In the case of delay calculation, whether or not signal transmission is possible when the clock phases of the output circuit and input circuit are the same is considered, but if the window is taken into account, an offset adjustment is made to the clock phase. This makes it possible to further increase the speed.

  For example, in the case shown in FIG. 3, the clock phase supplied to the memory module is shifted or advanced or delayed in comparison with the clock supplied to the memory controller. Say.

For example, when the delay time at the time of writing is faster than the delay time at the time of reading, the above-described method using the delay time determines the cycle according to the delay time at the time of reading, while considering the window. In this case, it is possible to output read data earlier by shifting the phase of the clock supplied to the memory LSI early. As a result, in the memory controller, the clock synchronization timing of the memory LSI and the clock synchronization of the next cycle of the memory controller Since the time until the timing can be extended, there may be a case where a time longer than the delay time at the time of reading can be secured. In other words, when considering securing window time, instead of the above formula, window time t window, that is,
t window = t cycle + t OH-t delay (max)
Design using.

  t OH is the data output hold time, and is the time from when the next clock enters the output circuit block that is outputting the signal to when the output switches to data (in that cycle). This time is equal to or longer than t delay (min), that is, the minimum value of t delay.

The following equation should be satisfied based on the value of t window obtained in this way.
t window> tpd (max-min) + t setup (max) + t hold (max)
Here, tpd (max-min) is the difference between the maximum value and the minimum value of tpd. In the case of FIG. 3, the maximum value is the propagation between the module at the farthest end and the memory controller. The minimum value is the propagation time between the nearest module and the memory controller. That is, t delay (max-min) is an amount representing a difference in propagation time depending on the position of the memory module.

This window time is examined for each time data is written to and read from the memory module.
t window> tpd (max-min) + t setup (max) + t hold (max)
If satisfied, the clock phase offset value may be set so that the setup time and hold time can be secured in the respective time widths t window -tpd (max-min).

  Although this method can increase the speed slightly, if the number of mounted modules increases in the device size, for example, the memory circuit shown in FIG. 3, the value of tpd (max-min) cannot be ignored. Is still difficult.

  That is, as the high-speed transmission is required, the influence of the difference between the signal propagation time from the memory controller to the near-end memory module and the signal propagation time from the memory controller to the far-end memory module increases. Difficulties arise in high-speed system design.

  The same problem occurs between circuits that transmit and receive signals in synchronization with the clock regardless of the memory system. For example, the same problem also applies to the processor bus in a multiprocessor system using a plurality of microprocessors. Can occur.

  An object of the present invention is to solve these problems in a system that exchanges signals in synchronization with a clock signal.

  It is an object of the present invention to provide a signal transmission device that can reduce signal transmission / reception failure due to a delay in signal propagation time between circuits.

  Other objects of the present invention will become apparent in the following detailed description.

  In order to achieve the above object, a clock output circuit that outputs a clock signal, a first circuit that outputs a first signal, a plurality of second circuits that receive the first signal, A substrate on which the second circuit is arranged and mounted, a first wiring for transmitting the clock signal, and a second wiring for transmitting a signal from the first circuit to the second circuit In the signal transmission device, the first wiring is wired from the clock output circuit and connected in series with the plurality of second circuits, and the second wiring is wired from the first circuit, The first and second wirings and the second circuit are connected so as to be connected in series to the memory module.

  By doing so, the relative relationship between the distance that the clock signal reaches the arbitrary second circuit and the distance that the first signal output from the first circuit reaches the second circuit is: Regardless of the mounting position of the second circuit, the distance can be substantially the same, and when the second circuit latches the first signal in synchronization with the clock signal, the circuit between the circuits of the first signal The influence of the propagation delay time can be suppressed.

  Further, each of the first and second wirings is folded back at a position farthest from the second circuit farthest from the first circuit and returns to the second circuit closest to the first circuit. A part of the second circuit is connected to the first wiring and the second wiring at a folded position, and the remaining second circuit is connected to the first wiring and the second wiring. By connecting after the turn-back position, the load density can be reduced.

  Furthermore, a clock output circuit that outputs a clock signal, a first circuit that outputs a first signal and receives a second signal, and receives the first signal and outputs the second signal A plurality of second circuits, a substrate on which the plurality of second circuits are arranged and mounted, a first wiring for transmitting the clock signal, and a signal from the first circuit to the second circuit And a third wiring for transmitting a signal from the second circuit to the first circuit, wherein the first wiring is the clock output circuit. And the second and third wirings are wired from the first circuit and connected in series to the plurality of memory modules, and the second wiring is connected to the plurality of memory modules in series. The wiring is farther from the second circuit farthest from the first circuit. The second circuit is laid out so as to return from the first circuit to the nearest second circuit, and each of the first and third wirings is the second circuit farthest from the first circuit. It is laid back so as to reach the first circuit after returning from the first circuit to the nearest second circuit, and in the first wiring and the second wiring, A part of the second circuit is connected to the first wiring and the second wiring until the folded position, and the remaining second circuit is connected after the folded position of the first and second wirings. In the third wiring, the part of the second circuit connected to the first wiring up to the folding position of the first wiring is connected after the folding position of the third wiring. For the remaining second circuit, the third wiring is folded. Connect up to the return position.

  By doing this, the relative relationship between the distance that the clock signal reaches the arbitrary second circuit and the distance that the first signal output from the first circuit reaches the second circuit, and The distance until the second signal output from the second circuit in synchronization with the clock signal reaches the first circuit, and the clock signal when the second circuit outputs the second signal are The relative relationship with the distance to reach the circuit can be substantially the same distance regardless of the mounting position of the second circuit, and the second circuit sends the first signal in synchronization with the clock signal. When latching and when the first circuit latches the second signal, the influence of the propagation delay time between the circuits of the first and second signals can be suppressed.

  In addition, the first output circuit that outputs the first signal, the second output circuit that outputs the second signal, the first reception circuit that receives the third signal, and the fourth signal are received. A first circuit block having a second receiving circuit, a third receiving circuit for receiving the first signal, a fourth receiving circuit for receiving the second signal, and a third signal. A plurality of second circuit blocks each having a third output circuit for outputting and a fourth output circuit for outputting the fourth signal; and the first signal, the second signal, and the third signal. A first wiring, a second wiring, a third wiring, and a fourth wiring that transmit the fourth signal between the first circuit block and the second circuit block are respectively connected to the first wiring. Fold at the position of the second circuit block farthest from the circuit block or at a position further away from the above position. A part of the second circuit block is connected on the wiring from the first circuit block to the folding position with respect to the first signal and the third signal, and the remaining first signal and third signal are connected. 2 circuit blocks are connected on the wiring ahead of the folded point, and for the second signal and the fourth signal, the first signal passes from the first circuit block to the folded position. The second circuit block is connected on the wiring before the folded point, and the other second circuit block is connected to the folded position from the first circuit block. The second receiving circuit latches the fourth signal in synchronization with the third signal, and the fourth receiving circuit outputs the fourth signal in synchronization with the first signal. It is configured to latch, and the memory module side is We may output a timing signal for receiving data at the memory controller side when outputting data.

  According to the present invention, a design capable of high-speed signal transfer can be performed even in a system such as a memory system in which a signal propagation time is large and there is a difference in delay time depending on a module position.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  In the present embodiment, an example of a memory bus of a memory system will be described. As described above, the present invention is applicable to signal wiring such as a system bus (processor bus), a memory bus, and a peripheral bus shown in FIG. Is also applicable. Needless to say, it is not limited to memory systems.

An embodiment (first embodiment) of the present invention will be described.
As a drawing related to the present embodiment, the wiring and connection between the memory controller and the memory module are shown in FIGS. 4, 6, and 1. Details of the memory controller are shown in FIGS. 28 to 31 and FIG. Details are shown in FIG. 21, FIG. 40 and FIG. Moreover, it shows in FIGS. 13-16, FIGS. 18-20, and FIGS. 22-25 about the modified example of the mounted system.

First, the basic board wiring pattern and the connection between the board wiring and the connector according to the present embodiment will be mainly described with reference to FIG.

  The memory controller 32 includes output circuits 11 and 12 and input circuits 13 and 14.

  Among them, the output circuit 11 and the input circuit 13 are clock signal circuits, the output circuit 12 and the input circuit 14 are data signal circuits, the wiring 15 is a clock wiring for transmitting a clock, and the wiring 16 is for data writing. The wiring line 17 is a data readout wiring line.

  Reference numerals 34A to 34F denote connectors to which a memory module (to be described later) mounted with a memory element or the like is connected.

  The memory controller 32, the wirings 15, 16, and 17 and the connectors 34A to 34F are mounted on a board (motherboard) as indicated by 33 in FIG.

  The transmission lines 15A, 15B, 16A, and 17A are wires that are drawn to the module when the memory controller 32 is mounted on a substrate (module) different from the motherboard. Further, even when the memory controller 32 is mounted on the motherboard, it may be pulled as necessary depending on the layout on the motherboard, but this is not always necessary.

  The connectors 34A to 34F are mounted in a line on the motherboard as shown in FIG. The wirings 15 to 17 extend from the memory controller 32 so as to sequentially cross the respective connectors 34A to 34F, are folded (U-turned) at the tip of the connector farthest from the memory controller 32, and again from the connector 34F to the connector 34A. They are laid out so as to cross each other. In FIG. 4, black circles (·) are shown for the connection points between the wires 15 to 17 and the connectors 34 </ b> A to 34 </ b> F.

  The clock wiring 15 and the data writing wiring 16 are connected to the connectors 34A-34C... 34E by the turn-back positions of the respective wirings, and are connected to the connectors 34F... 34D-34B after the turn-back positions.

  The data read wiring 17 is connected in a reverse relationship to the clock wiring 15 and the data write wiring 16. That is, the connection is made with the connectors 34B-34D... 34F up to the position where the wiring 17 is turned back, and the connection with the connectors 34E.

  By alternately arranging, the load applied to the wiring becomes uniform.

  In FIG. 4, one clock signal line 16, one data signal line for writing 17 and one data signal line for reading 18 are shown. However, the number of wirings can be drawn as many as necessary. Needless to say, it is good.

  The memory module 30 is mounted on the connectors 34A to 34F. Examples of the memory module are shown in FIGS. A plurality of memory LSIs are mounted on the memory module 30 as shown in FIG. The memory LSI is preferably a clock synchronous memory such as an SDRAM. The SDRAM is a memory that takes in a control signal and an address signal, or writes and reads data in synchronization with a clock.

  In the memory module 30, as shown in FIG. 19, in the memory module 30, the module contact 36 and the SDRAM pin are connected 1: 1. As shown in FIG. 20, the control signal and the address signal are connected to the module contact 36 and a plurality of SDRAM pins. FIG. 20 shows an example in which signals are distributed to all SDRAMs, but a case where signals are distributed from one contact 36 to a part of the SDRAM on the module, for example, a plurality of CAS (Column Address Strobe) in one module. This is the case when a signal is input.

  As shown in FIG. 22, when a buffer circuit 61 is inserted between the contact 36 and the SDRAM, or when a resistor is inserted in the data signal line as shown in FIG. 23, the control signal / address signal line as shown in FIG. In some cases, both the buffer circuit 61 and the resistor 60 are inserted as shown in FIG.

  The resistor inserted in FIG. 23 and the like is a resistor for impedance matching between the wiring on the mother board and the wiring on the memory module, and details thereof are described in Japanese Patent Application No. 5-334631 previously filed by the present applicant. (Japanese Patent Application Laid-Open No. 7-202947) and Japanese Patent Application No. 7-26495 (Japanese Patent Application Laid-Open No. 7-283836).

  FIG. 21 shows a circuit in which one SDRAM among the memory modules 30 is focused and all other circuits are omitted. The SDRAM in FIG. 21 shows a type in which the input circuit and the output circuit are separated. The SDRAM includes an input circuit 50 that captures a clock, an input circuit 51 that captures data, and an output circuit 52 that outputs data.

  The current SDRAM is an input / output type in which the input unit of the input circuit and the output unit of the output circuit are shared in the LSI. This will be described later. The operation will be briefly described below by taking as an example a pin specification in which the output part of the circuit is separated.

  The SDRAM 31 captures data by the input circuit 51 in synchronization with the clock captured by the input circuit 50 or outputs data from the output circuit 52 and writes or reads data in synchronization with the clock signal. ing.

  Usually, in the memory system of the present embodiment, the above-described memory module 30 is realized by being connected to all or part of the connector 34.

  Hereinafter, a processing example of writing data to the memory module 30 in the memory system in which the memory module 30 shown in FIG. 21 is connected to each connector of the motherboard shown in FIG. 4 will be described.

  The memory controller 32 outputs write data and a clock signal from the output circuits 12 and 11, respectively. The clock signal may be transmitted when the writing process is performed, or may be always output.

  The output clock signal is transmitted through the clock wiring 15 and is transmitted to each connector in the order of the connectors 34A, 34C,..., 34E, 34F,. Since the write data is also connected to the connectors in the same order as the clock wiring, it is transmitted to each connector in the same order.

  The SDRAM 31 of the memory module 30 connected to the arbitrary connector 34 takes in data from the previous input circuit 51 in synchronization with the clock signal received by the input circuit 50.

  When the memory controller reads data, the memory controller 32 issues a control signal including a clock signal and an address for reading data. Similar to the above writing, the control signal output from the memory controller 32 is received by the SDRAM 31.

  The SDRAM 31 outputs the corresponding data from the output circuit 52 to the data reading wiring 17 in synchronization with the clock signal received by the input circuit 50.

  The data read wiring 17 is connected to the connector in the reverse order to the data write data. Assuming that the memory module is connected to the connector 34, the data output from the output circuit 52 by the SDRAM 31 is connected to the connectors 34A, 34C, ..., 34E, 34F, ..., 34D, 34B. To get to the memory controller. A clock signal when the SDRAM 31 outputs data is used to synchronize data output with the connector 34A. The clock signal returns to the memory controller from the connector 34A through the connection points with the connectors 34C,..., 34E, 34F,.

  The memory controller 32 takes in the data read by the receiving circuit 14 in synchronization with the clock signal returned via the clock wiring received by the receiving circuit 13.

  Until the read data arrives at the memory controller 32 from the memory module 30 and until the clock signal arrives at the memory controller 32 from the position of the memory module 30, the clock signal and the data signal between the circuits are shifted. It becomes unnecessary to be aware of the difference in delay between circuits.

  In this manner, the time (distance) for the clock signal and the write data signal to reach any memory module can be substantially matched regardless of the connection position of the memory module. In addition, the time until the read data arrives from the memory module and the time from the position of the memory module until the clock signal returns to the memory controller can be substantially matched.

In this way, regardless of the position of the memory module, the sum of the propagation time at the time of data writing and the propagation time at the time of reading becomes a substantially constant value,
t window> tpd (max-min) + t setup (max) + t hold (max)
In this case, the value of tpd (max-min) can be reduced, and a window margin can be secured.

In other words, as I said before, time
t window-tpd (max-min)
Therefore, a time longer than the setup time and hold time values can be easily taken.

  In addition, as shown in FIG. 4, the connection method of the connector which makes the connection of a connector and wiring alternately before and after the return position of wiring is an example.

In the clock wiring 15, the portion from the output circuit 11 to the connector 34F (the furthest from the memory controller) is the “bound portion”, and the portion from the connector 34F to the input circuit is the “return portion”. In addition, the portion from the output circuit 12 to the connector 34F is the “bound portion”, the remaining portion (that is, the portion returning to the memory module ahead of the outbound portion) is the “return portion”, and the read data For wiring, the portion from the connector 34F to the input circuit 14 is referred to as “return portion”, and the remaining portion (that is, the portion before the return portion and the portion from connector 34A to connector 34F) is referred to as “bound portion”. If so, the following rules should be observed to connect the connectors.
(1) When the clock wiring is connected to the connector at the “outward part”,
-The write data wiring is connected to the connector at the "bound part"
• Wire the read data wiring at the “return part”.
(2) When the clock wiring is connected to the connector at the “return part”,
-The write data wiring is connected to the connector at the "return part"
・ Wiring for read data is done at the “bound part”.

In order to improve accuracy, the wiring layout may be performed in consideration of the following.
(1) The wiring length of the wiring 15 from the output circuit 11 to the input circuit 50 in the module is matched with the wiring length of the wiring 16 from the output circuit 12 to the input circuit 51 in the module, or the wiring load is adjusted.
(2) The wiring length of the wiring 16 from the output circuit 12 to the input circuit 51 in the module and the wiring length of the wiring 17 from the output circuit 52 to the input circuit 14 in the module are matched between modules, or the wiring load is Match.

  Increasing the accuracy of matching these wiring lengths and wiring loads has the effect of increasing the value of t window -tpd (max-min) accordingly.

In addition, as means for applying the clock phase offset,
(1) A method of placing a circuit, such as a delay circuit, for causing a propagation delay in either the memory controller or the clock wiring distributed to each memory module. This circuit may be placed on all the wirings or only on one of the signals.
(2) A method in which the delay circuit function of (1) is provided on the clock transmission source or distribution / frequency division source side. At this time, it is better that the delay can be adjusted by an external pin. For this purpose, several delay circuits are built in these clock sources, and a method of selecting them from the outside or a plurality of delay circuits are prepared, and how many of these circuits are used externally. There is a method to specify from.

  Also, when connecting the clock signal and data signal to the connector in the wiring connecting the memory controller and the connector, rather than using only the “bound portion” or “return portion (or return portion)” It is better to distribute and connect the “bound part” and the “return part (or return part)”. This is because the load due to the connection to the connector can be distributed, and the drop in the effective impedance of the signal wiring can be suppressed.

There are the following effects to suppress the drop in impedance.
(1) When the output of the output circuit is switched, it is possible to suppress a drop in the signal amplitude transmitted to the memory module first. In particular, in the case of a small amplitude signal, the signal amplitude of the first wave output from the output circuit is reduced due to a drop in impedance, and as a result, the noise margin of the input signal is reduced and sometimes prevents a malfunction.
(2) The quality for various uses can be improved. Depending on the user's usage, like the memory module, the module may be fully mounted on all connectors, or the module may be mounted on some connectors and other connectors may be left empty. In this way, when the usage changes, in order to guarantee performance in all conditions, a performance margin can be secured by reducing the amount of change in the device's characteristics, in this case the effective impedance of the wiring, Quality can be improved.

  As shown in FIG. 4, the connection method with the connector that makes the best use of these effects is a method of alternately connecting the “bound portion” and the “return portion (or return portion)”.

  Further, as a method of suppressing the drop in impedance, it is possible to use a signal wiring whose impedance of the wiring 15, 16 or 17 is lower than that of the module. For example, about 50Ω (for example, 40 to 60Ω).

  By mounting the module, the effective impedance is reduced to 20 to 40Ω, but this value is almost equal regardless of whether the wiring is 50Ω or 75Ω. That is, in this case, the difference in impedance before and after mounting the module can be reduced by using 50Ω wiring.

  In the present embodiment, an example in which the four circuits 11 to 14 are in one circuit block 32 is shown, but it goes without saying that the scope of the present invention is not limited by the configuration. These circuits may be separated into a plurality of circuit blocks. However, the configuration having four circuits in one circuit block 32 is superior in terms of performance and manufacturing cost.

  Considering the configuration of the current memory controller, it is also desirable to separate only the output circuit that outputs the clock signal into other circuit blocks.

  Further, in this embodiment, an example is shown in which both data writing to the memory module and data reading from the memory module are applied. However, the clock distribution of the present invention is used only for data writing, and for data reading, Conventional techniques can also be applied. Such a compromise configuration with the prior art may be used, and alternative examples of the circuit configuration are the same in the following embodiments.

  FIG. 6 shows an example in which a terminating resistor is added to the above-described wirings 15 to 17 with respect to the embodiment shown in FIG. In FIG. 6, reference numerals 40 to 45 denote termination resistors. As a matter of course, the termination resistor is connected to the termination power source.

  FIG. 6 shows an example of both-end termination, but the effect can be achieved even with one-end termination. For more effective termination, it is preferable to terminate both ends. However, when the direction of the signal is only one side, for example, in the case of a control signal line or an address signal line, it may be a one-side termination. At that time, the end is preferably on the opposite side of the output circuit.

  In many cases, the resistance value of the termination resistor is terminated with the impedance of the transmission line. However, in order to be more effective, it is preferable to terminate with the effective impedance value of the transmission line. However, even if this value is not strictly matched, even if there is a deviation of about ± 20Ω, the termination effect is obtained.

  In FIG. 1, matching resistors (46, 47, 48, 49) for impedance matching between wirings are inserted between the branch wirings (15A, 15B, 16A, 17A) and the wirings (15, 16, 17). An example is shown. This matching resistor is inserted for the purpose of reducing the amplitude of the signals on the wirings 15 to 17 and suppressing the reflection of the signal at the wiring branching point by matching the impedance between the wirings.

  This matching resistance is described in detail in Japanese Patent Application No. 5-334631 (Japanese Patent Application Laid-Open No. 7-202947) and Japanese Patent Application No. 7-26495 (Japanese Patent Application Laid-Open No. 7-28383) previously filed by the applicant of the present application. .

  This resistance has an effect of suppressing reflection at the branch point in signal propagation from the branch wiring to the main wiring. This resistance value is preferably set to a value obtained by subtracting half of the impedance of the wiring (15, 16, 17) from the impedance value of the branch wiring (15A, 15B, 16A, 17A). However, when the effective impedance of the main wiring is lowered by mounting the memory module on the main wiring, the effective impedance value of the main wiring may be used instead of the impedance value of the main wiring.

  The reference resistance value is desirably in the range of about 0.5 to 1.5 times the previously obtained value. However, even if it is about twice, it is effective for speeding up by reducing the amplitude.

  As described above, when the matching resistors (46, 47, 48, 49) shown in FIG. 1 are provided, the memory module side is preferably provided with resistors as shown in FIGS. It is desirable that this resistor has a value that achieves impedance matching between the wiring in the memory module and the wiring on the motherboard (15, 16, 17) and realizes low amplitude of signals on the wirings 15-17. The method of determining the resistance value of this resistor is the same as that of the matching resistors 46 to 49 described above. At that time, the branch wiring is calculated as the wiring in the memory module.

  Next, another embodiment (embodiment 2) of the present invention is shown in FIG. What has been clarified in the above embodiments can be applied to the following embodiments, and thus will not be described repeatedly. Only the differences are clarified.

  In the present embodiment, the clock signal output from the memory controller is separated into a read clock and a write clock, and the clock signal is transmitted in the same clock wiring 15 in different directions for reading and writing. This is a transmission method. Here, 11 is a write clock output circuit, 11A is a read clock output circuit, and 13 is a reception circuit that receives a clock for fetching read data by the memory controller. Reference numerals 12 and 14 denote a circuit 12 for outputting data and a circuit 14 for receiving data, respectively.

  Although not shown in FIG. 5, it is desirable that the memory controller 32 has a logic circuit for controlling the outputs of the output circuits 11 and 11A so that both are not operated and used.

As in the first embodiment, the portion of the clock wiring 15 from the output circuit 11 toward the connector 34F (the furthest from the memory controller) is the “bound portion” and the “bound portion”, that is, from the connector 34F. A portion toward the connector 34A is a “return portion”, a portion of the data wiring 16 that is directed from the output circuit 12 to the connector 34F is a “bound portion”, and the remaining portion (that is, the memory module ahead of the outbound portion). If the “returning part” is the “returning part”, the connector should be connected according to the following rules.
(1) When the clock wiring is connected to the connector at the “outward part”,
・ Connect the data wiring to the connector at the “outward part”.
(2) When the clock wiring is connected to the connector at the “return part”,
• Connect the data wiring to the connector at the “return part”.

  In this way, the same effect as that of the first embodiment can be obtained by reducing the data signal wiring by half, that is, from two sets of the write-only wiring and the read-out wiring to one set for writing / reading. I can do it.

The output section of the write clock signal output circuit and the input section of the read clock input circuit may be connected inside or outside the circuit block (integrated circuit or component). (FIG. 5 shows an example of connection in a circuit block)
The second embodiment is an example in which the memory LSI mounted on the memory module is applied to a type having an I / O common, that is, an input / output circuit having both an input circuit and an output circuit. In this embodiment, the circuit in the module used has the configuration shown in FIG. 26 as compared to FIG. 21 of the first embodiment. An output circuit 51 that outputs data and the like and a receiving circuit 52 that receives the data are connected.

  FIG. 7 is a type in which the memory controller 32 is connected to the wirings 15 and 16 via the branch wirings 15A to 16A in the second embodiment (the same type as FIG. 6 in the first embodiment). This is a type in which matching resistors 46 to 48 are interposed between the branch wires 15A to 16A and the wires 15 and 16 (the same type as that in FIG. 1 of the first embodiment).

  Next, a third embodiment will be described. In the first and second embodiments, examples of bidirectional signals such as data signals have been shown. However, unidirectional transmission of address signals or control signals is shown in FIGS. Thus, it can be easily done by deleting the path where the clock returns to the memory controller. This can be applied only to a line that uses only a data signal for writing.

  In this case, however, two types of clocks, that is, a data clock and other signal clocks are supplied to each memory module. However, an address signal and a control signal may be taken in using the data clock circuit. At this time, when there are two clocks as in the second embodiment, the address signal and the control signal may be captured by the SDRAM using the write-only clock. The circuit in the memory module at this time is of the type shown in FIG. 27 as compared to FIG. 21 in the first embodiment.

  FIG. 12 shows a fourth embodiment as an application of the second embodiment. Provided is a method for allowing a clock signal to be propagated only in one direction as in the first embodiment when a memory controller common to I / O is used.

  That is, a clock signal is output from the output circuit 11 and a write data signal is output from the output circuit 12. At this time, the switch 90 connects the input / output circuit (divided into the output circuit 12 and the input circuit 14 in the figure) and the transmission line 16A. In this way, the clock signal and the data signal can be transmitted from the memory controller 32 to the connectors 34A to 34F to the memory module on the connector via substantially the same wiring length.

  Further, at the time of reading, the switch 90 connects the input / output circuit and the transmission line 16B, and latches the data transmitted from the 16B by the clock transmitted from the 15B. By doing so, it can be applied to a circuit having a data line common to I / O using the clock control method shown in the first embodiment.

  In the first to fourth embodiments shown so far, the clock for fetching data is generally different in phase from the clock inside the memory controller. That is, in order to use the read data in the memory controller further, it is necessary to change the clock (in this case, change from the return clock to the internal clock) so that it can be controlled by the clock in the memory controller. Therefore, a retiming circuit, for example, a first-in first-out (FIFO) circuit may be provided at the tip of the input circuit 14. The memory controller may have a means for determining which cycle of the internal clock should be latched based on the magnitude of the phase shift between the clock propagated through the wiring 15 and the internal clock.

  In addition, by using the wiring length, the delay circuit, and the like, the phase of the output clock and the returning clock are matched to facilitate the data capture.

  FIG. 35 shows an example in which the memory controller 32 is provided with an embodiment of the retiming circuit described above. The retiming circuit includes at least a D-type latch circuit 25A and a flip-flop circuit 25B. The D-type latch circuit 25A passes the input data when the input clock is High (or Low), and the clock becomes High (or Low) again when the data is switched to Low (or High). Has the ability to hold up.

  The D-type latch circuit 25A is supplied with a return clock, 2φ ′ positive logic or non-logic as a clock, and the flip-flop circuit 25B has an internal clock of the memory controller 32, 2φ positive logic or negative logic. Input as clock.

  Which of these clocks is used is uniquely selected according to the magnitude of the phase difference between the clock 2φ inside the memory controller 32 and the returned clock 2φ ′.

  For example, if the magnitude of the phase difference between 2φ and 2φ ′ is shifted by exactly a half phase, a negative logic clock of 2φ ′ is input to the D-type latch circuit 25A in order to correct the deviation, A positive logic clock of 2φ is input to the flip-flop circuit 25B.

  When the phase difference between 2φ and 2φ ′ is exactly the same, a positive logic clock of 2φ ′ is input to the D-type latch circuit 25A, and a positive logic of 2φ is input to the flip-flop circuit 25B. A clock is input.

  As another embodiment, when the respective phases are matched, the flip-flop circuit 25B is not necessary, so the output of 25A may be directly transmitted to the inside of the memory controller.

  When a clock for operating the memory module is supplied to each memory module by a separate wiring in addition to the clock output from the memory controller 32, the above-described retiming circuit may be provided on the memory module side.

  FIG. 36 shows an embodiment in which the retiming circuit shown in FIG. 35 is applied to the circuit of FIG. FIG. 36 shows an example in which the clock φ is output not from the memory controller but from the clock distribution circuit before the connector 34A. Although the clock supply method shown in FIG. 1, that is, the clock φ may be supplied from the memory controller, the clock access time of the memory controller is generally faster than the clock access time of the memory LSI. For this reason, reading is severer than writing. Therefore, the clock output circuit is moved from the memory controller to the front of the connector 34A, the clock phase is brought forward, and the time required for writing and reading is matched.

  In addition, although the present Example showed the 2nd Example shown in FIG. 12 as an example, it cannot be overemphasized that it can apply also to another Example. FIG. 36 shows an example in which a PLL (Phase Locked Loop) 70 (A) with a frequency divider 71 is outside the memory controller. The clock signal supplied from the clock signal transmission circuit 360 via the clock distribution circuit 361 or the like is divided. Needless to say, the PLL 70 (A) may be inside the memory controller.

  Furthermore, FIG. 37 shows a fifth embodiment of the present invention. In this embodiment, the transmission lines 15 and 16 are laid out over the two connector rows 34A to 34F and 34G to 34M.

  In the embodiment shown above, the connector row connected on the “outbound wiring” and the connector row connected on the “return wiring” are the same example, but in this embodiment, The connector rows (34A to 34F in the example in the figure) connected on the “bound wiring” are different from the connector rows (34G to 34M in the example in the figure) connected on the “return wiring”. As a result, the number of transmission lines laid out under the connector is halved (from either “outbound wiring” or “return wiring” to “outbound wiring” or “return wiring”). The layout becomes easy and the number of signal wiring layers on the substrate can be reduced.

  FIG. 37 shows an example in which the transmission lines 15 and 16 are connected to all the connectors, but some connectors, for example, every other connector may be connected.

  Of course, in the diagrams shown before FIG. 37, the connector is connected to either “bound wiring” or “return wiring”, but there is a connector that is not connected to either wiring. Good. For example, two wirings are laid out in parallel and connected to even-numbered connectors, ie, 34B, 34D,..., 34F, and odd-numbered connectors, ie, wires connected to 34A, 34D,. It may be divided into

  Further, the embodiment shown in FIG. 37 can be applied to the embodiment shown in FIG. 36 and further to the embodiment shown in FIG.

  Next, a sixth embodiment will be described. In the first to fifth embodiments, when the data read from the memory module 30 is received on the memory controller 32 side, the data is received in synchronization with the clock signal output from the memory controller 32 and received through the wiring 15. In the sixth embodiment, the memory module that outputs data generates a trigger signal for taking the timing to receive the data output from the memory module. Details will be described below.

  FIG. 46 shows a sixth embodiment.

  The memory controller 161 includes a clock output circuit 171, a clock synchronous output circuit 172, an input circuit 181, and an input circuit 182 that synchronizes with a signal captured by the input circuit 181.

  The output circuit 172 and the input circuit 182 are data circuits.

  Further, the transmission lines 114 to 117 are wirings drawn when the memory controller is modularized or depending on the layout on the motherboard, and are not necessarily present, and the present invention is not limited by the presence or absence of the wirings. Absent.

  In the following embodiment, an example in which these four circuits are configured by one circuit block is shown, but these circuits may be separated into a plurality of circuit blocks.

  The wiring 110 is a clock necessary for a signal output from the memory controller 161 to be captured on each memory module mounted on the connectors 140 to 145, and is a wiring for a signal output from the memory controller 161. is there.

  Further, the wiring 111 is a wiring for transmitting a trigger signal (return clock) necessary for taking in the data read from the memory on the memory module by the memory controller, and this trigger signal is output from the read memory. .

  Unlike the clock output from the memory controller, only one pulse is output for this trigger signal for one read data.

  Further, the trigger signal is preferably delayed from the data by, for example, a setup time of the memory controller so that the read data can be captured on the memory controller side. Furthermore, in order to satisfy the hold time of the memory controller, it is desirable that the output of the memory holds data longer than the hold time of the memory controller after the trigger signal is output.

  In FIG. 46, attention is paid to each of the clock signal and the data signal in the memory circuit one by one, and all other circuits are omitted, so only one set of these input circuits and output circuits is shown. It goes without saying that the number does not limit the present invention.

  Each wiring and connector are connected at a black circle (•).

  That is, in the example of FIG. 46, the clock signal output from the memory controller is transmitted to the connectors 140, 142,. The data write signal wiring 112 is also connected to the connector in the same order as the clock wiring.

  The data reading wiring 113 and the trigger signal wiring 111 output from the memory are connected to the connector in the reverse order to the data writing data. That is, the data write wiring is connected from the memory controller to each connector 141, 143,.

  By doing so, the sum of the propagation time at the time of data writing and the propagation time at the time of reading becomes uniform regardless of the position of the memory module.

  At this time, it is desirable to design the clock signal wiring, the trigger signal wiring and the data writing wiring, or the reading wiring to have the same propagation time.

  When there is a connector where the memory module is not touched, there is a method of suppressing a change in effective impedance due to a change in the number of mounted modules by mounting a load equivalent to the memory module with a dummy.

  In FIG. 46, one embodiment of both-end terminations is shown. However, as shown in FIG. 47, signals that propagate only in one direction, such as wirings 110 and 112, may be terminated on one side. As a result, the number of parts mounted can be reduced, and current consumption can be reduced. Further, when the lengths of the wirings 114 to 117 are sufficiently short, for example, when the propagation time in these wirings is about 1/6 or less of the rising time or falling time of the signal waveform, the resistors 150 to 153 can be removed. It is. However, in this case, since the signal amplitude in the bus 110 increases, it is desirable to review such as reducing the signal amplitude itself output from the output circuit. This example is shown in FIG.

  Further, the present circuit can be applied to a small amplitude circuit that has been clarified by the applicant in Japanese Patent Application No. 5-334631 (Japanese Patent Laid-Open No. 7-202947). That is, the resistors 150 to 153 have an effect of suppressing reflection at the branch point in signal propagation from the branch wirings 114 to 117 to the main wiring 110. This resistance value is preferably set to a value obtained by subtracting the impedance of the main wiring from the impedance value of the branch wiring. However, when the effective impedance of the main wiring is lowered by mounting the memory module on the main wiring, a smaller value than the previous value may be used.

  The reference resistance value is desirably in the range of about 0.5 to 1.5 times the previously obtained value.

  Next, a seventh embodiment will be described below. Note that what has been clarified in the above-described embodiments can be applied to the following embodiments, and thus will not be described repeatedly. Clarify the differences.

  In the sixth embodiment, an example in which the input circuit and the output circuit of the memory controller 161 and the memory module 162 are separated has been described. However, FIG. 49 employs an input / output circuit for the memory controller 161 and the memory module 162. One embodiment is shown. For example, the input / output circuit is described using the memory controller shown in the figure. The output unit of the output circuit 172 and the input unit of the input circuit 182 are connected in a circuit block 161 (for example, an integrated circuit), and the terminal of the circuit block. Is a circuit that is not separated but is a common terminal.

  In this case, a switch 190 is inserted, and the switch is connected to the circuit block transmission line 161 side when data is written and to the transmission line 117 side when data is read.

  As a result, the same effect as that of the first embodiment can be applied to a system having an input / output circuit. FIG. 50 shows an example in which the circuit of FIG. 49 is terminated on one side, as in FIG. 47, and FIG. 51 shows an example in which the insertion resistance is deleted, as in FIG.

  The circuit diagrams shown in FIGS. 53 and 54 are diagrams focusing on the memory 1 chip in the memory module, FIG. 53 is the circuit diagram of the module applied to the embodiment shown in FIG. 46, and the input circuit 181 is For clock input, the output circuit 171 is a circuit for outputting a trigger signal serving as a return clock, the output circuit 172 is a circuit for outputting read data, and the input circuit 182 is a circuit for inputting write data. FIG. 54 shows a circuit example in the case where a data signal is output and input by an input / output circuit.

  Note that there is generally one input circuit 181 for inputting a clock signal for one chip, and write data, control signals, and address signals are taken in by the clock input by this circuit.

  Another embodiment shown in FIG. 52 is an example in which “bound wiring” and “return wiring” are passed through different connector rows. By doing so, the “outbound wiring” and the “return wiring” can be laid out in the same layer on the substrate wiring, and the present invention can be realized without increasing the number of substrate layers.

  The circuit diagram shown in FIG. 55 is a circuit showing in detail the output circuit and input circuit of the clock signal and data signal of the memory controller in the present invention.

  The flip-flops 191D and 191S operate in synchronization with the internal clock, and the flip-flop 191L operates in synchronization with the trigger signal from the memory received by the input circuit 181.

  As a result, the write data output from the memory controller is output in synchronization with the clock inside the chip, and the data read from the memory is received with the setup and hold times secured by the trigger signal, and the flip-flop at the next stage is received. Is retimed to the internal clock (the phase is adjusted to the internal clock).

  By doing this, it is possible to exchange signals from the memory controller to the processor bus in phase with the internal clock.

  In the present embodiment, the flip-flop 191S used for the retiming is an example of one stage, but the number of stages is naturally not limited to one, and in this case, it is input to the flip-flop. The phase of the clock can be realized by taking a phase between the internal clock and the trigger signal, or by using multiple clocks of the internal clock.

  Next, improvement of clock signal transmission in the present invention will be described. In the above embodiment, the clock signal operates under the same load as the data signal. However, for example, in order to perform data transfer at 100 HMz, the clock cycle must be 10 ns (frequency is 100 MHz) and the data cycle is 20 ns (cycle is 50 MHz). I must. Therefore, a method for supplying a clock stably in the present invention will be described below.

  First, the frequency (cycle) of the clock is made the same as that of a signal such as data. Then, a double clock of the input clock is generated in the module or in the memory LSI, and the signal acquisition and output of the SDRAM are controlled in synchronization with the generated clock.

  Similar functions are also provided on the memory controller side.

  In addition, although it is a method of doubling, in order to stabilize the duty to around 50%, it is better to multiply by 4 once using a PLL, and then divide by 2 and return to 2 times. In general, N is a natural number, multiplied by 2 (N + 1), and divided by N + 1.

  These are shown in FIGS. 28 to 34.

  In FIG. 28, the clock 2φ is generated by using a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 to generate a clock φ having a frequency 0.5 times, and the clock is output from the memory controller 32 by using the output circuit 11. To do. In addition, the original clock 2 FIG. 29 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is located ahead of the output circuit 11. By this method, the present invention can be applied to a memory controller 32 that does not have a PLL (Phase Locked Loop) 70 with a frequency divider 71.

  In FIG. 30, the clock φ ′ received by the receiving circuit 13 is generated by using a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 to generate a clock 2φ ′ having a double frequency, and the receiving circuit 2 is used by using the clock 2φ ′. The signal received at 14 is latched by the flip-flop 25. Here, the clock to be latched is 2φ ′, not the clock 2φ supplied inside the memory controller. Although 2φ and 2φ ′ have the same frequency, 2φ ′ is a clock generated from φ ′ that is a clock that is output from the memory controller and returned again, and generally has a different phase.

  FIG. 31 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is in front of the receiving circuit 13. By this method, the present invention can be applied to a memory controller that does not have a PLL (Phase Locked Loop) 70 with a frequency divider 71.

  FIG. 32 shows an embodiment of a clock output circuit and an input / output circuit. A clock φ having a frequency half that of the internal clock 2φ is generated by a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71, and the clock is output from the memory controller by the output circuit 11. Also, the clock φ ′ returned to the memory controller is received by the input circuit 13, and a clock 2 φ ′ having a double frequency is generated by a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71. Data output from the output circuit 12 is output in synchronization with the clock 2φ, and data received by the reception circuit 14 is received in synchronization with the clock 2φ ′.

  FIG. 33 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is provided in front of the output circuit 11 and in front of the input circuit 13 as in FIG.

  FIG. 34 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency divider 71 is used for the memory module. In order to supply φ ′ transmitted on the memory bus to the clock pin of the synchronous memory 31, for example, the SDRAM, in order to restore the clock whose frequency is halved on the memory controller side, Using the (Phase Locked Loop) 70, the frequency is doubled to generate a clock 2φ ′, which is supplied to the memory 31.

  In the example shown in FIGS. 32 and 33, an example of an I / O circuit type memory controller having both a receiving circuit and an output circuit is shown. However, in FIGS. 38 and 39, the receiving circuit and the output circuit are different. The present invention is applied to an I / O separation type memory controller having separate terminals. The difference between FIG. 38 and FIG. 39 is the difference between the case where the PLL circuit is inside the memory controller and the case where it is outside, like the difference between FIG. 32 and FIG.

  Further, a memory module shown in FIG. 40 is provided for the I / O separation type memory module. This is an application example of the I / O separation type with respect to FIG. 34 of the I / O circuit type.

  In addition, the present invention provides a memory module having a register type buffer (FIG. 42) and a memory module having a simple buffer (a buffer that is used as an intermediate buffer and does not latch, also referred to as a through type or a bus driver). (FIG. 43).

  Further, the present invention is naturally effective even when a resistor is inserted on the memory module side as compared with the embodiments of the present invention that have been clarified so far. With this resistor, not only the amplitude can be reduced, but also impedance matching can be achieved and reflection noise can be prevented.

  41 shows an embodiment in which a resistor is added to FIG. 40, and FIGS. 44 and 45 show an embodiment in which a resistor is added to FIGS. 42 and 43, respectively.

  13 to 14 show the state of a board on which one embodiment of the present invention is realized. FIG. 13 shows a state in which the memory controller 32 is directly mounted on the motherboard, and the memory module 30 in which the memory IC (SDRAM) 31 is mounted on the daughter board is mounted on the motherboard via the connector 34.

  FIG. 14 shows an example in which the memory controller 32 is mounted on a daughter board and modularized. 15 and 16 show an example in which the memory IC 31 is directly mounted on the mother board without using a connector.

  Some of the embodiments described above can also be used to connect a cache memory and a processor. Furthermore, as shown in FIG. 17, a workstation or a personal computer has various buses such as a processor bus, a memory bus, and a peripheral bus. In the present invention, the connection between the memory module and the memory module has been shown as an example. However, the present invention is not limited to the memory bus, and is effective in other buses, regardless of whether a connector is used and whether it is modularized. Needless to say. Further, the present invention can be applied to a multi-module in which a plurality of LSIs are housed in one package, instead of being mounted on a board.

The figure which shows the connection relation of a memory controller and a memory module, and a wiring pattern about the application example of the 1st Example of this invention. The figure which shows the signal transmission apparatus of the conventional single phase clock system system. The figure which shows the mounting structure and circuit of the conventional memory system. The figure which shows the connection relation and wiring pattern of the memory controller and memory module about 1st Example of this invention. The connection relation between the memory controller and the memory module and the wiring pattern in the second embodiment of the present invention are shown. FIG. 6 is a diagram illustrating an example in which the direction of a clock signal is inverted between reading and writing when the present invention is applied to a common input / output circuit. The figure which shows the connection relation and wiring pattern of the memory controller of an application example of the 1st Example of this invention, and a memory module. The figure which shows the connection relation and wiring pattern of a memory controller and a memory module about the application example of the 2nd Example of this invention. The figure which shows the connection relation and wiring pattern of a memory controller and a memory module about the application example of the 2nd Example of this invention. The connection relationship and wiring pattern between the memory controller and the memory module according to the third embodiment of the present invention are shown. The figure which shows the example applied to the signal transmission of a single direction. The figure which shows the connection relation and wiring pattern of a memory controller and a memory module about the application example of the 3rd Example of this invention. The figure which shows the connection relation and wiring pattern of a memory controller and a memory module about the application example of the 3rd Example of this invention. The figure which shows the connection relation and wiring pattern of the memory controller and memory module of 4th Example of this invention. The figure which shows the mounting structure at the time of applying this invention to a memory system. The figure which shows the mounting structure at the time of applying this invention to a memory system. The figure which shows the mounting structure at the time of applying this invention to a memory system. The figure which shows the mounting structure at the time of applying this invention to a memory system. The block block diagram of an information processing system. The figure which shows the external shape of a memory module. The figure which shows the data signal wiring on a memory module. The figure which shows the address, control, and clock signal wiring on a memory module. The figure which shows the input-output separation type SDRAM circuit on a memory module. The figure which shows the signal connection at the time of inserting a buffer circuit on the address / control / clock signal wiring on the memory module. The figure which shows signal connection at the time of inserting resistance on the data signal wiring on a memory module. The figure which shows the signal connection at the time of inserting a resistor on the address / control / clock signal wiring on the memory module. The figure which shows signal connection at the time of inserting a buffer circuit and resistance on the address, control, and clock signal wiring on a memory module. The figure which shows the input / output common type SDRAM circuit on a memory module. The figure which shows the address, control, and clock signal input circuit of SDRAM which exists on a memory module. The figure which shows the clock output circuit of the memory controller in which a PLL circuit is inside a memory controller. The figure which shows the clock output circuit of the memory controller in which a PLL circuit is outside a memory controller. The figure which shows the clock input circuit of the memory controller which has a PLL circuit inside a memory controller. The figure which shows the clock input circuit of the memory controller in which a PLL circuit is outside a memory controller. The figure which shows the input / output common type memory controller which has a PLL circuit inside a memory controller. The figure which shows the input / output common type memory controller with a PLL circuit outside a memory controller. The figure which shows the clock input in a memory module with a PLL circuit. The figure which shows the memory controller provided with the retiming circuit. The figure which shows the memory system of this invention using the retiming circuit of this invention. The figure which shows the 5th Example of this invention. The figure which shows the clock output circuit of the input-output separation type memory controller in which a PLL circuit is in a memory controller. The figure which shows the clock output circuit of the input-output separation type memory controller in which a PLL circuit is outside a memory controller. The figure which shows the clock input in the memory module which has the input-output separation type SDRAM circuit. The figure which shows the clock input in a memory module with an insertion resistance and an input-output separation type SDRAM circuit. The figure which shows the memory module which has the register type buffer circuit and the input / output common type SDRAM circuit. The figure which shows the memory module which has the through type buffer circuit and the input / output common type SDRAM circuit. The figure which shows the memory module which has the insertion resistance, the through type buffer circuit and the input / output common type SDRAM circuit. The figure which shows the memory module which has the insertion resistance, the register type buffer circuit and the input / output common type SDRAM circuit. The figure which shows the 6th Example of this invention. The modification of the 6th Example of this invention is shown. The figure which shows the bus structure of the one side termination | terminus. The figure which shows the modification of the 6th Example of this invention. The figure which shows the 7th Example of this invention. The figure which shows the modification of a 4th Example. The figure which shows the modification of a 4th Example. The figure which shows a retiming circuit. The figure which shows one Example of the memory module circuit connected to a 6th Example. The figure which shows one Example of the memory module circuit connected to a 7th Example. The figure which shows the 8th Example of this invention.

Explanation of symbols

11, 11A, 12, 26,... Output circuit, 13, 14, 27, .. receiving circuit 24, 25. flip-flop 25A, .. D type latch circuit, 25B .. flip-flop circuit 15-17, 15A-15D, 23, 35, 37 ... Transmission line 21, 22 ... Circuit block 30 ... Memory module, 31 ... Memory LSI, 32 ... Memory controller 33 ... Motherboard, 34 ... Connector, 36 ... Module contact 38 .. Mark indicating contact between transmission line and connector 40-45 .. Terminating resistor (including terminating power supply)
46 to 49 ··· matching resistor 60 ·· resistor 61 · · buffer circuit 70 · · PLL circuit 71 · · divider circuit 90 · · switch circuit

Claims (20)

A first circuit block comprising a first output circuit for outputting a first signal and a first receiving circuit for receiving a second signal;
A plurality of second circuit blocks including a second receiving circuit for receiving the first signal and a second output circuit for outputting the second signal;
In the signal transmission device having a wiring connecting the first circuit block and the second circuit block,
The first circuit block includes a third output circuit that outputs a third signal;
A third receiving circuit for receiving the third signal,
The second circuit block includes a fourth receiving circuit that receives the third signal,
The wiring includes a first wiring that propagates the first signal, a second wiring that propagates the second signal, and a third wiring that propagates the third signal,
The first wiring, the second wiring, and the third wiring are respectively folded back at a position farther than the second circuit farthest from the first circuit block, and laid out,
A second circuit block connected to the first wiring and the third wiring between the first circuit block and the folded position, and connected to the second wiring before the folded position;
The first wiring and the third wiring are connected to the first circuit block from the folded position, and the second wiring, the first circuit block, and the folded position are connected to each other. 2 circuit blocks are arranged alternately,
The second receiving circuit latches the first signal in synchronization with the third signal received by the fourth receiving circuit;
The first receiving circuit latches the second signal in synchronization with the third signal received by the third receiving circuit;
The second output circuit outputs the second signal in synchronization with the third signal received by the fourth receiving circuit. The signal transmission device according to claim 1,
The signal transmission device according to claim 1, wherein the first, second, and third wirings include termination resistors. In the signal transmission device according to claim 1 or 2,
A first branch wiring for transmitting the first signal between the first output circuit and the first wiring is provided between the second receiving circuit and the second wiring. A second branch wiring for transmitting the second signal, and a third branch wiring for transmitting the third signal between the third output circuit and the third wiring. A fourth wiring for transmitting the third signal between the receiving circuit and the third wiring;
The first branch wiring has a first resistance element;
The second branch wiring has a second resistance element;
The third branch wiring has a third resistance element,
The signal transmission device, wherein the fourth branch wiring has a fourth resistance element. The signal transmission device according to claim 3, wherein
The resistance value of the first resistance element is in the range of half to twice the value obtained by subtracting half of the impedance of the first wiring from the impedance value of the first branch wiring, and The resistance value of the second resistance element is in the range of half to twice the value obtained by subtracting half of the impedance of the second wiring from the impedance value of the second branch wiring, and the third resistance The resistance value of the element is in the range of half to twice the value obtained by subtracting half the impedance value of the third wiring line from the impedance value of the third branch wiring line. The signal transmission device according to claim 1, wherein a resistance value is in a range of half to twice a value obtained by subtracting a value of half of the impedance of the third wiring from a value of impedance of the fourth branch wiring. A first circuit block having a first transmission / reception circuit including a first transmission circuit for outputting a first data signal and a first reception circuit for receiving a second data signal;
A second circuit block having a second transmission / reception circuit including a second reception circuit for receiving the first data signal and a second transmission circuit for outputting the second data signal;
In the signal transmission device having a wiring connecting the first circuit block and the second circuit block,
The first circuit block includes a third transmission / reception circuit including a third output circuit that outputs a third clock signal and a third reception circuit that receives a fourth clock signal;
A fourth transmission circuit for outputting the fourth clock signal;
The second circuit block includes a fourth receiving circuit that receives the third clock signal and the fourth clock signal,
The wiring includes a first wiring for transmitting the first and second data signals between the first transmission / reception circuit and the second transmission / reception circuit, the third transmission / reception circuit, and the fourth reception circuit. And a second wiring for transmitting the third and fourth clock signals between the fourth transmission circuit and the fourth reception circuit,
The first and second wirings are folded and laid out at a position farther than the second circuit block farthest from the first circuit block,
Connected to the first wiring from the first transmission / reception circuit to the folding position of the first wiring, and from the second wiring and the third transmission / reception circuit to the folding position of the second wiring. A second circuit block connected between
A second circuit that connects to the first wiring first from the turn of the first wiring and connects the second circuit and the second circuit block that connects first from the turn-up position of the second wiring. Place the blocks alternately,
The second receiving circuit latches the first data signal in synchronization with the third clock signal, and the second output circuit synchronizes with the fourth clock signal. Output signal,
The signal transmission device, wherein the first receiving circuit latches the second data signal in synchronization with the fourth clock signal. The signal transmission device according to claim 5, wherein
The signal transmission device according to claim 1, wherein the first and second wirings include termination resistors. The signal transmission device according to claim 5 or 6,
There is a third wiring for transmitting the first and second signals between the first transmission / reception circuit and the first wiring, and between the third transmission / reception circuit and the second wiring. There is a fourth wiring for transmitting the third and fourth signals, and a fifth wiring for transmitting the fourth signal is provided between the fourth output circuit and the second wiring.
The third wiring has a first resistance element;
The fourth wiring has a second resistance element,
The signal transmission device, wherein the fifth wiring includes a third resistance element. The signal transmission device according to claim 7, wherein
A resistance value of the first resistance element is in a range of half to twice a value obtained by subtracting a half value of the impedance of the first wiring from a value of the impedance of the third wiring; The resistance value of the resistance element is in the range of half to twice the value obtained by subtracting half the impedance value of the second wiring from the impedance value of the fourth wiring, and the resistance value of the third resistance element is A signal transmission device having a value in a range of half to twice a value obtained by subtracting a value of half of the impedance of the second wiring from a value of impedance of the fifth wiring. A first output circuit that outputs a first signal; a first reception circuit that receives the first signal; and a first input / output circuit that outputs a second signal and receives a third signal. A first circuit block;
A plurality of second circuit blocks having a third receiving circuit for receiving the first signal, a fourth receiving circuit for receiving the second signal, and a third output circuit for outputting the third signal; Have
The first wiring for transmitting the first signal and the second wiring for transmitting the second signal and the third signal are each a second circuit farthest from the first circuit block. , Or at a position further away from the position, and laid out so as to return to the first circuit block again,
Connected to the first wiring from the first transmission circuit to the folded position of the first wiring, and from the second wiring and the first transmission / reception circuit to the folded position of the second wiring A second circuit block connected between
The second circuit block is connected alternately to the first wiring after the first wiring is folded, and the second wiring is connected to the second wiring and the second wiring block is connected first from the folding position of the second wiring.
The second wiring and the first input / output circuit are connected so that the second signal is transmitted in the same direction as the first signal, and the third signal is transmitted in the opposite direction to the first signal. A switch circuit with a switch function is inserted between
The third output circuit outputs a third signal in synchronization with the first signal;
The signal transmission device according to claim 1, wherein the first input / output circuit latches the third signal in synchronization with the first signal. The signal transmission device according to claim 9, wherein
The signal transmission device according to claim 1, wherein the first wiring or the second wiring is terminated on one side or both sides. In the signal transmission device according to claim 9 or 10,
There is a third wiring for transmitting a first signal between the first output circuit and the first signal wiring, and a second signal is provided between the switch circuit and the second signal wiring. And a fourth wiring for transmitting a third signal, and a fifth wiring for transmitting a third signal between the switch circuit and the second signal wiring. The signal transmission device according to claim 11, wherein
The third wiring has a first resistance;
The fourth wiring has a second resistance;
The signal transmission device according to claim 5, wherein the fifth wiring has a third resistor. The signal transmission device according to claim 12, wherein
The resistance value of the first resistor is in the range of half to twice the value obtained by subtracting half of the impedance of the first wiring from the impedance value of the third wiring, and the resistance of the second resistance The value is in the range of half to twice the value of the impedance of the fourth wiring minus the value of half of the impedance of the first wiring, and the resistance value of the third resistor is the value of the fifth wiring A signal transmission device characterized by being in a range of half to twice of a value obtained by subtracting half of the impedance of the second wiring from the value of impedance. The signal transmission device according to claim 12, wherein
A signal transmission apparatus, wherein the first input / output circuit receives the third signal in synchronization with a signal obtained by multiplying the signal received by the first receiving circuit by two. The signal transmission device according to claim 14, wherein
A signal transmission device comprising a phase adjustment circuit for converting a phase of a third signal received by a first input / output circuit into a signal that can be controlled in synchronization with the first signal. A first output circuit that outputs a first signal; a second output circuit that outputs a second signal; a first reception circuit that receives a third signal; and a second output circuit that receives a fourth signal. A first circuit block having two receiving circuits;
A third receiving circuit for receiving the first signal; a fourth receiving circuit for receiving the second signal; a third output circuit for outputting a third signal; and outputting the fourth signal. A plurality of second circuit blocks having a fourth output circuit,
A first wiring for transmitting the first signal, the second signal, the third signal, and the fourth signal between the first circuit block and the second circuit block; Each having a wiring, a third wiring, and a fourth wiring;
The first, second, third, and fourth wirings are respectively folded at the position of the second circuit block farthest from the first circuit block, or at a folding position farther than the position, and laid out,
Any one of the second circuit blocks is connected on the wiring from the first circuit block to the folding position of the first wiring and on the wiring to the folding position of the second wiring, and the third wiring is folded. A second circuit block connected on the previous wiring from the position and on the previous wiring from the folding position of the fourth wiring;
On the wiring from the folding position of the first wiring to the previous wiring and from the folding position of the second wiring to the previous wiring, on the wiring from the first circuit block to the folding position of the third wiring And second circuit blocks that are connected to the wiring from the first circuit block to the turn-around position of the fourth wiring,
The fourth receiving circuit latches the second signal in synchronization with the first signal;
The fourth transmission circuit outputs a fourth signal in synchronization with the first signal;
The signal transmission device, wherein the second receiving circuit latches the fourth signal in synchronization with the third signal. The signal transmission device according to claim 15 or 16,
The signal transmission device, wherein the first, second, third, and fourth wirings have termination resistors. The signal transmission device according to any one of claims 15 to 17,
A first branch wiring for transmitting a first signal between the first output circuit and the first wiring; a second branch wiring between the second output circuit and the second wiring; A second branch wiring for transmitting a signal, a third branch wiring for transmitting a third signal between the first receiving circuit and the third wiring, and the second receiving circuit. A fourth branch wiring for transmitting a fourth signal between the fourth wiring and the fourth wiring;
The first branch wiring includes a first resistor,
The second branch wiring includes a second resistor,
The third branch line includes a third resistor;
The signal transmission device, wherein the fourth branch line includes a fourth resistor. The signal transmission device according to claim 18, wherein
The resistance value of the first resistance element is in the range of half to twice the value obtained by subtracting half of the impedance of the first wiring from the impedance value of the first branch wiring, and The resistance value of the second resistance element is in the range of half to twice the value obtained by subtracting half of the impedance of the second wiring from the impedance value of the second branch wiring, and the third resistance The resistance value of the element is in the range of half to twice the value obtained by subtracting half the impedance value of the third wiring line from the impedance value of the third branch wiring line. The signal transmission device according to claim 1, wherein a resistance value is in a range of half to twice a value obtained by subtracting a value of half of the impedance of the third wiring from a value of impedance of the fourth branch wiring. The signal transmission device according to any one of claims 1, 5, 9, and 15,
The first circuit block is a memory controller;
The signal transmission device, wherein the second circuit block is a memory module.

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