JP3758231B2 - Signal recording apparatus and method, and signal reproducing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal recording apparatus and method, and a signal reproducing apparatus and method for preventing copy prevention and unauthorized use.
[0002]
[Prior art]
In recent years, with the increase in capacity and spread of signal recording media such as optical discs, it has become important to prevent illegal copying in order to protect the copyright of recorded signals. That is, in the case of digital audio data or digital video data, a copy without deterioration can be easily generated by copying or dubbing, and in the case of computer data, the same data as the original data can be easily copied. In fact, there are already harmful effects such as copyright infringement due to illegal copying.
[0003]
For this reason, in order to prevent illegal copying, some original signal recording media record predetermined ID bits for preventing illegal copying.
[0004]
For example, as a method for preventing illegal copying in a digital audio signal recording / reproducing apparatus referred to as a so-called R-DAT (Rotary head Digital Audio Taperecoder), a digital audio recorded on a digital audio tape as a signal recording medium is used. In the main data area of the signal, a prohibition code (so-called SCMS: prohibition code of the serial copy management system standard) for prohibiting digital copy and stepwise generation copy (that is, generation limit) is recorded and digitally recorded. When the audio signal recording apparatus detects this prohibition code, a method is adopted in which copy recording of the digital audio signal onto a new digital audio tape is prohibited.
[0005]
In order to prevent illegal copying of, for example, a digital video signal recorded on a signal recording medium, the original digital recording medium is illegally copied in the same manner as the illegal copying prevention method between recording and reproducing apparatuses in the R-DAT. It is conceivable to record a predetermined ID bit (CGMS: prohibited code of copy generation management system standard) for copy prevention.
[0006]
Further, in the case of computer data, the file content itself is encrypted using encryption key information, and the license is granted only to authorized users. In addition, as a form of information distribution, a digital recording medium on which information is encrypted is distributed, a key is obtained for the contents required by the user, key information is obtained, and the encryption is decrypted. It is linked to a system that can be used.
[0007]
[Problems to be solved by the invention]
However, the prohibition code and encryption key information for the conventional signal recording medium as described above are stored in a specific system-specific location accessed by the user on the recording medium, as disclosed in JP-A-5-173891. It is recorded. Note that the prohibition code and encryption key information are also usually encrypted.
[0008]
Thus, if the arrangement of the forbidden code and the encryption key information is fixed at an arbitrary place in each encryption method, there is a possibility that compatibility is lost. Further, if the prohibition code and encryption key information are fixedly arranged, the encryption method is also fixed, and the flexibility and expandability are poor, and the format itself may be shortened.
[0009]
Furthermore, since the encryption key information and the prohibition code are in a location accessible by the user, for example, they are easily subject to decryption or illegal copying by a malicious user.
[0010]
Accordingly, the present invention has been made in view of the above-described circumstances, and an object thereof is to provide a signal recording apparatus and method, and a signal reproducing apparatus and method that make illegal decoding and illegal copying difficult.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problem, a signal recording apparatus according to the present invention includes at least one signal encryption unit that encrypts an input signal in a signal recording apparatus that records an encrypted signal on a signal recording medium. Output means for outputting key storage location information for indicating a location where key information for decrypting the signal encrypted by the at least one signal encryption means is disposed; the encrypted signal; and Recording means for recording the key storage location information on the signal recording medium, When using an address that does not exist on the signal recording medium among the address on the signal recording medium and the address that does not exist on the signal recording medium as the key storage location information, As the key information, information arranged in a place other than the signal recording medium is used.
According to another aspect of the present invention, there is provided a signal recording method for recording an encrypted signal on a signal recording medium, wherein the signal encryption means encrypts an input signal. An encryption step, an output step in which output means outputs key storage location information indicating a location where key information for decrypting the signal encrypted in the signal encryption step is arranged, and the encryption Recording means for recording the recorded signal and the key storage location information on the signal recording medium, and the key storage location information does not exist on the address and the signal recording medium as the key storage location information. When an address that does not exist on the signal recording medium is used, information arranged at a place other than the signal recording medium is used as the key information.
[0012]
The signal reproduction apparatus according to the present invention is a signal reproduction apparatus for reproducing an encrypted signal from a signal recording medium in order to solve the above-described problem, and the encrypted signal and the key storage location from the signal recording medium. Reading means for reading information and specified based on the key storage location information place And extracting means for extracting the key information for decrypting the encryption, and decrypting means for decrypting the encrypted signal using the key information extracted by the extracting means. When an address that does not exist on the signal recording medium among addresses on the signal recording medium and addresses that do not exist on the signal recording medium is used as the key storage location information, information other than the signal recording medium The location is specified It is characterized by that.
Furthermore, a signal reproduction method according to the present invention is a signal reproduction method for reproducing an encrypted signal from a signal recording medium in order to solve the above-described problem, and the encrypted signal and the key storage location from the signal recording medium. A reading process in which information is read by the reading means, and designated based on the key storage location information. place A take-out step in which the take-out means takes out the key information for decrypting the encryption arranged in the above; and a decryption step in which the decryption means decrypts the encryption of the encrypted signal using the key information taken out by the take-out step And have When an address that does not exist on the signal recording medium among addresses on the signal recording medium and addresses that do not exist on the signal recording medium is used as the key storage location information, information other than the signal recording medium The location is specified It is characterized by that.
[0013]
That is, according to the present invention, the key storage location information indicating the location of the key information is recorded on the signal recording medium, and the key information is extracted based on the key storage location information when reproducing the signal. Therefore, key information cannot be easily extracted.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some preferred embodiments according to the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a block diagram schematically showing a configuration example of a signal recording apparatus according to an embodiment of the present invention.
In FIG. 1, the input terminal 11 is supplied with digital data such as data obtained by digitally converting an analog audio signal or video signal, or computer data, for example. This input digital data is sent to the sectoring circuit 13 via the interface circuit 12, and is sectored in units of a predetermined data amount, for example, 2048 bytes.
[0016]
The sectorized data is sent to the scramble processing circuit 14 and scrambled. The scramble process in this case is intended to randomize the input data so that the same byte pattern does not appear continuously, that is, to remove the same pattern, so that the signal can be read and written appropriately. It is a randomization process.
[0017]
The scrambled or randomized data is sent to the header adding circuit 15, header data arranged at the head of each sector is added, and then sent to the error correction coding circuit 16.
[0018]
Next, the error correction coding circuit 16 performs data delay and parity calculation to add parity.
[0019]
In the next modulation circuit 17, for example, 8-bit data is converted into 16-channel bit modulation data according to a predetermined modulation method, and sent to the synchronization adding circuit 18. The synchronization adding circuit 18 adds a synchronization signal of a so-called out-of-rule pattern that breaks the modulation rule of the predetermined modulation method in units of a predetermined data amount, and sends it to the recording head 20 via a drive circuit, that is, a driver 19. Yes.
[0020]
The recording head 20 performs, for example, optical or magneto-optical recording, and records the modulated recording signal on a disk-shaped recording medium 21. The disk-shaped recording medium 21 is rotationally driven by a spindle motor 22.
[0021]
The scramble processing circuit 14 is not essential, and is inserted after the header addition circuit 15 to scramble the digital data to which the header is added and send it to the error correction coding circuit 16. May be.
[0022]
Here, at least one of the sectorization circuit 13, the scramble processing circuit 14, the header addition circuit 15, the error correction coding circuit 16, the modulation circuit 17, and the synchronization addition circuit 18 performs an encryption process on the input. It has the structure which gives and outputs. Preferably, encryption processing is performed by two or more circuits.
[0023]
The key information for this encryption process includes, for example, identification information unique to the medium, destination information (Regional Code) indicating the area to which the medium is shipped, manufacturer identification information, seller identification information, or recording apparatus or encoder specific information. Identification information, identification information unique to a medium manufacturing apparatus such as a cutting machine or stamper, identification information supplied from the outside, and the like can be used at least in part. Encryption processing is performed on input data using the key information by at least one of the circuits 13 to 18, preferably two or more.
[0024]
In this case, which circuit of the circuits 13 to 18 has been subjected to the encryption process is also an option, and is considered a key necessary for obtaining a normal reproduction signal during reproduction. That is, if encryption processing is performed in one circuit, it is necessary to select one of six options. If encryption processing is performed in two circuits, the number of combinations of the two circuits It is necessary to select one of 15 options corresponding to. If there is a possibility that encryption processing is performed in 1 to 6 of the 6 circuits 13 to 18, the options increase further, and it is difficult to find this combination by trial and error, It fully plays the role of cryptography.
[0025]
Furthermore, the key information for encryption is switched at a predetermined timing, for example, a sector cycle. When switching key information at this predetermined timing, information such as whether or not to perform switching, a switching cycle, a switching order of a plurality of key information, and the like can be used as a key. Difficult to solve and difficult to decipher.
[0026]
Further, the key information described above is stored at a position on the medium 101 indicated by encryption key storage location information, which will be described later, or at a position other than on the medium 101. The key storage location information is, for example, information sent from the interface circuit 12 to the terminal 24 via the TOC (Table of contents) generation circuit 23, and information sent directly from the interface circuit 12 to the terminal 25. is there. The key storage location information from these terminals 24 and 25 is recorded in, for example, a TOC area described later of the recording medium 101 or other predetermined position. In the following description, the case where the key storage location information is recorded in the TOC area is taken as an example.
[0027]
Next, the configuration of each circuit 13 to 18 and a specific example of the encryption process will be described.
[0028]
First, in the sectorizing circuit 13, for example, an even / odd byte interleaving process as shown in FIG. 2 is performed. That is, in FIG. 2, the output from the interface circuit 12 in FIG. 1 is sent to a two-output selector switch 31, and one output of this selector switch 31 is sent to the sectorizer 34 via the even-odd interleaver 33. The other output of the changeover switch 31 is sent to the sectorizer 34 as it is. In the sectorizer 34, for example, a unit of 2048 bytes of input data is combined into one sector. The switching operation of the changeover switch 32 of the sectorizing circuit 13 is controlled by a 1-bit control signal as a key. The even-odd interleaver 33 converts one sector of input data in which even-numbered bytes 36a and odd-numbered bytes 36b as shown in A of FIG. 3 are alternately arranged into an even-numbered data section 37a as shown in B of FIG. It distributes and outputs to the odd data part 37b. Further, as shown in FIG. 3C, a predetermined area 39 in one sector is specified by key information, and only the data in this area 39 is distributed to the even data section 39a and the odd data section 39b. Also good. In this case, it is possible to set so that a plurality of specific ways of the area 39 can be selected, and it is possible to further increase the encryption level by further increasing the choices of the key information.
[0029]
Next, as the scramble processing circuit 14, for example, as shown in FIG. 4, a so-called parallel block synchronization type scrambler using a 15-bit shift register can be used. Data from the sectorizing circuit 13 is input to the data input terminal 35 of the scrambler in the order in which the LSB (least significant bit) precedes in time, so-called LSB first. The scrambled 15-bit shift register 14a uses an exclusive OR (ExOR) circuit 14b to generate a generator polynomial x. ¹⁵ Feedback is applied according to + x + 1, and a preset value (or initial value) as shown in FIG. 5 is set in the 15-bit shift register 14a. The preset value selection number in FIG. For example, the preset value is switched in units of sectors in correspondence with the value of the lower 4 bits of the sector address. The output data from the shift register 14a and the input data from the terminal 35 are exclusive ORed by the ExOR circuit 14c, taken out from the terminal 14d, and sent to the header adding circuit 15 in FIG.
[0030]
Here, the generator polynomial and the preset value (initial value) can be changed according to key information such as a predetermined identification number. That is, in order to change the generator polynomial, for example, a configuration as shown in FIG. 6 may be used. In FIG. 6, the output from each bit of the 15-bit shift register 14a is sent to each selected terminal of the change-over switch 14f, and this change-over switch 14f is change-controlled by, for example, 4-bit control data from the control terminal 14g. The output from the changeover switch 14f is sent to the ExOR circuit 14b. By changing the control data of the control terminal 14g having such a configuration, the generator polynomial x ¹⁵ + X ⁿ N of +1 can be changed. In order to change the preset value, for example, each preset value in the preset value table of FIG. 5 is logically operated with each bit value of 16-bit identification information. In this case, the identification information unique to the medium, the manufacturer identification information, the seller identification information, the identification information unique to the recording apparatus or the encoder, the identification information unique to the medium production apparatus, and the like are supplied from the outside. Identification information, combinations of these, and combinations with other information, etc., and the above logical operations include exclusive OR (ExOR), AND (AND), and OR (OR). Shift operations can be used. Note that the configuration for changing the generator polynomial is not limited to the structure of FIG. 6, and the number of stages of the shift register and the number of taps taken out may be arbitrarily changed.
[0031]
Next, the header addition circuit 15 will be described.
First, FIG. 7 shows a specific example of the sector format. One sector has a 4-byte synchronization area 42, a 16-byte header area 43, and a 4-byte error with respect to a 2048-byte user data area 41. A detection code (EDC) region 44 is added. The error detection code in the error detection code area 44 is composed of a 32-bit CRC code generated for the user data area 41 and the header area 43. As an encryption process in the header addition circuit 15, it is possible to apply to the address and CRC of the header for synchronous so-called data sync.
[0032]
As an example of performing encryption processing on sector synchronization, that is, data sync, byte patterns assigned to each byte of the 4-byte synchronization area 42 are represented by “A”, “B”, “C”, When each is represented by “D”, the contents of these 4 bytes are shifted or rotated in byte units using 2-bit key information. That is, by switching to “ABCD” when the 2-bit key is “0”, “BCDA” when “1”, “CDAB” when “2”, “DABC” when “3”, etc. If the keys do not match, the sectors cannot be synchronized and normal playback cannot be performed. As the byte patterns “A” to “D”, for example, ISO646 character codes can be used.
[0033]
In the header area 43, as shown in FIG. 9, a CRC 45, which is a so-called cyclic code, copy information 46 for copy permission / non-permission, copy generation management, and the like, a layer 47 indicating which layer of the multilayer disk, Areas of address 48 and spare 49 are provided. Of these, encryption can be performed by performing bit scrambling on the 32 bits of the address 48, in this case, transposing in bit units. In addition, as a generator polynomial of CRC45, x ¹⁶ + X ¹⁵ + X ² If +1 is used, x in the second and third terms ¹⁵ , X ² Instead of x ¹⁵ It is possible to change 15 bits corresponding to ~ x according to the key. Another example is a logical operation of 16 bits of CRC45 and key information.
[0034]
Note that, as described above, the key information includes medium-specific identification information, manufacturer identification information, seller identification information, recording apparatus, encoder, or medium manufacturing apparatus-specific identification information, and identification information supplied from the outside. Etc., or a combination thereof or a combination with other information can be used.
[0035]
Next, a specific example of the error correction coding circuit 16 is shown in FIG.
In FIG. 10, one frame of error correction coding is made up of 148 bytes or 148 symbols of data, and the digital data from the header addition circuit 15 is grouped every 148 bytes to form C1 as the first encoder. It is supplied to the encoder 52. In the C1 encoder 52, 8-byte P parity is added and sent to the C2 encoder 54, which is the second encoder, via a delay circuit 53 for interleaving. In the C2 encoder 54, a 14-byte Q parity is added, and this Q parity is fed back to the C1 encoder 52 via the delay circuit 55. 170 bytes including P and Q parities from the C1 encoder 52 are extracted, output via the delay circuit 56, the rearrangement circuit 57 having the inverter 57a, and sent to the modulation circuit 17 of FIG.
[0036]
When encryption processing is performed in such an error correction encoding circuit, for example, for each byte of the inverter unit 57a in the rearrangement circuit 57, whether or not an inverter is inserted according to encryption key information is selected. It is mentioned to make it perform. That is, in the reference configuration, the 22-byte P and Q parity is inverted and output by the inverter of the inverter unit 57a of the rearrangement circuit 57, but some of these inverters are eliminated or the C1 data It is possible to put some inverters on the side and invert them for output.
[0037]
When performing such data conversion, the error-correction probability changes depending on the degree of difference from the reference configuration. When the difference is small, the error occurrence probability in the final playback output is slightly higher, whereas the difference When there is a large number of errors, the error correction is not performed as a whole and almost no reproduction is possible. That is, for example, when looking at the C1 encoder, the so-called distance, which is an index indicating error correction capability, is 9, so that error detection and correction can be performed up to 4 bytes, and if there is an erasure pointer, correction up to 8 bytes can be performed. Therefore, if there are five or more differences, the C1 code is always uncorrectable or erroneously corrected. If there are four differences, a subtle situation is indicated in which correction is not possible if an error occurs even with one byte. As the difference decreases to 3, 2, and 1 places, the probability of error correction increases. By using this, when providing audio and video software, it is possible to actively create a playback state that can be played to a certain extent but is not perfect and sometimes disturbed, and only for an overview of the software etc. Can be used for
[0038]
In this case, for example, a method of prescribing about two places where the inverter is changed in advance, a method of randomly selecting the changed place according to the key information, and limiting the minimum number to about two places, and the like are combined. And a method.
[0039]
Furthermore, the position where the inverter is inserted or changed is not limited to the position of the rearrangement circuit 57 in FIG. 10, and other positions such as a front stage or a rear stage of the C1 encoder 52 or these positions may be combined. Different keys may be used for a plurality of positions. In addition to using an inverter, bit addition and various logical operations may be used. In addition, various encryption methods such as conversion using a shift register and conversion by various function operations can be applied, and they can also be used in combination.
[0040]
Here, FIG. 11 shows another specific example of the error correction coding circuit 16 in which an exclusive OR (ExOR) circuit group 61 is inserted at a position subsequent to the inverter unit 57a in the rearrangement circuit 57, and C1 An example is shown in which an ExOR circuit group 66 is also inserted at a position preceding the encoder 52, that is, at the input side.
[0041]
Specifically, the ExOR circuit group 61 has 170 bytes of data taken out from the C1 encoder 52 via the delay circuit 56 and the inverter 57a of the rearrangement circuit 57, that is, information data C1. _{170n + 169} ~ C1 _{170n + 22} And parity data P1 _{170n + 21} ~ P1 _{170n + 14} , Q1 _{170n + 13} ~ Q1 _170n Is converted to data using an exclusive OR (ExOR) circuit, and the ExOR circuit group 66 is 148 bytes of input data B. _148n ~ B _{148n + 147} Is converted using an exclusive OR (ExOR) circuit. The ExOR circuits used in these ExOR circuit groups 61 and 66 take the exclusive OR (ExOR) of 1-byte, that is, 8-bit input data and predetermined 8-bit data indicated by 1-bit control data, respectively. There are 170 such 8-bit ExOR circuits (corresponding to inverter circuits when the predetermined 8-bit data is all 1), 170 in the ExOR circuit group 61, and 148 in the ExOR circuit group 66. Used.
[0042]
In FIG. 11, 170-bit key information is supplied to a terminal 62 and is supplied to each of 170 ExOR circuits in the ExOR circuit group 61 via a so-called D latch circuit 63. In response to the 1-bit encryption control signal supplied to the enable terminal 64, the D latch circuit 63 sends the 170-bit key information from the terminal 62 to the ExOR circuit group 61 as it is, or is all zero, that is, all 170 bits. Whether or not is set to “0” is controlled. Of the 170 ExOR circuits in the ExOR circuit group 61, the ExOR circuit to which “0” is sent from the D latch circuit 63 outputs the data from the inverter unit 57a in the rearrangement circuit 57 as it is, and the D latch circuit The ExOR circuit to which “1” is sent from 63 inverts and outputs the data from the inverter unit 57 a in the rearrangement circuit 57. When all zeros, the data from the inverter unit 57a in the rearrangement circuit 57 is output as it is. The ExOR circuit group 66 is the same as the ExOR circuit group 61 except that the ExOR circuit group 66 has 148 ExOR circuits and the key information is 148 bits. The key information is sent to each of 148 ExOR circuits in the ExOR circuit group 66 via the D latch circuit 68, and the D latch circuit 68 determines whether the key information of 148 bits or all zeros by the encryption control signal of the enable terminal 69. Switching control is performed.
[0043]
In the example of FIG. 11, the ExOR circuit group 61 includes information data C1 as 170-byte data extracted from the C1 encoder 52 via the delay circuit 56 and the inverter unit 57a. _{170n + 169} ~ C1 _{170n + 22} And parity data P1 _{170n + 21} ~ P1 _{170n + 14} , Q1 _{170n + 13} ~ Q1 _170n Data is converted using an exclusive OR (ExOR) circuit, but the parity data is not subjected to data conversion, and the remaining 148 bytes of information data C1 _{170n + 169} ~ C1 _{170n + 22} On the other hand, data conversion corresponding to 148-bit key information may be performed.
[0044]
Of course, in the circuit of FIG. 11, the same effect as in the case of FIG. 10 can be obtained. It is also possible to use only one of the ExOR circuit groups 61 and 66, or to select either one or both as the encryption key.
[0045]
Note that, as described above, the key information includes medium-specific identification information, manufacturer identification information, seller identification information, recording apparatus, encoder, or medium manufacturing apparatus specific identification information, identification information supplied from the outside, and the like. Alternatively, a combination thereof, a combination with other information, or the like can be used.
[0046]
Note that AND, OR, NAND, NOR, an invert circuit group, etc. may be used instead of the ExOR circuit groups 61 and 66 as the data conversion means. In addition to performing a logical operation using 1-bit key information or key data in units of 8 bits, a logical operation may be performed on 8-bit information data using 8-bit key data. A combination of AND, OR, ExOR, NAND, NOR, and an invert circuit may be used for each of the 8 bits corresponding to one word. In this case, for example, 148 × 8-bit key data is used for 148 bytes, that is, 148 × 8-bit data, and AND, OR, ExOR, NAND, NOR, and an invert circuit are used in combination. In this case, the combination itself can also be used as a key. In addition to logical operations, transposition that changes the position of data, replacement that replaces data values, and the like can also be used as the data conversion. In addition, various encryption methods such as conversion using a shift register and conversion by various function operations can be applied, and they can also be used in combination.
[0047]
Next, encryption processing in the modulation circuit 17 of FIG. 1 will be described with reference to FIG. In FIG. 12, the input terminal 71 is supplied with data from the error correction encoding circuit 16 every 8 bits (1 byte), and the input terminal 72 is supplied with 8-bit key information. The 8-bit data is sent to an ExOR circuit 73 as an example of a logical operation circuit, and an exclusive OR is taken. The 8-bit output from the ExOR circuit 73 is sent to a modulator of a predetermined modulation system, for example, an 8-16 conversion circuit 74 and converted into 16 channel bits. An example of the 8-16 modulation system in the 8-16 conversion circuit 74 is a so-called EFM plus modulation system.
[0048]
In the example of FIG. 12, encryption processing using 8-bit key information is performed before data modulation. However, the number of bits of key information is not limited to 8 bits, and in the case of 8-16 modulation. The input / output correspondence of the conversion table may be changed according to the key information. Of course, the above-mentioned identification information unique to the medium can be used as the key information.
[0049]
Next, the synchronization adding circuit 18 will be described.
In the synchronization adding circuit 18, for example, four types of synchronization words S0 to S3 as shown in FIG. 13 are used to synchronize in units of the 8-16 modulation frame. This 8-16 modulation frame (for example, EFM plus frame) is composed of 1360 channel bits which are 85 data symbols, for example, and a sync word of 32 channel bits is added to each 1360 channel bits, and The above four types of synchronization words S0 to S3 are selectively used by structuring corresponding to the C1 code and C2 code and making the synchronization word of the first frame of the C1 code sequence different from the synchronization word of other frames. These synchronization words S0 to S3 have two synchronization patterns a and b, respectively, depending on the state of “1” and “0” of the immediately preceding word, the so-called digital sum or DC value, and the like.
[0050]
Encryption can be performed by changing the selection of the four types of synchronization words S0 to S3 according to the 2-bit key information 75 using, for example, a circuit as shown in FIG. That is, each bit of the 2-bit data 76 designating the four types of synchronization words S0 to S3 and each bit of the 2-bit key information 75 are exclusively ORed by the two ExOR circuits 77 and 78, respectively. The new synchronous word designation data 79 is obtained. As a result, the use of the synchronization word in the frame structure or the use position of various synchronization words in the frame structure is changed, and encryption is performed.
[0051]
Note that the number of types of synchronization words may be further increased, and a method of extracting four types of synchronization words from them may be determined by an encryption key. As the key information, the above-described identification information unique to the medium can be used.
[0052]
Next, FIG. 15 shows a disc-shaped recording medium 101 such as an optical disc as an example of the recording medium. The disc-shaped recording medium 101 has a center hole 102 in the center, and leads from the inner circumference to the outer circumference of the disc-shaped recording medium 101 as a TOC (table of contents) area that is a program management area. A (lead in) area 103, a program area 104 in which program data is recorded, and a program end area, a so-called lead out area 105, are formed. In an audio signal or video signal reproducing optical disc, audio and video data are recorded in the program area 104, and time information and the like of the audio and video data are managed in the lead-in area 103.
[0053]
In the recording medium 101 of FIG. 15, the key storage location information is recorded in the lead-in area 103 as part of the TOC information. During reproduction, the key storage location information is read out, and key information for decrypting the encryption is extracted based on the read key storage location information.
[0054]
The storage location of the key information whose storage location is indicated by the key storage location information will be described later.
[0055]
Next, a reproducing apparatus for reproducing data from the disc-shaped recording medium 101 will be described with reference to FIG.
[0056]
In FIG. 16, the disc-shaped recording medium 101 is rotationally driven by a spindle motor 211, and the recorded content of the recording medium 101 is read by a reproducing head device 212 such as an optical pickup device.
[0057]
The signal read by the reproducing head device 212 is converted into binary digital data by the binarization circuit 213 and sent to the digital signal processing circuit 220. Of the digital data converted to binary by the binarization circuit 213, data read from the TOC area is sent to the TOC decoder 219 for decoding processing, and TOC information obtained by this decoding processing. Is sent to the CPU 224.
[0058]
The CPU 224 extracts the key storage location information from the data from the TOC decoder 219. The CPU 224 extracts the key information based on the key storage location information as described later, and extracts the key information from the plurality of encryption key information storage circuits 222 of the digital signal processing circuit 220. ₁ ~ 222 _N To accumulate.
[0059]
The digital signal processing circuit 220 includes a plurality of decoders 221. ₁ ~ 221 _N And a plurality of encryption key information storage circuits 222 ₁ ~ 222 _N Each decoder 221. ₁ ~ 221 _N The reverse processing corresponding to the configuration from the sectorizing circuit 13 to the synchronization adding circuit 18 in the configuration of FIG. 1 is performed. That is, as described above, when encryption processing using key information is performed on at least one of these circuits 13 to 18, preferably 2 or more, the digital signal processing circuit 220 has the circuits 13 to 13. The encryption key information storage circuit 222 is connected to each of the decoders corresponding to the circuits involved in the encryption process. ₁ ~ 222 _N The encryption is decrypted by using the key information stored in.
[0060]
More specifically, the digital signal processing circuit 220 has a configuration as shown in FIG. ₁ ~ 221 _N The output data from the binarization circuit 213 is supplied to the terminal 113 in FIG. In FIG. 17, the synchronization separation circuit 114 separates the synchronization signal added by the synchronization addition circuit 18 of FIG. The digital signal from the sync separation circuit 114 is sent to the demodulation circuit 115, and the process of demodulating the modulation of the modulation circuit 17 in FIG. 1 is performed. Specifically, the process is such that 16 channel bits are converted into 8-bit data. The digital data from the demodulation circuit 115 is sent to the error correction decoding circuit 116 and subjected to a decoding process as an inverse process of the encoding in the error correction encoding circuit 16 of FIG. Thereafter, the sector decomposition circuit 117 decomposes the data into sectors, and the header separation circuit 118 separates the header of the head portion of each sector. The sector decomposition circuit 117 and the header separation circuit 118 correspond to the sectorization circuit 13 and the header addition circuit 15 shown in FIG. Next, descrambling processing circuit 119 performs descrambling processing as reverse processing of scrambling processing in scrambling processing circuit 14 of FIG. 1, and this output data is output from terminal 120 and output terminal 223 of FIG. Sent to.
[0061]
Here, as described above, when encryption processing is performed by the sectorizing circuit 13 in FIG. 1 at the time of recording, decryption of encryption using key information at the time of encryption by the sector decomposition circuit 117 is performed. In the same manner, the encryption / decryption process in the descrambling process circuit 119 corresponds to the encryption process in the scramble process circuit 14 in FIG. 1, and the encryption process in the header addition circuit 15 in FIG. Corresponding to the process, the encryption / decryption process in the header separation circuit 118 is performed. The encryption / decryption process in the error correction / decoding circuit 116 is corresponded to the encryption process in the error correction encoding circuit 16 in FIG. The encryption / decryption process in the demodulation circuit 115 corresponds to the encryption process in the first modulation circuit 17, and the encryption / decryption process in the synchronization separation circuit 114 corresponds to the encryption process in the synchronization addition circuit 18 in FIG. Each process is performed To have.
[0062]
By the way, as described above, the CPU 224 of the playback device of the present invention obtains the position where the key information is actually stored based on the key storage location information supplied from the TOC decoder 219, and the key storage location information. The key information stored in the location corresponding to is extracted, and the extracted key information is stored in each of the decryptors 221. ₁ ~ 221 _N Encryption key information storage circuit 222 corresponding to ₁ ~ 222 _N And the decryption process is performed using the stored key information.
[0063]
In order to do this, in the present invention, key storage location information KP having a data structure as shown in FIG. ₁ ~ KP _N For each decoder 21 in the digital signal processing circuit 220. ₁ ~ 221 _N Prepared for each key storage location information KP ₁ ~ KP _N Are arranged in the TOC area of the recording medium 101.
[0064]
Here, each key storage location information KP ₁ ~ KP _N As shown in FIG. 18, it consists of sector address information, offset information, byte number information, and attribute information. That is, each of these key storage location information KP ₁ ~ KP _N Is the position indicated by the offset information (the position indicated by the offset information from the first byte) within the sector indicated by the sector address information. Byte) to the byte of the length indicated by the byte count information. As the attribute information, the decoder 221 is used. ₁ ~ 221 _N The presence or absence of use, and other information can be stored.
[0065]
Next, the flow of decryption processing in the playback apparatus of FIG. 16 when the key storage location information table is used will be described below.
[0066]
The playback apparatus in FIG. 16 is configured so that every time the disk-shaped recording medium 101 is replaced, all the decoders 221 are replaced. ₁ ~ 221 _N , Encryption key information storage device 222 ₁ ~ 222 _N Is reset, and all sector addresses of the disk-shaped recording medium 101 are set to an accessible mode.
[0067]
Next, the playback apparatus reads the key storage location information KP from the TOC area of the disc-shaped recording medium 101. ₁ ~ KP _N , And these key storage location information KP ₁ ~ KP _N In each decoder 221 ₁ ~ 221 _N Whether or not the corresponding decoder is used is determined based on the attribute information indicated in the entry. Here, if the decoder is used, read the contents of the sector indicated in the sector address information as the key storage location (the case where a special address is written will be described later), and After reading out the information in the range indicated by the offset information and the byte number information from this sector and extracting the encryption key information, the encryption key information is stored in the encryption key information storage means 222 and set in the decoder 221. Complete the preparations for unencrypting (ie plaintizing). This is applied to all decoders 221. ₁ ~ 221 _N Repeat about.
[0068]
Thereafter, the playback device shifts to the user access area restriction mode.
[0069]
Next, the playback apparatus accepts a user command, reads out user data in response thereto, and decrypts the encryption applied to the user data based on the encryption key information stored in the encryption key information storage unit 222.
[0070]
The key information, its storage location, and key storage location information will be described below.
[0071]
Here, as the sector address indicated by the sector address information, all sectors on the disk-shaped recording medium 101 can be targeted. For example, the sector address information is represented in a 4-byte two's complement format. For example, when the area used in the system such as the TOC area is at (0ffffffffh), the recognition originally written for use in another purpose, for example, for recording the manufacturing history, etc. Information can be designated as encryption key information. For example, when manufacturing history information is recorded in 16 bytes of the 160th byte from the head in the sector of the TOC area, if offset information = 160th byte and byte number information = 16 bytes, The manufacturing history recognition information can be designated.
[0072]
Further, for example, by setting a negative value such as (0fffffff0h) as a sector address and designating encryption key information written in an area inaccessible by the user (in this case, for example, a lead-in area). The encryption key can be hidden from the user.
[0073]
Further, for example, when the disc-shaped recording medium 101 has a plurality of recording layers, the sector address of a recording layer different from the data recording layer on the recording medium 101 decreases from, for example, (7fffffffh). In such a case, by specifying (7fffffffh) as the sector address information, the encryption key information stored in the first sector of the recording layer different from the data recording layer on the recording medium 101 Can be specified.
[0074]
Further, as an example in which a special address is written in the sector address information, a sector address number that does not exist on the disk-shaped recording medium 101, for example, (90000000h) to (0effffffh) is assigned to each of the following information. Thus, various information can be handled as encryption key information with a unified expression of sector addresses.
[0075]
In this case, instead of the configuration in which the key information is read out from the normal sector, another recording format on the medium, for example, information written in a barcode, wobbling, ultraviolet light, or the like, the EEPROM 225 in the apparatus shown in FIG. Identification information unique to the recording / playback device recorded on the device, destination information (Regional Code) indicating the region where the device is shipped, IC card connected to or built in the device, and so-called PCMCIA (Personal Computer Memory Card International Association) ) Or the like stored in the information storage device 226, information supplied from a communication device such as a modem / LAN via the communication interface 227, or an external device received by the remote control receiving means 229 from the keyboard 228 or the remote control transmission device 232 The information supplied from is taken out as identification information.
[0076]
Here, for example, when the key storage location information is read, for example, the information stored in the barcode BC recorded on the disk surface of the disk-shaped recording medium 101 is used as the key information, and the special sector address (90000000h) As specified in the sector address information, the barcode reading device 210 provided independently of the normal reading device is operated, and the information from the reading device 210 is decoded by the barcode decoding device 233, If the decrypted information is sent to the CPU 224, the key information can be set in the decryptor as described above.
[0077]
When a device such as the keyboard 228, the remote control transmission device 232, or the remote control reception means 229 that inputs interactively with a person is designated as the encryption key storage location, the display circuit 230 built in or connected to the device. In addition, a process of prompting the person who operates the apparatus to input an encryption key using the display device 231 or the like is required before the key information reading process.
[0078]
When such a special sector address is used, offset information and byte count information in the key storage location information are given their own information and device-specific meanings to absorb differences between devices. be able to. For example, when designation is made such that encryption key information is read from a modem, an example in which offset information is used to designate a telephone number of a distribution company of encryption key information can be considered.
[0079]
In addition, as another example of decryption using encryption key information, when there is a decoder A that can be decrypted in units of sectors and a decoder B that can be decrypted in units of media, for example, the decoder in units of sectors After the encryption key is read out at A, the operation of setting the encryption key in the decoder A is performed before the operation of extracting the encryption key of the decoder B, thereby further improving the concealment of the encryption key of the decoder B. be able to.
[0080]
In the above description, an example is given in which a plurality of encryption processes are performed in the recording apparatus, and a plurality of decryptors are provided in the playback apparatus corresponding thereto, but the present invention basically has one encryption process. Needless to say, the present invention can be applied even if one decoder corresponding to that is provided.
[0081]
As described above, according to the above configuration example of the present invention, the arrangement location of the encryption key information is prepared according to the decoder of the device (if necessary, a plurality is prepared), and the pointers (keys) indicating the arrangement locations are respectively provided. Recording location information) on the medium makes it possible to flexibly specify the location of the encryption key information at an arbitrary position on the medium. For example, the encryption key information can be specified by specifying a location inaccessible to the user. Concealment can be improved. Also, by specifying any recognition information already specified in the physical format, or by specifying physical characteristics of the medium (for example, another recording layer of a medium having a plurality of recording surfaces), the deterrent against illegal duplication And a plurality of encryption keys can be grouped in one sector, so that a large number of encryption keys can be accessed at high speed.
[0082]
The key information indicated by the key storage location information can specify not only the data area read by the normal reading means on the medium but also information recorded on the medium by another recording method. Furthermore, since the key information pointed to by the key storage location information can specify not only the medium but also the logical device attached to the recording / reproducing apparatus, the internal information (such as the identification number) of the recording / reproducing apparatus can be designated, It can also support the input of encryption keys.
[0083]
In addition, the combination of key information can be changed for each master of the medium. Therefore, by making use of the characteristics of each decoder in the playback device, only a part of the key information is used. Can be done easily.
[0084]
Needless to say, this arrangement method can also be applied to the arrangement of key information in a general encryption method.
[0085]
Next, encryption / decryption processing in each component of FIG. 17 will be described.
[0086]
First, as described with reference to FIGS. 13 and 14, the encryption / decryption processing in the synchronization separation circuit 114 in FIG. 17 uses a plurality of types, for example, four types of synchronization words, or various synchronization words in the frame structure. This is performed by detecting the use position changed according to the key information and the encryption performed according to the key information.
[0087]
Next, as shown in FIG. 19, the encryption / decryption processing in the demodulating circuit 115 is a process in which 16 channel bits sent from the synchronization separation circuit 114 to the 16-8 conversion circuit 131 are converted into 8-bit data. 12 is sent to the ExOR circuit 132 corresponding to the ExOR circuit 73 shown in FIG. 12 and exclusive-ORed with the 8-bit key information from the terminal 133, so that the 8-bit data supplied to the input terminal 71 in FIG. Corresponding data is restored and sent to the error correction decoding circuit 116.
[0088]
Next, in the error correction decoding circuit 116, for example, the reverse process of the error correction encoding process of FIG. 10 is performed by the configuration of FIG.
[0089]
In FIG. 20, 170 bytes or 170 symbols of data demodulated by the demodulating circuit 115 are grouped as a unit, through a rearrangement circuit 142 having an inverter unit 172a, and through a delay circuit 143 by a first decoder. It is sent to a certain C1 decoder 144. Of the 170 bytes of data supplied to the C1 decoder 144, 22 bytes are P and Q parity, and the C1 decoder 144 performs error correction decoding using these parity data. From the C1 decoder 144, 170-byte data is output and sent to the C2 decoder 146, which is the second decoder, via the delay circuit 145. After error correction decoding using parity data is performed, Further, it is sent to a C3 decoder 148 as a third decoder via a delay circuit 147. Here, the delay circuit 147 and the C3 decoder 148 are the same as the delay circuit 143 and the C1 decoder 144, and a plurality of sets of the delay circuit and the C1 decoder may be provided. The C3 decoder 148 performs final error correction decoding, and 148-byte data without parity is extracted. The 148-byte data corresponds to the 148-byte data input to the C1 encoder 52 shown in FIG.
[0090]
When the inverter 57a in the rearrangement circuit 57 of the error correction encoding circuit of FIG. 10 performs encryption based on the presence or absence of an inverter, the rearrangement circuit 142 of the error correction decoding circuit of FIG. It is necessary to perform corresponding encryption / decryption in the inverter unit 142a. In addition, corresponding to the various encryption processes described with reference to FIG. 10, it is needless to say that encryption / decryption, which is an inverse process for decrypting the encryption, is required.
[0091]
Here, FIG. 21 is a diagram showing a specific configuration of the error correction decoding circuit corresponding to the specific configuration of the error correction encoding circuit of FIG.
[0092]
In FIG. 21, the input side of the inverter unit 142a of the rearrangement circuit 142 and the delay circuit 143 correspond to the ExOR circuit group 61 inserted on the output side of the inverter unit 57a in the rearrangement circuit 57 of FIG. An ExOR circuit group 151 is inserted at a position on the input side, and an ExOR circuit group 156 is inserted on the output side of the C3 decoder 148 corresponding to the ExOR circuit group 66 inserted on the input side of the C1 encoder 52 in FIG. ing.
[0093]
As described above, these ExOR circuit groups 151 and 156 perform data conversion for decoding data conversion by the ExOR circuit groups 61 and 66 in FIG. 11, respectively. The ExOR circuit group 151 is, for example, 170. Each of the 8-bit ExOR circuits and the ExOR circuit group 156 includes 148 8-bit ExOR circuits. If the ExOR circuit group 61 of the error correction encoding circuit in FIG. 11 on the recording side performs data conversion according to key information on 148-byte information data excluding parity data, the ExOR circuit Of course, the group 151 includes 148 8-bit ExOR circuits.
[0094]
The terminal 152 in FIG. 21 is supplied with 170-bit key information corresponding to the key information supplied to the terminal 62 in FIG. 11, and each of the 170 pieces in the ExOR circuit group 151 via a so-called D latch circuit 153. It is supplied to each ExOR circuit. In response to the 1-bit encryption control signal supplied to the enable terminal 154, the D latch circuit 153 sends the 170-bit key information from the terminal 152 to the ExOR circuit group 151 as it is or all zeros, that is, all 170 bits. Whether or not is set to “0” is controlled. Further, the ExOR circuit group 156 has the 148 ExOR circuits, and the ExOR circuit group 151 is the same as the ExOR circuit group 151 except that the key information is 148 bits similar to the key information supplied to the terminal 67 in FIG. The 148-bit key information supplied to the terminal 157 is sent to the 148 ExOR circuits in the ExOR circuit group 156 via the D latch circuit 158, and the D latch circuit 158 is connected to the enable terminal 159. Switching control is performed to determine whether the 148-bit key information or all zeros is set by the encryption control signal.
[0095]
In this way, simple and large encryption can be realized by using an inverter of an error correction circuit, an ExOR circuit, or the like as an encryption key. In addition, by controlling the number of inverters, etc., it is possible to respond to security level requirements, such as encryption level data that cannot be absolutely reproduced or data that cannot be reproduced when an error state deteriorates. In other words, by controlling the number of inverters, ExOR circuits, etc., it is possible to control the playback so that it can be played back when the error condition is good, and cannot be played back when it becomes bad. Possible states can also be formed. Further, as the encryption key, the number of bits is as large as several hundreds of bits per place as in the example shown in the figure, and encryption with a large number of bits of the key can be performed, so that data security is improved. Moreover, by implementing such an error correction coding circuit and error correction decoding circuit in the hardware of so-called LSIs and IC chips, it is difficult for general users to access, and in this respect data security is also high. It has become a thing.
[0096]
Next, in the sector decomposition circuit 117, as described with reference to FIGS. 2 and 3, this even-odd interleaving is performed when the sectoring circuit 13 performs encryption by even-numbered and odd-numbered interleaving during recording. The reverse process of solving the above, so-called deinterleave process is performed.
[0097]
Further, in the header separation circuit 118, at the time of recording, the header addition circuit 15 performs encryption processing as described with reference to FIGS. 7 to 9, that is, transposition of a byte pattern of a data sync for sector synchronization, an address, When the CRC is changed, an encryption / decryption process is performed to restore the CRC.
[0098]
Next, FIG. 22 shows a specific example of the descrambling circuit 119, and digital data from the header separation circuit 118 of FIG. 17 is supplied to the terminal 161. The digital data from the terminal 161 is descrambled by, for example, the scrambler 163 having the configuration shown in FIG. The generator polynomial 165 and the preset value (or initial value) 166 described with reference to FIG. 4 for the scrambler 163 are changed in accordance with the encryption key information from the authentication mechanism 171 to perform encryption / decryption. It can be carried out. In this authentication mechanism 171, the contents of the copy information 46 of the header information 167, the medium-specific or playback apparatus-specific unique identification information 172, the common identification information 173 of the manufacturer, the seller, etc., and the externally given external Encryption key information is generated based on the identification information 174 and the like, and the generation polynomial 165 and the preset value 166 are controlled according to the key information.
[0099]
As described above, information indicating which of these circuits 114 to 119 requires encryption / decryption processing also becomes encryption key information. Also, encryption key information can be switched at a predetermined cycle, for example, a sector cycle, and whether or not to perform this switching, and the switching cycle, etc. are also used as keys, thereby increasing the difficulty of encryption.
[0100]
Next, a second embodiment of the present invention will be described.
The second embodiment is a partial modification of the configuration of the first embodiment described above, and the overall basic configuration is as shown in FIG. 1 described above. Changes in each of the circuits 13 to 18 having the configuration shown in FIG. 1 will be described below.
[0101]
The sectorizing circuit 13 in FIG. 1 may be configured in the same manner as in the first embodiment described above, but the configuration shown in FIG. 23 is used for the scramble processing circuit 14.
[0102]
In the scramble processing circuit 14 shown in FIG. 23, the data input terminal 35 receives data from the sectorizing circuit 13 in FIG. 1 in the order in which the LSB (least significant bit) precedes in time, so-called LSB first. Is entered. The scrambled 15-bit shift register 14a uses an exclusive OR (ExOR) circuit 14b to generate a generator polynomial x. ¹⁵ + X ^Four The feedback according to +1 is applied, and a preset value (or initial value) as shown in FIG. 24 is set in the 15-bit shift register 14a. The preset value selection number in FIG. For example, the preset value is switched in units of sectors in correspondence with the value of the lower 4 bits of the sector address. The output data from the shift register 14a and the input data from the terminal 35 are exclusive ORed by the ExOR circuit 14c, taken out from the terminal 14d, and sent to the header adding circuit 15 in FIG.
[0103]
Here, the preset value (initial value) can be changed according to key information such as a predetermined identification number. That is, each preset value in the preset value table of FIG. 24 is logically calculated with each byte value of 16-byte identification information, for example. In this case, the identification information unique to the medium, the manufacturer identification information, the seller identification information, the identification information unique to the recording apparatus or the encoder, the identification information unique to the medium production apparatus, and the like are supplied from the outside. Identification information, etc., or combinations of these and other information, etc., and the above logical operations include exclusive OR (ExOR), logical product (AND), logical OR (OR) Shift operations can be used.
[0104]
Next, for example, the sector format shown in FIG. 25 is used as the sector format of the second embodiment.
[0105]
As shown in FIG. 25, one sector is composed of 12 rows of 172 bytes, that is, 2064 bytes, and includes 2048 bytes of main data. At the head position of the first row of 12 rows, a 4-byte ID (identification data), a 2-byte IED (ID error detection code), and a 6-byte RSV (reserved) are arranged in this order. A 4-byte EDC (error detection code) is arranged at the end position of the last row.
[0106]
As shown in FIG. 26, the 4 bytes of the ID (identification data) are the first byte (bits b31 to b24) on the MSB side made up of sector information, and the remaining 3 bytes (bits b23 to b0) from the sector number. It is made up. Sector information consists of information of 1-bit sector format type, 1-bit tracking method, 1-bit reflectivity, 1-bit reserve, 2-bit area type, and 2-bit layer number in order from the MSB side. Yes.
[0107]
In the header addition circuit 15 of FIG. 1, in such a sector format, for example, the 24 bits of the sector number in the ID (identification data) are scrambled in units of bits, for example, according to the key information. Encryption can be performed by performing transposition processing. The 2-byte IED (ID error detection code) generator polynomial, 4-byte EDC (error detection code) generator polynomial, etc. may be changed according to the key information, or the information and the key may be changed. Encryption can also be performed by performing a logical operation on information.
[0108]
Next, as the error correction encoding circuit 16 of FIG. 1, a circuit having a configuration as shown in FIG. 27 is used. For this encoding, a product code or a block code as shown in FIG. 28 is used.
In FIG. 27, data from the header adding circuit 15 in FIG. 1 is supplied to an input terminal 310, and this input data is sent to a PO encoder 311 which is a first encoder. As shown in FIG. 28, the input data to this PO encoder 311 is B _0,0 ~ B _191,171 172 bytes × 192 rows of data. In the PO encoder 311, each of 172 columns of 192 bytes of data has a 16-byte Reed-Solomon (RS) code of RS (208, 192, 17). An outer code (PO) is added. The output data from the PO encoder 311 is sent to the interleave circuit 313 via the data conversion circuit 312 for encryption as described above, subjected to interleave processing, and sent to the PI encoder 314. In this PI encoder 314, as shown in FIG. 28, 10 bytes each of RS (182, 172, 11) for 172 bytes of data of 172 bytes × 208 rows of data to which the PO parity is added. An inner code (PI) is added. Therefore, 182 bytes × 208 rows of data are output from the PI encoder 314. This output data is taken out from the output terminal 316 via the data conversion circuit 315 for encryption as described above.
[0109]
Here, for the data conversion circuit 312, since the PO encoder 311 adds 16-byte PO parity to the 192-byte input data for each column and outputs 208-byte data, the 16-byte parity is output. On the other hand, or the entire 208-byte data can be encrypted by performing the data conversion as described above. As described above, this data conversion may be performed according to the input key information. Also, for the data conversion circuit 315, the PI encoder 314 adds 10 bytes of PI parity to the 172 bytes of data in each row and outputs 182 bytes of data. On the other hand, encryption can be performed by performing data conversion on the entire data of 182 bytes.
[0110]
Specifically, in the data conversion, as described with reference to FIGS. 10 and 11, an inverter is disposed at a predetermined position, or data is selectively inverted according to key information by an ExOR circuit group. In addition, an AND, OR, NAND, NOR circuit group or the like may be used. In addition to performing a logical operation using 1-bit key information or key data in units of 8 bits, a logical operation may be performed on 8-bit information data using 8-bit key data. A combination of AND, OR, ExOR, NAND, NOR, and an invert circuit may be used for each of the 8 bits corresponding to one word. Further, when AND, OR, ExOR, NAND, NOR, and an invert circuit are used in combination, these combinations themselves can be used as a key. In addition to logical operations, transposition that changes the position of data, replacement that replaces data values, and the like can also be used as the data conversion. In addition, various encryption methods such as conversion using a shift register and conversion by various function operations can be applied, and they can also be used in combination.
[0111]
The 182 bytes × 208 rows of data subjected to error correction coding are interleaved with respect to rows, divided into 16 groups of 13 rows, and each group is associated with a recording sector. One sector has 2366 bytes of 182 bytes × 13 rows. These are modulated, and two synchronization codes SY are added per row as shown in FIG. For modulation, 8-16 conversion is used as in the first embodiment described above, but one row is divided into two sync frames, and one sync frame includes a sync code SY of 32 channel bits and 1456 channels. It consists of a bit data part. FIG. 29 shows a structure for one sector obtained by modulation and synchronization addition, and 38688 channel bits for one sector shown in FIG. 29 correspond to 2418 bytes before modulation.
[0112]
29, eight types of synchronization codes SY0 to SY7 are used, and these synchronization codes SY0 to SY7 are in states 1 and 2 in accordance with the state of the 8-16 conversion (state). 30 is the synchronization pattern of FIG. 30A, and states 3 and 4 are the synchronization pattern of FIG. 30B.
[0113]
Encryption can be performed by changing the selection of these eight types of synchronization codes SY0 to SY7 according to 3-bit key information using, for example, a circuit as shown in FIG. In other words, each bit of the 3-bit data 321 designating the above eight types of synchronization codes SY0 to SY7 and each bit of the 3-bit key information 322 are obtained by exclusive logic by the three ExOR circuits 323, 324, and 325, respectively. By taking the sum, new synchronization code designation data 326 is obtained. As a result, the use of the synchronization code in the frame structure or the use position of various synchronization codes in the frame structure is changed, and encryption is performed. Of course, data can be transposed, replaced, or converted by a shift register according to the key information for the 3 bits. This may also be function conversion.
[0114]
The effects of the second embodiment of the present invention described above are the same as those of the first embodiment described above.
[0115]
Next, the basic configuration on the playback side is the same as that in FIG. 17 as compared with the configuration on the recording side in the second embodiment of the present invention described above. The reverse processing changed corresponding to the changed part is performed. For example, the reverse processing for the error correction coding shown in FIG. 27 can be realized by an error correction decoding circuit having a configuration as shown in FIG.
[0116]
That is, in FIG. 32, the input terminal 330 is an output signal from the demodulating circuit 115 in FIG. 17 and corresponds to the output from the output terminal 316 in FIG. Row data is supplied. The data from the input terminal 330 is sent to the data reverse conversion circuit 331, and the reverse processing of the data conversion circuit 315 in FIG. 27 is performed. The output data from the data inverse conversion circuit 331 is sent to the PI (inner code) decoder 332, and is subjected to a decoding process as an inverse process of the PI encoder 314 in FIG. 27, that is, an error correction process using the PI code. The data of 172 bytes × 208 rows in FIG. The output data from the PI decoder 332 is subjected to reverse processing in the interleave circuit 313 in the deinterleave circuit 333, sent to the data reverse conversion circuit 334, and reverse processing in the data conversion circuit 312 in FIG. Thereafter, it is sent to a PO (outer code) decoder 335. In the PO decoder 335, the decoding process as an inverse process of the PO encoder 311 in FIG. 27, that is, the error correction process using the PO code, is performed, and the original 172 bytes × 192 rows of data in FIG. Is taken out through. When the key information is used in the data conversion in the data conversion circuits 312 and 315 in FIG. 27, the key information supplied to the terminals 318 and 319 is used as the data in the data inverse conversion circuits 334 and 331 in FIG. The data may be supplied to terminals 339 and 338, respectively, and reverse data conversion may be performed according to the key information.
[0117]
The effects of the second embodiment of the present invention described above are the same as those of the first embodiment described above.
[0118]
Note that the present invention is not limited only to the above-described embodiments. For example, as data conversion, an example of an inverter or ExOR is shown, but other than this, bit addition, various logical operations, etc. Of course, data conversion may be performed. In addition, of course, various encryption methods can be applied, such as replacing data according to encryption key information, transposing, converting using a shift register, converting by various function operations, etc. It is also possible to use them in combination. In addition, various modifications can be made without departing from the scope of the present invention.
[0119]
【The invention's effect】
In the present invention, the key storage location information indicating the location of the key information is recorded on the signal recording medium, and the key information is extracted based on the key storage location information at the time of signal reproduction. Since information is not easily extracted, illegal decoding and illegal copying can be prevented.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a configuration example of a signal recording apparatus of the present invention.
FIG. 2 is a block circuit diagram showing a configuration example for realizing even / odd byte interleaving in a sectorization circuit;
FIG. 3 is a diagram for explaining interleaving of even and odd bytes.
FIG. 4 is a circuit diagram showing an example of a scrambler.
FIG. 5 is a diagram illustrating preset values of a scrambler.
FIG. 6 is a diagram illustrating an example of a scrambler having a variable generator polynomial.
FIG. 7 is a diagram illustrating an example of a sector format.
FIG. 8 is a diagram for explaining an example of encryption in a synchronous area in a sector.
FIG. 9 is a diagram illustrating an example of a header area in a sector.
FIG. 10 is a diagram illustrating an example of an error correction coding circuit.
FIG. 11 is a diagram illustrating another example of an error correction coding circuit.
FIG. 12 is a diagram for explaining an example of encryption processing in a modulation circuit;
FIG. 13 is a diagram illustrating a specific example of a synchronization word added to a modulation signal.
FIG. 14 is a diagram for explaining an example of encryption in a synchronization adding circuit.
FIG. 15 is a diagram illustrating an example of a data recording medium.
FIG. 16 is a block circuit diagram showing a configuration example of a signal reproduction device of the present invention.
FIG. 17 is a block circuit diagram showing a specific configuration of a digital signal processing circuit of the signal reproduction device.
FIG. 18 is a diagram for explaining a key storage location information table.
FIG. 19 is a diagram for explaining an example of an encryption process in a demodulation circuit.
FIG. 20 is a diagram illustrating an example of an error correction decoding circuit.
FIG. 21 is a diagram illustrating another example of an error correction decoding circuit.
FIG. 22 is a diagram illustrating an example of a descrambling processing circuit.
FIG. 23 is a diagram illustrating another example of a scrambler.
FIG. 24 is a diagram showing an example of preset values of the scrambler of FIG.
FIG. 25 is a diagram illustrating another example of the sector format.
26 is a diagram showing an example of a header area in a sector in the sector format of FIG.
FIG. 27 is a block diagram illustrating another example of an error correction coding circuit.
FIG. 28 is a diagram illustrating a product code as a specific example of an error correction code.
FIG. 29 is a diagram illustrating an example of a signal format of a sector.
FIG. 30 is a diagram illustrating another specific example of the synchronization word added to the modulation signal.
FIG. 31 is a diagram for explaining another example of encryption in the synchronization adding circuit.
FIG. 32 is a block diagram illustrating another example of the error correction decoding circuit.
[Explanation of symbols]
13 sectorization circuit, 14 scramble processing circuit, 15 header addition circuit, 16 error correction coding circuit, 17 modulation circuit, 18 synchronization addition circuit, 57, 142 rearrangement circuit, 61, 66, 151, 156 ExOR circuit group, 114 Sync separation circuit, 115 demodulation circuit, 116 error correction decoding circuit, 117 sector decomposition circuit, 118 header separation circuit, 119 descrambling processing circuit, 220 digital signal processing circuit, 221 ₁ ~ 221 _N Decoder 222 ₁ ~ 222 _N Cryptographic key information storage circuit, 224 CPU

Claims (6)

In a signal recording apparatus for recording an encrypted signal on a signal recording medium,
At least one signal encryption means for encrypting the input signal;
Output means for outputting key storage location information indicating a location where key information for decrypting the signal encrypted in the at least one signal encryption means is disposed;
Recording means for recording the encrypted signal and the key storage location information on the signal recording medium;
When the address that does not exist on the signal recording medium among the address on the signal recording medium and the address that does not exist on the signal recording medium is used as the key storage location information , the signal recording A signal recording apparatus using information arranged in a place other than a medium. Key information encryption means for encrypting the key information;
Storage information instruction information output means for outputting storage information instruction information indicating the location where the key information for decrypting the key information encrypted by the key information encryption means is disposed,
2. The signal recording apparatus according to claim 1, wherein the recording unit records the encrypted signal, the key storage location information, and the storage information instruction information on the signal recording medium. A signal reproducing device for reproducing an encrypted signal from a signal recording medium,
Reading means for reading the encrypted signal and key storage location information from the signal recording medium;
Extraction means for extracting key information for decrypting the encryption arranged at a location specified based on the key storage location information;
Using the key information extracted by said extraction means, have a decoding means for solving the encryption of the encrypted signal,
As the key storage location information, when an address that does not exist on the signal recording medium out of an address on the signal recording medium and an address that does not exist on the signal recording medium is used, the location other than the signal recording medium is A signal reproducing apparatus characterized by being specified .   4. The signal reproducing apparatus according to claim 3, wherein the key information is encrypted, and the reading unit also reads information indicating a location where the key information for encryption of the key information is arranged. In a signal recording method for recording an encrypted signal on a signal recording medium,
A signal encryption step in which the signal encryption means encrypts the input signal;
An output step in which the output means outputs key storage location information indicating the location where the key information for decrypting the signal encrypted in the signal encryption step is disposed;
A recording step in which the recording means records the encrypted signal and the key storage location information on the signal recording medium;
When the address that does not exist on the signal recording medium among the address on the signal recording medium and the address that does not exist on the signal recording medium is used as the key storage location information , the signal recording A signal recording method using information arranged at a place other than a medium. A signal reproduction method for reproducing an encrypted signal from a signal recording medium,
A reading step in which the reading means reads the encrypted signal and the key storage location information from the signal recording medium;
A retrieval step in which the retrieval means retrieves the key information for decrypting the encryption arranged at the location designated based on the key storage location information;
Using the key information extracted by the extraction step, the decoding means have a decoding step of solving the encryption of the encrypted signal,
As the key storage location information, when an address that does not exist on the signal recording medium out of an address on the signal recording medium and an address that does not exist on the signal recording medium is used , the location other than the signal recording medium is A signal reproduction method characterized by being specified .

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