JP3758437B2 - DMA controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a direct memory access control (hereinafter referred to as “DMA control”) device that achieves low power consumption. More specifically, the present invention relates to a DMA control device that reduces the power consumption by controlling the operation mode of a memory in accordance with the usage ratio of a shared bus by a plurality of devices connected to the shared bus. For example, it is suitable for a device such as a copying machine that shares a bus between a CPU and other devices (scanner, printer, etc.).
[0002]
[Prior art]
A conventional DMA control apparatus is known that includes a bus arbitration unit for arbitrating bus access when there is a request for bus access from a plurality of devices. As an example of the system, an image forming apparatus system in a digital copying machine is shown in FIG. The system shown in FIG. 11 basically includes a memory 107, each of the DMA control units 101, 102, 103, and an access control unit 104. The DMA control units 101 to 103 and the access control unit 104 are shared. Data is transferred by accessing the memory 107 via the bus 105.
[0003]
A memory controller 109 that controls access to the memory 107 is provided between the bus 105 and the memory 107. Further, a bus arbitration unit 106 that arbitrates access from the DMA control units 101 to 103 and the access control unit 104 to the bus 105 is provided. A printer device 111 is connected to the DMA control unit 101, a scanner device 112 is connected to the DMA control unit 102, and a CPU 114 is connected to the access control unit 104.
[0004]
This system operates as follows. This operation will be described with reference to FIG. For example, when the DMA control unit 101 needs to access the bus 105, the DMA control unit 101 outputs a request signal req 1 to the bus arbitration unit 106. In response to the request signal req1, the bus arbitration unit 106 returns a bus use permission signal ack1 if possible. During the period in which the permission signal ack1 is active, the printer apparatus 111 can access the bus 105 via the DMA control unit 101. The same applies to other DMA control units (devices). When each DMA control unit accesses the bus 105, a memory access request is issued from the bus 105 to the memory controller unit 109. Based on this memory access request, the memory controller unit 109 controls access to the memory 107 by each DMA control unit.
[0005]
When there are requests from a plurality of control units simultaneously, the bus arbitration unit 106 returns a bus use permission signal in accordance with a predetermined priority. An example of the priority order is shown in FIG. In the case of this priority, when the request signals req1, req2, req3, and req4 are simultaneously output to the bus arbitration unit 106, the bus arbitration unit 106 returns only the bus use permission signal ack1 having the highest priority. Thereby, the DMA control unit 101 accesses the bus 105 with priority over the other control units 102 to 104. Similarly, when the request signals req2, req3, and req4 are output simultaneously, the bus arbitration unit 106 returns only the bus use permission signal ack2 having the highest priority among them. For this reason, the DMA control unit 102 accesses the bus 105 with priority over the other control units 103 and 104.
[0006]
Here, a DRAM is used for the memory 107. This is because an image forming apparatus such as a digital copying machine requires a large capacity memory. However, DRAM has the advantage of large storage capacity, but has the disadvantage of high power consumption. For this reason, when the memory 107 is not used, the power consumption of the system is reduced by shifting the operation mode to the low power consumption mode.
[0007]
[Problems to be solved by the invention]
However, the conventional DMA control device 100 described above has a problem that the operation mode cannot be finely controlled for each block (area) of the memory 107. For this reason, the power consumption could not be effectively suppressed low. In order to solve this problem, the operation mode may be controlled for each block of the memory 107. However, in order to do so, it is necessary for the CPU 114 to grasp the status of access to the memory 107 by each control unit. And in order to implement | achieve such control, there existed a problem that very complicated control had to be performed in CPU114.
[0008]
Accordingly, the present invention has been made to solve the above-described problems, and grasps the bus usage ratio and access status by a plurality of devices without performing complicated control, and accordingly, for each block of the memory. It is an object of the present invention to provide a DMA control device capable of controlling an operation mode.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, according to the DMA control device of the present invention, a CPU, a memory including a plurality of memory blocks, a shared bus connected to the memory, and the memory connected to the shared bus and the memory A plurality of devices accessing the memory, and memory controller means for controlling access to the memory by each device; Occupancy rate calculating means for calculating the usage rate of the shared bus every predetermined time, and access detecting means for detecting the access status to the shared bus for each device And the memory controller means comprises: Based on the calculation result of the occupancy rate calculation means and the detection result of the access detection means, for each memory block Control the operating mode.
[0010]
In this DMA controller, The occupancy rate calculation means calculates the usage ratio of the shared bus as a whole device every predetermined time. The access detection means detects the access status to the shared bus for each device. And by the memory controller means, Based on the calculation result of the occupancy rate calculation means and the detection result of the access detection means, for each memory block The operation mode is controlled. In other words, the memory controller means each memory block according to the operation status of each memory block. Every The operation mode is controlled. Thereby, an operation mode suitable for the information processing speed required for each memory block is selected. Therefore, when high-speed processing is not necessary, the power consumption can be effectively reduced by shifting to the low power consumption mode.
[0011]
In the DMA control device according to the present invention, each memory block is a storage means that can be written and read at any time, and the memory controller means can select one of a normal mode, a power-down mode, and a self-refresh mode as the operation mode of the storage means. It is preferable to select the mode.
[0012]
When the device is hardly operated, data is not frequently written or read in the memory block corresponding to the device. For this reason, even in such a case, operating the memory block in the normal mode consumes power wastefully. For this reason, in this DMA control device, the operation mode of the storage means is switched from the normal mode to the power-down mode or the self-refresh mode by the memory controller means in accordance with the shared bus usage ratio calculated by the bus monitor means. That is, when the device is hardly operated, the operation mode of the storage means corresponding to the device is the power down mode or the self refresh mode. Since these modes consume significantly less power (about 1/50) than the normal mode, the power consumption of the storage means can be effectively reduced.
[0013]
Note that both the power down mode and the self refresh mode are low power consumption modes, and each mode is shifted by a command input. A command input is also required to return from the power-down mode or the self-refresh mode to the normal mode.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying a DMA control device of the present invention will be described below in detail with reference to the drawings. This embodiment is a DMA control device that controls access of each device to a bus in a copying machine.
[0015]
As shown in FIG. 1, the DMA control device 10 includes a memory 7 having memory blocks (DRAMs) 71 to 74 (see FIG. 2), which will be described later, the DMA controllers 1, 2, 3, and the access controller 4. The DMA controllers 1 to 3 and the access controller 4 access the memory 7 via the shared bus 5. Then, each of the DMA control units 1 to 3 and the bus arbitration unit 6 that arbitrates access to the bus 5 from the access control unit 4, a bus monitor unit 8 that calculates the usage rate of the bus 5, and calculation of the bus monitor unit 8 A memory controller unit 9 is provided for controlling the operation mode of each memory block provided in the memory 7 according to the result.
[0016]
Further, a printer device 11 is connected to the DMA control unit 1, a scanner device 12 is connected to the DMA control unit 2, and a CPU 14 is connected to the access control unit 4. The CPU 14 controls the entire copying machine including this system. The printer device 11 and the scanner device 12 can directly access the memory 7 by the DMA control units 1 and 2 without using the CPU 14.
[0017]
As shown in FIG. 2, the memory 7 includes four memory blocks 71 to 74. Each of the memory blocks 71 to 74 corresponds to each of the DMA control units 1 to 3 and the access control unit 4. Specifically, the DMA control unit 1 accesses the memory block 71, the DMA control unit 2 accesses the memory block 72, the DMA control unit 3 accesses the memory block 73, The access control unit 4 accesses the memory block 74.
[0018]
The memory controller unit 9 performs control such as data exchange and operation mode switching by transmitting control signals and address signals to the memory blocks 71 to 74. The memory controller unit 9 includes an operation mode selection table shown in FIG. 3 for determining the operation mode of each of the memory blocks 71 to 74 according to the combination of the states of a large occupation rate signal BS and access signals ac1 to ac3 described later. Tm is stored.
[0019]
In this operation mode selection table Tm, the reference operation mode varies greatly depending on whether the occupation ratio large signal BS is active or inactive. That is, when the large occupation ratio signal BS is active, all the operation modes of the memory blocks 71 to 74 are set to the normal mode. This is because when the large occupation ratio signal BS is active, it is necessary to increase the processing speed in each of the memory blocks 71 to 74 and decrease the bus occupation ratio S.
[0020]
On the other hand, when the large occupation rate signal BS is inactive, the operation mode of each of the memory blocks 71 to 74 is basically set to the power down mode. In order to keep power consumption low, the self-refresh mode is more advantageous than the power-down mode. However, since the time required to start access (recovery time) becomes longer, the power-down mode is basically set. I am doing so. The recovery time from the power-down mode is several tens of nsec, while the recovery time from the self-refresh mode is several hundred μsec.
[0021]
Here, when the large occupation rate signal BS is inactive and all the access signals ac1 to ac3 are active, only the operation mode of the memory block 74 is set to the normal mode. In this case, the occupation rate S of the bus 5 is low (less than 50%), but since all the DMA control units 1 to 3 are operating, high speed processing is required for the CPU 14.
[0022]
When the large occupation ratio signal BS is inactive and both the access signals ac2 and ac3 are inactive, the operation mode of the memory block 73 is set to the self-refresh mode. Thereby, power consumption can be further reduced. In this way, the operation mode of the memory block 73 can be set to the self-refresh mode because when the image data is decompressed, it may take several hundreds of microseconds for the first access to perform the decompression process in several hundreds of milliseconds. This is because no problem occurs even if the self-refresh mode is shifted to the power-down mode after the access is started.
[0023]
As shown in FIG. 4, when the request signals req1, req2, req3, and req4 are output from the DMA control units 1 to 3 and the access control unit 4, respectively, the bus arbitration unit 6 The bus use permission signals ack1, ack2, ack3, and ack4 are returned to the access control unit 4 as appropriate. As shown in FIG. 5, the bus arbitration unit 6 has a request input register 15 to which the request signals req 1 to req 3 and req 4 of the DMA control units 1 to 3 and the access control unit 4 are input, and the bus 5. A priority table T (see FIG. 13) in which priority levels to be accessed are stored, and a bus response control unit 17 that returns a bus use permission signal ack are provided. The control unit to which the bus use permission signal ack is returned can access the bus 5 only while the bus use permission signal ack issued from the bus response control unit 17 is active.
[0024]
When the DMA control units 1 to 3 and the access control unit 4 output the request signals req1, req2, req3, and req4 at the same time, a priority order table T that records a predetermined priority order (see FIG. 13). ), The access to the bus 5 is arbitrated.
[0025]
Returning to FIG. 4, the bus monitor unit 8 calculates the bus occupation rate S of the bus 5 by monitoring the generation state of the address signal ADD in the bus 5 and detects the operation state of each of the DMA control units 1 to 3. The information is input to the memory controller unit 9. The reason why the bus occupancy S of the bus 5 can be calculated from the address signal ADD in this way is because addresses that can be used by the DMA control units 1 to 3 and the access control unit 4 in the bus 5 are assigned in advance. It is.
[0026]
For example, in this embodiment, as shown in FIG. 6, addresses 0000000h to 0FFFFFFh are assigned to the DMA control unit 1 (memory block 71), and addresses 1000000h to 1FFFFFFh are assigned to the DMA control unit 2 (memory block 72). Addresses 2000000h to 2FFFFFFh are assigned to the DMA control unit 3 (memory block 73), and addresses 3000000h to 3FFFFFFh are assigned to the access control unit 4 (memory block 74). The description of the region signals R1 to R3 in the drawing will be described later.
[0027]
As shown in FIG. 7, the bus monitor unit 8 includes an occupancy rate calculation unit 52 that calculates the bus occupancy rate S, an access detection unit 53 that detects the access status of each of the DMA control units 1 to 3, and an address decoder 51. And is equipped. The address decoder 51 reads the address signal ADD of the bus 5 and activates one of the area signals R1 to R3 according to the address signal ADD. Specifically, since the 24th and 25th bits of the address signal ADD indicate the highest numerical value in the address space, this numerical value is detected, and one of the area signals R1 to R3 is activated according to the detection result. It is supposed to be. For example, if the 24th and 25th bits of the address signal ADD are “10”, the area signal R3 becomes active because it is “2” when converted to hexadecimal.
[0028]
As shown in FIG. 6, the region signal R1 is active for the addresses 0000000h to 0FFFFFFh, and the region signal R2 is for the addresses 1000000h to 1FFFFFFh. It becomes active, and the region signal R3 becomes active for the addresses 2000000h to 2FFFFFFh.
[0029]
As shown in FIG. 8, the occupancy rate calculation unit 52 includes counters 21, 22, 23, extended flip-flops (Delay Flip-Flop, hereinafter referred to as “DFF”) 31, 32, 33, an adder 25, And a comparator 26. The region signal R1 is input to the terminal EN of the counter 21, the clock signal CS is input to the terminal CLK, and the counter clear signal CCS is input to the terminal CLR. On the other hand, the count value C1 in the counter 21 is output from the terminal Q, and this is input to the terminal IN of the DFF 31. An occupancy set signal SSS is input to the terminal CLK of the DFF 31, and an occupancy S 1 is output from the terminal OUT, and this is input to the adder 25.
[0030]
The counter 21 counts up if the region R1 input to the terminal EN is active at the rising edge of the clock signal CS input to the terminal CLK, and outputs the count value C1 from the terminal Q to output the DFF 31. To the terminal IN. When the counter clear signal CCS transmitted every predetermined cycle is input to the terminal CLK, the count value C1 is reset. The counters 22 and 23 have the same function.
[0031]
The DFF 31 outputs the count value C1 input from the counter 21 from the terminal OUT when the occupation rate set signal SSS transmitted every predetermined cycle is input to the terminal CLK. That is, the DFF 31 calculates the generation ratio of the area signal R1 in the input period of the occupation ratio set signal SSS, that is, the bus use ratio of the DMA control unit 1. The DFFs 32 and 33 operate in the same manner, and the DFF 32 calculates the bus usage ratio of the DMA control unit 2 and the DFF 33 calculates the bus usage ratio of the DMA control unit 3.
[0032]
The adder 25 calculates the sum of the bus occupancy rates S1 to S3 calculated by the DFFs 31 to 33. The comparator 26 compares the result calculated by the adder 25 with a threshold value (the threshold value in the present embodiment is “50”), and if the calculated result is greater than the threshold value, the comparator 26 The large occupation ratio signal SB input to the controller unit 9 is activated. Note that the clock signal CS, the counter clear signal CCS, and the occupation rate set signal SSS are all generated inside the bus monitor 8.
[0033]
The access detector 53 outputs the access signals ac1 to ac3 every 1 msec in principle from the state of the area signals R1 to R3. As shown in FIG. 9, the access detection unit 53 includes DFFs 81, 82, 83, DFFs 91, 92, 93, and a counter 80. The counter 80 emits a signal every 1 msec. The clock signal CS (1 μsec cycle) is input to the terminal CLK of the counter 80, and this clock signal CS is output from the terminal OUT every 1 msec. The signal output from the terminal OUT is input to each terminal CLK of each of the DFFs 81 to 83 and 91 to 93.
[0034]
Further, the region signal R1 is input to the terminals PR of the DFFs 81 and 91, the region signal R2 is input to the terminals PR of the DFFs 82 and 92, and the region signal R3 is input to the terminals PR of the DFFs 83 and 93. Thus, the access signal ac1 is immediately activated when the area signal R1 is input to the terminal PR of the DFFs 81 and 91 regardless of the 1 msec period signal from the counter 80. Similarly, when the region signal R2 is input to the terminal PR of the DFFs 82 and 92, the access signal ac2 is immediately activated, and when the region signal R3 is input to the terminal PR of the DFFs 83 and 93, access is immediately performed. The signal ac3 is activated.
[0035]
Furthermore, the terminals IN of the DFFs 81 to 83 are grounded (“Lo” level is fixed), and the terminals OUT of the DFFs 81 to 83 and the terminals IN of the DFFs 91 to 93 are connected to each other. As a result, when the area signal R1 is not input to the terminals PR of the DFFs 81 and 91 for 1 msec or longer, the access signal ac1 is made inactive. Similarly, when the region signal R2 is not input to the terminal PR of the DFFs 82 and 92, the access signal ac2 is inactive, and when the region signal R3 is not input to the terminal PR of the DFFs 83 and 93, the access signal ac3 is inactive. It has become so.
[0036]
Thus, the occupancy rate calculation unit 52 that calculates the occupancy rate S of the bus 5 and the access detection unit 53 that detects the status of access to the bus 5 by the DMA control units 1 to 3 are both configured by hardware. . For this reason, it is not necessary to perform complicated control in the CPU 14 in order to calculate the occupation rate S and to detect the access status of each of the DMA control units 1 to 3.
[0037]
Next, the operation of the DMA control device 10 configured as described above will be described with reference to the timing chart shown in FIG. In this embodiment, both the occupation rate set signal SSS and the counter clear signal CCS are transmitted every 100 μsec, and the counter clear signal CCS is transmitted immediately after the occupation rate set signal SSS is transmitted (after 125 nsec). Yes. The clock signal CS is a signal having a period of 1 μsec.
[0038]
Time t ₀ Previously, the count values C1, C2, and C3 are “50”, “28”, and “9”, respectively. Further, the values “15”, “8”, and “10” read at the time of transmission of the previous occupation rate set signal SSS are input to the adder 25 as the bus occupation rates S1 to S3 of the respective DMA control units 1 to 3. . Therefore, the adder 25 outputs “33” as the calculation result. Although this output is input to the comparator 26, the threshold value “50” is not exceeded, so the large occupation ratio signal BS is inactive (Lo).
[0039]
And time t ₀ Since the address signal ADD is “100FFFFh” at this time, the address decoder 51 sets the area signal R2 to active (Hi) and sets the area signals R1 and R3 to inactive (Lo). Therefore, the counter 22 counts up, and the count value C2 is updated to “29”. On the other hand, since the counters 21 and 23 do not count up, the respective count values C1 and C3 remain “50” and “9”.
[0040]
Here, the region signals R1, R3 are ₀ It is assumed that it has been inactive for 1 msec or more before. Then time t ₀ , The access signal ac1 becomes inactive, the access signal ac2 becomes active, and the access signal ac3 becomes inactive. As a result, the memory controller unit 9 sets all the operation modes of the memory blocks 71 to 74 to the power down mode.
[0041]
Also, time t ₀ 1 μsec after t ₁ Then, the clock signal CS rises again, and at this time, the address signal ADD is “100FFFFh”. Therefore, the address decoder 51 makes the region signal R2 active (Hi) and makes the region signals R1 and R3 inactive (Lo). Therefore, the counter 22 counts up, and the count value C2 is updated to “30”. On the other hand, since the counters 21 and 23 do not count up, the respective count values C1 and C3 remain “50” and “9”. The operation mode of the memory blocks 71 to 74 is the time t. ₀ All remain in power-down mode.
[0042]
Time t ₁ Time t after 500nsec from ₂ , The address signal ADD is changed to “2001234h”. Then, the address decoder 51 makes the region signal R3 active (Hi) and makes the region signals R1 and R2 inactive (Lo). Therefore, although the access signal ac3 becomes active, the operation mode of the memory blocks 71 to 74 is determined at time t according to the operation mode selection table Tm of FIG. ₀ All remain in power-down mode.
[0043]
Then time t ₁ 1 μsec after t ₃ Then, since the clock signal CS rises again, the counter 23 counts up, and the count value C3 is updated to “10”. On the other hand, since the counters 21 and 22 do not count up, the respective count values C1 and C2 remain “50” and “30”.
[0044]
Time t ₃ 375nsec after t ₄ , The occupation rate set signal SSS is input to each of the DFFs 31-33. Then, the DFFs 31 to 33 are time t ₄ The count values C1 to C3 at the time are output as bus occupancy rates S1 to S3. That is, “50” is output as the bus occupation rate S1 from the DFF 31, “30” is output as the bus occupation rate S2 from the DFF 32, and “10” is output as the bus occupation rate S3 from the DFF 33. In this embodiment, the count values C1 to C3 can be output as the bus occupancy rates S1 to S3. In this embodiment, the occupancy rate set signal SSS and the counter clear signal CCS are output at 100 μsec intervals to the DFFs 31 to 33 and the counters 21 to 21. This is because the data is input to 23.
[0045]
The bus occupancy rates S1 to S3 calculated in this way are input to the adder 25. Then, the adder 25 outputs “90” as the calculation result and inputs it to the comparator 26. Since the comparator 26 determines that the threshold value “50” is exceeded, the comparator 26 activates the high occupation ratio signal BS (Hi). As a result, the memory controller unit 9 sets all the operation modes of the memory blocks 71 to 74 to the normal mode according to the operation mode selection table Tm of FIG.
[0046]
Furthermore, time t ₄ T after 125nsec from ₅ At 500 nsec from time t3, a counter clear signal CCS is input to each counter 21-23. As a result, the count values C1 to C3 of the counters 21 to 23 are all cleared and become “0”.
[0047]
Time t ₅ Time t after 500nsec from ₆ Then, the clock signal CS rises again. At this time, since the address signal ADD remains “2001234h” and the area signal R3 is active (Hi), the counter 23 counts up, and the count value C3 is updated. 1 ”. On the other hand, since the area signals R1 and R2 are inactive (Lo), the counters 21 and 22 do not count up, so that the count values C1 and C2 are both “0”.
[0048]
Then time t ₆ Time t after 500nsec from ₇ Assume that the address signal ADD changes to “000ABCDh”. Then, the address decoder 51 makes the region signal R1 active (Hi) and makes the region signals R2 and R3 inactive (Lo). Then time t ₆ 1 μsec after t ₈ Then, since the clock signal CS rises again, the counter 21 counts up, and the count value C1 is updated to “1”. On the other hand, since the counters 22 and 23 do not count up, the respective count values C2 and C3 remain “0” and “1”.
[0049]
Thereafter, similarly, the address decoder 51 makes any one of the region signals R1 to R3 active (Hi), so that the counter corresponding thereto is counted up at the rising edge of the clock signal CS. When the occupancy rate set signal SSS is input to the DFFs 31 to 33, the occupancy rates S1 to S3 of the DMA control units 1 to 3 are calculated. Thereafter, the operation mode of each of the memory blocks 71 to 74 is controlled by the memory controller unit 9 according to the calculation result and the states of the access signals ac1 to ac3. As a result, the memory blocks 71 to 74 are operated in an operation mode with low power consumption within a range that does not adversely affect the processing. Therefore, the power consumption can be effectively reduced.
[0050]
As described above in detail, according to the DMA controller 10 according to the embodiment, the bus monitor unit 8 calculates the bus occupancy S of the bus 5 and detects the operation status of the DMA controls 1 to 3. Is done. The memory controller unit 9 controls the operation mode of each of the memory blocks 71 to 74 in accordance with the calculated bus occupancy S and the operation status of the DAM control units 1 to 3. Accordingly, each of the memory blocks 71 to 74 is operated in an operation mode with low power consumption within a range that does not adversely affect the processing. Therefore, the power consumption can be effectively reduced. The calculation of the bus occupancy S and the detection of the operation status of each of the DMA control units 1 to 3 are performed by the occupancy detection unit 52 and the access detection unit 53 configured by hardware, respectively. For this reason, the control regarding the operation mode of each memory block 71-74 does not become complicated.
[0051]
In addition, the said embodiment is only a mere illustration and does not limit this invention at all. Accordingly, the present invention can be variously improved and modified without departing from the scope of the invention. The DMA control apparatus in the copying machine has been exemplified as the above-described embodiment. However, the present invention is not limited to this, and the present invention can be applied to any apparatus that performs DMA control.
[0052]
【The invention's effect】
As described above, according to the DMA control device of the present invention, the bus usage ratio and access status by a plurality of devices can be grasped without performing complicated control, and the operation mode is controlled for each block of the memory accordingly. The As a result, blocks that do not require high-speed processing can be operated in the low power consumption mode. For this reason, power consumption can be effectively suppressed low.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a DMA control device.
FIG. 2 is a block diagram of a memory and a memory controller unit in FIG. 1;
FIG. 3 is an explanatory diagram for explaining the contents of an operation mode selection table stored in a memory controller unit;
4 is an explanatory diagram for explaining operations of a bus arbitration unit and a bus monitor unit of FIG. 1; FIG.
FIG. 5 is a block diagram illustrating a configuration of a bus arbitration unit in FIG. 1;
FIG. 6 is an explanatory diagram for explaining a correspondence between an address signal, a device, and a region signal.
7 is a block diagram showing a configuration of a bus monitor unit in FIG. 1. FIG.
8 is a block diagram showing a configuration of an occupancy rate calculation unit in FIG. 7. FIG.
9 is a block diagram showing a configuration of an access detection unit in FIG. 7;
FIG. 10 is a timing chart showing states of various signals.
FIG. 11 is a block diagram showing a schematic configuration of a conventional DMA control device.
FIG. 12 is an explanatory diagram for explaining bus arbitration control in a bus arbitration unit;
FIG. 13 is an explanatory diagram for explaining priorities of bus arbitration control in the bus arbitration unit.
[Explanation of symbols]
1,2,3 DMA controller
4 Access control unit
5 buses
6 Bus mediation department
7 memory
8 Bus monitor section
9 Memory controller
10 DMA controller
14 CPU
71, 72, 73, 74 Memory blocks

Claims (2)

CPU,
A memory comprising a plurality of memory blocks;
A shared bus connected to the memory;
A plurality of devices connected to the shared bus and accessing the memory;
Memory controller means for controlling access to the memory by each device;
An occupancy rate calculating means for calculating a usage rate of the shared bus every predetermined time;
Access detecting means for detecting an access status to the shared bus for each device ;
The DMA controller according to claim 1, wherein the memory controller means controls an operation mode for each memory block based on a calculation result of the occupation ratio calculation means and a detection result of the access detection means . The DMA controller according to claim 1, wherein
Each of the memory blocks is storage means that can be written and read at any time,
The DMA controller according to claim 1, wherein the memory controller means sets the operation mode of the storage means to one of a normal mode, a power-down mode, and a self-refresh mode.

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