JP3763664B2 - Test circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit for manufacturing process monitoring, which is formed on a scribe lane provided in a semiconductor substrate for cutting the semiconductor substrate into individual chips.
[0002]
[Prior art]
For the purpose of managing the process conditions of semiconductor integrated circuits, analyzing the cause of characteristic defects, and matching the characteristics of the integrated circuit body with the individual element characteristics such as the transistors that make it up, the element characteristics are usually set on a semiconductor substrate. A test circuit that can be easily measured is formed.
[0003]
Recently, such a test circuit is often formed not on the chip body but on a scribe lane provided on the semiconductor substrate in order to cut the semiconductor substrate into individual chips. This is because the test circuit is omitted from the chip to reduce the area, and the maximum number of chips that can be taken from the semiconductor substrate is secured to contribute to cost reduction.
[0004]
An example of the pattern arrangement of a conventional test circuit formed on a scribe lane is shown in FIG. This test circuit is particularly for MOS type integrated circuits.
In FIG. 5, the following test circuit is formed on the surface of the scribe lane 1, and regions 2 on both sides thereof are regions where the integrated circuit body is formed.
[0005]
Since the scribe lane 1 is typically about 150 μm in width and narrow, the voltage application and measurement pads 3 to 7 and the transistor region 8 are arranged in a line. Although a specific pattern of the MOS transistor in the transistor region 8 is omitted here, it is actually formed.
[0006]
Specifically, the source electrode pad 6 is connected to the source of each transistor in the transistor region 8 by an extended wiring 10. The gate electrode pad 7 is connected to the gate of each transistor in the transistor region 8 through the wiring 11 and the diffusion layer 12 provided on the semiconductor substrate. The voltage application pad 3 is connected to a substrate or a well diffusion layer from a contact portion provided near each transistor in the transistor region 8 by a wiring 9 extending therefrom. The drain electrode pads 4 and 5 are independently connected to the drains of the transistors in the corresponding transistor regions 8, respectively.
[0007]
That is, the source, gate, and substrate (well) of each transistor have a common pad for supplying voltage or measuring them, and the drain pad is independent.
[0008]
FIG. 6 shows the structure of the CC ′ cross section of the test circuit of FIG.
As shown in FIG. 6, FIG. 5 shows a test circuit corresponding to an integrated circuit having a two-layer aluminum wiring structure, in which 21 is a semiconductor substrate, 22 is an insulating oxide film formed by a so-called LOCOS method, 23 Is an interlayer insulating film. Reference numeral 24 denotes a lower aluminum pad portion which is a lower portion of the drain electrode pad 5 made of a first layer aluminum wiring.
[0009]
The wirings 9, 10, and 11 are all formed using the first aluminum wiring layer. Reference numeral 25 denotes an interlayer insulating film, 26 denotes an upper aluminum pad portion on the drain electrode pad 5 formed from the second aluminum wiring layer, 27 denotes a passivation film, and an opening 13 applies a voltage application or measurement probe needle 28. Is provided on the passivation film 27 so as to contact the pad.
[0010]
[Problems to be solved by the invention]
However, such a conventional test circuit has the following problems.
In order to further increase the chip yield from the semiconductor substrate and reduce the cost, the width of the scribe lane must be reduced.
[0011]
As apparent from FIG. 5, the conventional test circuit arrangement requires an area for providing three wirings 9, 10, and 11 having a common pad in parallel in the direction in which the scribe lane extends. Is difficult to effectively shrink.
[0012]
In FIG. 6, when the probe needle 28 is brought into contact with the upper aluminum pad portion 26, if the pressure of the needle is too large, the probe needle 28 is once in contact with the upper aluminum pad portion 26 and then the circuit. Slip on the surface and stop at the position of the probe needle 28 'as shown in phantom lines in FIG. In this case, if the wiring 9 is arranged close to the pad in order to reduce the width of the scribe lane 1 as much as possible, the probe needle 28 can easily reach the position of the wiring 9 and exert pressure to cause damage. Depending on the situation, there is a possibility of cutting.
[0013]
Further, since the source electrode pad 6 is shared, the wiring 10 must be extended and connected to a transistor located at a position considerably away from the source electrode pad 6. The material of the wiring 10 is, for example, a multilayer film of an Al alloy and a refractory metal. If the sheet resistance is about 65 mΩ, the wiring width is 5 μm, and the length is 1000 μm, the wiring resistance is about 12Ω. If this acts as the source parasitic resistance of the transistor, it has an undesirable aspect that it is difficult to accurately evaluate because it affects the drain current and the like.
[0014]
An object of the present invention is to provide a test circuit having a pattern arrangement and a structure that can be mounted on a scribe lane 1 even if the width of the scribe lane 1 is reduced.
[0015]
[Means for Solving the Problems]
In a first test circuit of the present invention for solving the above-described problem, one source electrode pad and one drain electrode pad are provided only for the corresponding source and drain of at least two adjacent transistors, respectively. One gate electrode pad and one substrate potential or well potential supply pad are connected in common to the corresponding gate and substrate potential or well potential supply locations of at least a plurality of transistors, respectively. Further, the gate electrode pad The wiring from the substrate potential or well potential supply pad to the transistor is arranged on one side of the end portion of the scribe lane.
[0016]
By connecting one source electrode pad only to the corresponding sources of at most two adjacent transistors, the wiring length from the source pad to the transistor becomes very short and extends along the scribe lane. Therefore, the wiring area for the wiring can be saved by one line, and the scribe lane width can be shortened. Further, since the source wiring is shortened and the wiring resistance can be reduced, accurate transistor characteristics can be obtained. By providing a long wiring on one side, it is possible to avoid damage to the wiring even if the probe needle moves to the end of the scribe lane deviated from the original position.
[0017]
In the second test circuit of the present invention, the wiring from the gate electrode pad and the substrate potential or well potential supply pad to the transistor is arranged so as to overlap two upper and lower layers.
[0018]
By adopting such a configuration, the area for the wiring extended to the scribe lane can be further saved by one line, and the scribe lane width can be further reduced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS.
( Reference example )
First, in describing the embodiment, a conventional reference example will be described.
FIG. 1 shows ( Reference Example ).
[0020]
A test circuit pattern is formed in the area of the scribe lane 1, and areas 2 on both sides thereof are areas where the integrated circuit body is formed. The scribe lane 1 is about 100 μm, and voltage application and measurement pads 3 to 7 and MOS transistor regions 8, 8 ′, 8 ″,... Are arranged in a line. The specific pattern of the MOS transistor in the region 8 is omitted as in FIG.
[0021]
The source electrode pad 6 is directly connected to the source of the transistor region 8 through a short aluminum wiring 30 of about several tens of μm. The source electrode pad 6 ′ is directly connected to the sources of the two transistor regions 8 ′ and 8 ″ arranged adjacent to each other through short aluminum wirings 31a and 31b of about several tens μm. Drain electrode The pad 5 is commonly connected to the drains of the adjacent transistor regions 8 and 8 ′ via short aluminum wirings 32a and 32b.
[0022]
The gate electrode pad 7 is connected to the gates of the transistor regions 8, 8 ', 8 ",... Via the aluminum wiring 11 and the diffusion layer 12 provided on the semiconductor substrate. 3 is connected to a substrate or well from a contact portion provided in the vicinity of each transistor region 8, 8 ', 8 ",... By an aluminum wiring 9 extended therefrom.
[0023]
These wires 9 and 11 are provided side by side on one side of the scribe lane 1. That is, the gate for each transistor, the supply of voltage to the substrate (well), or a pad for performing measurement thereof is shared by one, and the source / drain pads are arranged independently or commonly connected to only two transistors. It has become.
[0024]
By arranging the source electrode pad 6 ′ to be connected to the sources of the two transistors as described above, the source electrode pad 6 ′ can be directly connected by the very short aluminum wirings 30, 31a, 31b, 32a, and 32b extending from the pads. Therefore, the long wirings installed along the scribe lane 1 become the gate wiring 11 and the substrate or well potential wiring 9, and the conventional wiring 10 can be omitted, and one can be reduced. Can be reduced without difficulty.
[0025]
Also, since the source electrode wiring length to the transistor is very short and the wiring resistance can be ignored, almost correct transistor characteristics can be measured.
Furthermore, the reference example is characterized in that long wires are provided together on one side of the scribe lane. This corresponds to the wiring 9 removed from the conventional example shown in FIG. In such a structure, even if the probe needle is displaced from the pad, there is no wiring on one side, so that it is possible to avoid damaging or cutting long wiring for common connection. Play.
[0026]
Here, if the probe card or the like is set so that the probe needle contacts the circuit surface from the side where the long connection wires 9 and 11 of the scribe lane 1 are installed to the opposite side, the contact pressure is larger than a predetermined value. Sometimes the probe needle can be slid toward the side without the wires 9 and 11.
[0027]
In this ( reference example ), the pads 6 and 6 ′ are used for the source and the pad 5 is used for the drain. However, the pads 6 and 6 ′ may be used for the drain and the pad 5 may be used for the source.
[0028]
(Embodiment 1 )
2 and 3 show (Embodiment 1 ).
2, the connection wiring pattern of the source electrode pads 6, 6 ′ and the drain electrode pad 5 and the transistor regions 8, 8 ′, 8 ″,... Has the same configuration as that of the reference example .
[0029]
On the other hand, the aluminum wiring 14 is extended partway from the gate electrode pad 7. The contact portion 16 is connected to the gate of each MOS transistor through a wiring 15 made of the same conductive layer as that of which the gate electrode of the MOS transistor is formed. The wiring 15 is made of polycrystalline silicon, refractory metal, refractory metal silicide or so-called polycide.
[0030]
The voltage application pad 3 to the substrate or well diffusion layer is connected to the substrate or well from a contact portion provided in the vicinity of each transistor by a wiring 9 extending therefrom. The wiring 9 is mainly composed of aluminum and is provided on top of the wiring 15. The width of the scribe lane 1 is about 80 μm.
[0031]
FIG. 3 shows the structure of the test circuit taken along the line bb ′ of FIG.
FIG. 3 is a cross-sectional view of a test circuit corresponding to an integrated circuit having a two-layer aluminum wiring structure, in which 21 is a semiconductor substrate, 22 is an insulating oxide film formed by a so-called LOCOS method, and 23 is a gate of a MOS transistor. An interlayer insulating film formed on the electrode. Reference numeral 24 denotes a lower aluminum pad portion which is a lower portion of the pad 5 made of the first layer aluminum wiring, 9 denotes a wiring made of the first layer aluminum wiring, and 15 denotes a gate electrode connection wiring made of a conductive layer constituting the gate electrode. is there. Reference numeral 25 denotes an interlayer insulating film, 26 denotes an upper aluminum pad portion which is an upper part of the pad 5 formed from the second aluminum wiring layer, 27 denotes a passivation film, and 13 denotes a passivation film for bringing the probe needle 28 into contact with the pad. 27 is an opening formed in 27.
[0032]
In (Embodiment 1 ), since the wiring 15 extended long over the scribe lane 1 is formed using a conductive layer on which a gate electrode is to be formed, unlike the wiring 9, a two-layer structure with the wiring 9 is formed.
[0033]
Thus, the area occupied by the wiring on the scribe lane is substantially one, and the width of the scribe lane can be further reduced as compared with the arrangement of FIG.
The long wiring 15 from the gate electrode pad 7 has a configuration in which a conductive layer constituting a gate electrode having a higher resistance is used in place of the conventional aluminum wiring layer. However, a current essentially flows through the gate. Therefore, the wiring resistance of the wiring 15 does not cause a problem in measurement.
[0034]
Rather, since the wiring resistance is high, the time constant due to the resistance and the capacitance between the wiring 15 and the substrate 21 is increased, so that there is an advantage that the resistance against a sudden surge applied from the outside to the gate of the transistor is increased. Therefore, in some cases, a protective diode is not required for the gate.
[0035]
Another form of the wiring 15 having this advantage, that is, a diffusion layer formed on the semiconductor substrate can be used. In this case, in addition to reducing the surge by the time constant due to the resistance of the diffusion layer and its PN junction capacitance, the diffusion layer itself serves as a protective diode.
[0036]
The two-layer structure of the wirings 9 and 15 is not limited to the specific example of (Embodiment 1 ), and two different types of conductive layers constituting the semiconductor integrated circuit body can be used. It is also an example that the wiring 9 described in the first embodiment 1 ) is a first-layer aluminum wiring and the wiring 15 is a diffusion layer.
[0037]
(Embodiment 2 )
(Embodiment 2 ) shown in FIG. 4 shows another embodiment of a two-layer structure of the wiring 15 and the wiring 9 in (Embodiment 1 ).
[0038]
Using the first-layer using an aluminum wiring layer, the second layer aluminum wiring layer as a substrate (well) voltage supply wiring 9 as a gate connection wiring 15 'from the pad 7 in FIG. 2 (Embodiment 1) Is. In the configuration of FIG. 3 of (Embodiment 1 ), the thickness of the wiring 15 is about 100 to 250 nm and the thickness of the wiring 9 is about 700 nm, whereas in FIG. 700 nm and the film thickness of the wiring 9 are 1000 nm, and the height of this wiring part is higher than in FIG. In this sense, it can be said that it is superior to (Embodiment 1 ).
[0039]
3 of (Embodiment 1 ) and FIG. 4 of (Embodiment 2 ), even if the integrated circuit body is a metal (aluminum) wiring system having three or more layers, the structure up to the second layer is applied. It can be used as it is. Further, the wirings 9 and 15 'are not limited to the use of the second layer, and any two layers of aluminum multilayer wiring may be selected and used.
[0040]
In each of the above embodiments, the pad disposed at the position sandwiched between the transistors is connected to the adjacent transistors on both sides. However, from the viewpoint of reducing the scribe lane width, the pad is sandwiched between the transistors. Alternatively, a pad for each transistor may be provided at a different position.
[0042]
【The invention's effect】
The test circuit according to claim 1 , wherein one source electrode pad is commonly connected to corresponding sources of at least two adjacent transistors, and one drain electrode pad is at most two adjacent ones. Commonly connected to the corresponding drains of the transistors, one gate electrode pad is commonly connected to the corresponding gates of at least the plurality of transistors, and one substrate potential or well potential supply pad is at least the plurality of the transistors. Are connected in common to the corresponding substrate potential or well potential supply location, and further, the wiring from the gate electrode pad to the gate of the transistor, and the substrate potential or well potential supply of the transistor from the substrate potential or well potential supply pad The wiring to the location should be a scratch with the transistor at the center. Because it is arranged along one of the two longitudinal sides of the brain, it can reduce the number of long wires extended along the scribe lane of the semiconductor substrate in order to supply or measure the voltage commonly to the transistors in the test circuit. This reduces the scribe lane width and increases the number of chips that can be taken from the substrate, thereby contributing to cost reduction. Further, the influence of the source electrode wiring resistance on the transistor is eliminated, and the transistor characteristics can be measured accurately. In addition, a great effect is exhibited such that the wiring can be prevented from being damaged by the probe needle.
[0043]
Further, in claim 2 , the wiring from the gate electrode pad to the gate of the transistor and the wiring from the substrate potential or well potential supply pad to the substrate potential or well potential supply location of the transistor are in two upper and lower layers, Since the positions are arranged so as to overlap each other, the scribe lane width required for mounting the test circuit can be further reduced.
[0044]
A test circuit according to a second aspect of the present invention is the test circuit according to the first aspect, wherein the wiring from the gate electrode pad to the gate of the transistor is formed of a conductive layer constituting the gate electrode of the transistor or a diffusion layer formed on the semiconductor substrate. The advantage is that resistance to sudden surges applied to the gate from the outside increases, and no protective diode is required at the gate. When a diffusion layer formed on a semiconductor substrate is used, the diffusion layer itself acts as a protective diode in addition to alleviating the surge by the time constant due to the resistance of the diffusion layer and its PN junction capacitance.
[0045]
According to a third aspect of the present invention, there is provided a test circuit according to the first aspect , wherein an integrated circuit having a multi-layered conductive layer structure is formed on the semiconductor substrate, a wiring from the gate electrode pad to the gate of the transistor, and a substrate potential or well potential supply pad The wiring from the substrate to the substrate potential or well potential supply point of the transistor is configured using two of the multilayer conductive layers, so that an integrated circuit is formed in regions on both sides of the scribe lane of the semiconductor substrate. The test circuit can be created on the scribe lane.
[Brief description of the drawings]
FIG. 1 is a plan view of a test circuit of (reference example) FIG. 2 is a plan view of (Embodiment 1 ) of a test circuit of the present invention. FIG. 3 is a cross-sectional view taken along line bb ′ of FIG. Sectional view of (Embodiment 2 ) of the test circuit of the present invention FIG. 5 is a plan view showing an example of pattern arrangement of a conventional test circuit. FIG. 6 is a sectional view taken along line cc ′ of FIG.
DESCRIPTION OF SYMBOLS 1 Scribe lane 2 Integrated circuit main body area | region 3 Pad 4 for voltage application to a board | substrate or a well diffused layer 4, 6, 6 'Source electrode pad 5 Drain electrode pad 7 Gate electrode pad 8, 8', 8 "Transistor area | region 9, 10, DESCRIPTION OF SYMBOLS 11, 14, 15 Wiring 12 Diffusion layer 13 Pad opening 16 Contact part 21 Semiconductor substrate 22 Insulating isolation oxide film 23 Interlayer insulating film 24 Lower aluminum pad part 25 of pad 5 made of the first aluminum wiring layer Interlayer insulating film 26 Upper aluminum pad portion 27 of pad 5 made of second-layer aluminum wiring layer 27 Passivation films 28, 28 'Probe needle

Claims (3)

A test circuit formed by arranging along said scribe lanes a plurality of transistors on the semiconductor substrate scribing on the live lane for manufacturing process monitoring of the semiconductor substrate,
One source electrode pad is commonly connected to corresponding sources of two adjacent transistors at most;
One drain electrode pad is commonly connected to corresponding drains of at least two adjacent transistors,
One gate electrode pad, are commonly connected to a corresponding gate before Symbol plurality of transistors,
One substrate potential or well potential supply pads are commonly connected to a corresponding substrate potential or well potential supply point of the previous SL plurality of transistors,
Furthermore wiring from the gate electrode pad to the gate of the transistor, and the wiring from the substrate potential or well potential supply pad to the substrate potential or well potential supply point of the transistor, the scribe lane and the transistor in the center The test circuits are arranged only on one of the two sides in the longitudinal direction and arranged so that the wirings overlap each other. The test circuit according to claim 1 ,
The wiring from the gate electrode pad to the gate of the transistor, a conductive layer or said those formed from diffusion layers formed on the semiconductor substrate test circuit constituting said gate electrode of said transistor. The test circuit according to claim 1 ,
Wherein the semiconductor substrate is formed an integrated circuit of a multi-layer conductive layer structure, the wiring from the gate electrode pad to the gate of the transistor, the substrate potential or well of the transistor from the substrate potential or well potential supply pad A test circuit in which a wiring to a potential supply location is configured using two of the multilayer conductive layers.

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