JP3764622B2 - Image storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image storage device effective for use in a system that needs to write and read a plurality of types of image data.
[0002]
[Prior art]
In recent years, a system of an apparatus for processing image data such as a television receiver or a magnetic recording / reproducing apparatus has used a plurality of memories for writing or reading a plurality of types of image data. As the plurality of types of image data, there are a luminance signal (Y), a color difference signal (C), motion information (M), and the like necessary for constituting one digital video signal. In order to write and read such a digital video signal, at least one field of memory capacity is required for one type of image data. In addition, when considering frame delay processing, the capacity is usually set to 3 fields for one type of image data in consideration of 2 fields and margin and reserve.
[0003]
As shown in FIG. 18, for example, five types of image data are input to the input terminals IN1 to IN5, and each image data is written to and read from the field memories 101 to 105, and output terminals OUT1 to OUT5. 5 types of image data are output. The writing and reading processing of image data to and from these memories 101 to 105 can be performed by synchronizing writing and reading for each memory based on the same clock, or writing and reading for each memory can be performed at different clocks. It can also be done asynchronously based on When frame delay processing is performed, each of the memories 101 to 105 has a memory capacity for three fields.
[0004]
By the way, when a plurality of field memories such as 5 to 6 are separately used in one system as described above, there is a problem that the whole system is increased in size and disadvantageous in terms of cost.
[0005]
[Problems to be solved by the invention]
As described above, when a plurality of field memories are used separately in one system, there is a problem that the whole system becomes large and the cost becomes high.
[0006]
The present invention has been made in response to such a problem, and an object of the present invention is to provide an image storage device that can reduce the circuit scale and is advantageous in terms of cost.
[0007]
[Means for Solving the Problems]
  The present invention includes a first memory means capable of storing a plurality of types of image data, a second memory means for storing image data to be written in the first memory means, and the first memory means. Third memory means for storing the read image data, and selecting the plurality of types of image data by time divisionIn the second memory meansFirst selection means to supply; second selection means for reading out data stored in the third memory means in a time-sharing manner;Reading data from the second memory and writing to the first memory means, and reading data from the first memory means and writing to the third memory means based on the first clock. And at least one of data writing to the second memory means and data reading from the third memory means based on a clock different from the first clock. Memory control means that controls asynchronously with the clock of
  The memory control means further performs an operation for writing the plurality of types of image data in the first memory and an operation for reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner. As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to one cycle period is set, the writing / reading speed of the first memory means, the writing speed to the second memory means, or the reading speed from the third memory means The overflow or underflow caused by the difference from the above is repaired in the preliminary periodAn image storage device.
[0008]
  The present invention also provides a first memory means capable of storing a plurality of types of image data, a second memory means for storing image data to be written to the first memory means, and the first memory means. A third memory means for storing the image data read from the image data, and selecting the plurality of types of image data in a time-sharing mannerIn the second memory meansFirst selection means to supply; second selection means for reading out data stored in the third memory means in a time-sharing manner;Reading data from the second memory and writing to the first memory means, reading data from the first memory means and writing to the third memory means, and the third memory Reading data from meansBased on the first clock to control the second memory means.Write data toThe memory control means for controlling asynchronously with the reading based on a second clock different from the first clock;With,
  The memory control means further performs an operation for writing the plurality of types of image data in the first memory and an operation for reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner. As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a spare period corresponding to one cycle period is set, and an overflow or underflow caused by a difference between the writing / reading speed of the first memory means and the writing speed to the second memory means is detected in the spare period. It is characterized by being repairedAn image storage device.
[0009]
  Furthermore, the present invention provides a first memory means capable of storing a plurality of types of image data, a second memory means for storing image data to be written in the first memory means, and the first memory means. A third memory means for storing the image data read from the image data, and selecting the plurality of types of image data in a time-sharing mannerIn the second memory meansFirst selection means to supply; second selection means for reading out data stored in the third memory means in a time-sharing manner;Reading data from the second memory and writing to the first memory means, and reading data from the first memory means and writing to the third memory meansControlled synchronously based on the first clock, to the second memory meansDataWriting is controlled asynchronously with reading based on a second clock different from the first clock, and reading of data from the third memory means is different from the first and second clocks. Memory control means for controlling asynchronously with the writing based on the third clock,
  The memory control means further performs an operation for writing the plurality of types of image data in the first memory and an operation for reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner. As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to one cycle period is set, and the difference between the writing speed to the second memory means and the reading speed of the third memory means with respect to the writing / reading speed of the first memory means The overflow or underflow caused by the above is repaired in the preliminary period.An image storage device.
[0010]
  Furthermore, the present invention provides a first memory means capable of storing a plurality of types of image data, a second memory means for storing image data to be written in the first memory means, and the first memory. Third memory means for storing image data read from the means; first selection means for selecting the plurality of types of image data in a time-division manner and supplying them to the second memory means; Second selection means for reading data stored in the memory means in a time-sharing manner, reading data from the second memory, writing to the first memory means, and from the first memory means Data reading and writing to the third memory means are controlled in synchronization with each other based on a first clock, and at least one of writing to the second memory means and reading from the third memory means The Serial to the first clock based on different clocks, provided with a memory control means for controlling at said first clock and asynchronous,
  The memory control means further performs an operation for writing the plurality of types of image data in the first memory and an operation for reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner. As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to at least one cycle period is set, and the writing / reading speed of the first memory means and the writing speed to the second memory means or reading from the third memory means An overflow or underflow caused by a difference from the speed is repaired in the preliminary period.An image storage device.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0013]
FIG. 1 is a block diagram schematically showing an image storage device having the basic configuration of the present invention. A case will be described as an example where three types of image data of a luminance signal (Y), a color difference signal (C), and motion information (M) constituting one digital video signal are input / output as a plurality of types of image data.
[0014]
The image storage device 10 includes a first memory unit 11 having a large capacity for at least three fields according to the number of input three types of image data capable of storing a plurality of types of image data, and input terminals 21 to 21. 23. Three types of image data are input from 23 and three buffer memories for storing data to be written in the first memory means 11, each of which has a second memory means 12 having a small capacity below the line memory, , Comprising three buffer memories that store data read from the first memory means 11 and can output the data to the output terminals 31 to 33 at an appropriate timing, each having a small capacity below the line memory. The horizontal synchronizing signal (HD) and vertical synchronizing signal (VD) of the image are input from the memory means 13 and the input terminals 24 and 25, and all of the first to third memory means 11 to 13 are horizontally and It is configured to include a memory means 14 for controlling in synchronism with the synchronization signal directly.
[0015]
The memory control unit 14 can also perform writing and reading in synchronism based on the same clock, for example, horizontal and vertical synchronization signals, for all the memories of the first to third memory units 11 to 13. Alternatively, since the first memory means 11 writes and reads out three types of image data in a time-sharing manner every cycle period as will be described later, the same first writing and reading are performed. The second memory means 12 and the third memory means 13 are read and written synchronously based on the same first clock, and the second memory means 12 Only twelve writes can be performed asynchronously with the read based on a second clock different from the first clock. Alternatively, the writing and reading of the first memory means 11, the reading of the second memory means 12, and the writing of the third memory means 13 are performed synchronously based on the same first clock, and the second memory means The writing of 12 is performed asynchronously with the reading based on the second clock different from the first clock, and the reading of the third memory means 13 is performed differently from the first and second clocks. Based on the clock of 3, the writing can be performed asynchronously.
[0016]
FIG. 2 is a block diagram showing a more specific configuration of the image storage device of FIG. Here, as in FIG. 1, a case where data of three types of images is input / output will be described as an example.
[0017]
The image storage device 10 is a large-capacity memory composed of a single memory chip capable of storing a plurality of types (three in the figure) of image data as the first memory means and having a large capacity for at least three fields. 11 and three buffer memories 12A to 12C on the writing side consisting of a memory having a small capacity below the line memory for inputting the data inputs A to C constituting the second memory means, and the third memory means Data outputs A to C are output, respectively. Three buffer memories 13A to 13C composed of a small-capacity memory equal to or smaller than the line memory as well as the write-side buffer memory, the large-capacity memory 11, the buffer memories 12A to 12C, and 13A to Memory control circuits 15-17 constituting memory control means for controlling 13C and data input terminals 21-2 for inputting three types of image data When, an output terminal 31 to 33 that outputs the three types of image data is constructed by an input terminal 24 and 25 for inputting the horizontal synchronizing signal of the image (HD) and vertical synchronizing signal (VD).
[0018]
These buffer memories 12A to 12C and 13A to 13C are all provided with separate addresses for writing and reading, and are called dual ports, and writing and reading can be operated completely asynchronously. Writing and reading can be performed asynchronously based on different clocks, but writing and reading can be performed synchronously based on the same clock, for example, the same horizontal and vertical synchronization signals, as shown in FIG. Good. The large capacity memory 11 has the same write and read addresses.
[0019]
The operation speed of the memory 11 is very high with respect to the operation speeds of the buffer memories 12A to 12C and 13A to 13C. That is, the speed at which the data inputs A to C are written to the buffer memories 12A to 12C is low-speed writing, while the data read from the buffer memories 12A to 12C and written to the memory 11 is faster. Similarly, the speed of reading from the memory 11 and writing to the buffer memories 13A to 13C is high-speed writing, whereas the speed of reading the data outputs A to C from the buffer memories 13A to 13C is low. .
[0020]
The memory control means 14 includes memory control circuits 15, 16 and 17, and the memory control circuit 15 supplies write and read address signals to the large capacity memory 11. The memory control circuit 16 supplies write and read address signals to the buffer memories 12A, 12B, and 12C. The memory control circuit 17 writes and reads data to and from the buffer memories 13A, 13B, and 13C. The address signal is supplied.
[0021]
Next, FIG. 3 shows timings of writing and reading operations to the large capacity memory 11. Here, the write and read relationships between the buffer memories 12A to 12C and 13A to 13C and the large capacity memory 11 are shown.
[0022]
FIG. 3A shows a write address period A (W), B (W), C (W) assigned to write three types of image data A, B, C to the memory 11 within one cycle. , And read address periods A (R), B (R), and C (R) assigned to read out three types of image data A, B, and C from the memory 11 within one cycle.
[0023]
In the write period of the memory 11, a plurality of addresses (in FIG. 3, (b) in the write period of the memory 11 corresponding to the write address periods A (W), B (W), C (W) per cycle. ), Four clocks for each period, that is, four addresses for each period corresponding to four data) are sequentially supplied. Similarly, during the read period of the memory 11, one cycle from the memory control circuit Corresponding to the read address periods A (R), B (R), and C (R), a plurality of addresses (in FIG. 3, (b) in each period shown in FIG. 3 for 4 clocks, that is, 4 data). Correspondingly, four addresses are sequentially supplied for each period. The memory 11 writing period and reading period constitute one cycle period. In one cycle period, the memory 11 as the first memory means has a set of image data consisting of data A, B, C (ie, Y, C, M) from the second and third memory means 12, 13. Can be considered as a period for writing and reading by a predetermined number of clocks (four clocks in FIG. 3).
[0024]
FIG. 3B shows a basic clock of the memory 11, a period for accessing (reading) the buffer memory 12 A, a period for accessing the buffer memory 12 B, a period for accessing the buffer memory 12 C, and an access to the buffer memory 13 A ( The memory 11 accesses each buffer memory in a time division manner, such as a period for writing), a period for accessing the buffer memory 13B, and a period for accessing the buffer memory 13C.
[0025]
In this manner, access between the large-capacity memory 11 serving as the first memory means and each buffer memory is divided in a time division manner, and input / output access to the memory 11 is performed in accordance with the basic clock. ing. That is, writing and reading of a plurality of types (three types in the example) of image data with respect to the large-capacity memory 11 are performed in a time division manner based on the same clock.
[0026]
On the other hand, the writing and reading of the data A to C with respect to the buffer memories 12A to 12C described above can be performed synchronously or asynchronously. Similarly, the writing and reading of the data A to C with respect to the buffer memories 13A to 13C can be performed as follows. Can be done synchronously or asynchronously.
[0027]
Next, FIG. 4 shows the timing of the data write operation to the buffer memories 12A to 12C and the data read operation from the buffer memories 13A to 13C. FIG. 4 shows an example in which writing and reading of data A to C with respect to the buffer memories 12A to 12C and 13A to 13C are performed synchronously.
[0028]
FIG. 4A shows, for example, 7 cycles of data corresponding to a write area signal or a read area signal (see FIGS. 4C and 4F) to the buffer memory in one horizontal period (HD period). Indicates that there is an access period. As can be seen from FIG. 3, since data of 4 clocks can be read and written for each cycle of data A to C, data of 28 clocks can be read and written in 7 cycles.
[0029]
FIG. 4B shows a buffer clock, and a read / write operation to the buffer memory is performed in accordance with this clock.
[0030]
FIG. 4C shows a signal generated by write area signal generating means (see FIG. 9 described later) for the buffer memories 12A to 12C. Based on the write area signal, the write address counters 161 and 163 shown in FIG. , 165 count operation can generate write addresses to the buffer memories 12A-12C shown in FIG. 2 or FIG.
[0031]
FIG. 4D shows the write data written to the buffer memories 12A to 12C at the timing of the buffer clock corresponding to the write address based on the write area signal of FIG.
[0032]
Similarly, FIG. 4E shows a signal generated by read area signal generating means (see FIG. 10 described later) for the buffer memories 13A to 13C. Based on this read area signal, the read address counter 172 of FIG. , 174, and 176 perform a count operation, so that read addresses from the buffer memories 13A to 13C shown in FIG. 2 or FIG. 8 can be generated.
[0033]
FIG. 4 (f) shows read data read from the buffer memories 13A to 13C at the timing of the buffer clock corresponding to the read address based on the read area signal of FIG. 4 (e).
[0034]
In FIG. 4 described above, the example in which the writing and reading of the data A to C with respect to the buffer memories 12A to 12C and 13A to 13C are performed synchronously based on the same clock is shown. When writing and reading are performed asynchronously, there is a gap between the data writing speed and the data reading speed (this is, for example, a clock skew when performing fast forward rewinding (search) while playing in a VTR system. A countermeasure for absorbing such a deviation between the speeds will be described next with reference to FIG.
[0035]
FIG. 5 also shows the timing of the data write operation to the buffer memories 12A to 12C and the data read operation from the buffer memories 13A to 13C as in FIG.
[0036]
  The relationship between the data access cycle (1 to 7 cycles) in one horizontal period shown in the lower part of FIG. 5A and FIGS. 5B to 5F is shown in the lower part of FIG. A data access cycle (1 to 7 cycles) within one horizontal periodFIG.Since it is the same as the relationship of (b)-(f), the detailed description is abbreviate | omitted. However, FIG. 5 differs from FIG. 4 in that there are few differences within one horizontal period in FIG.BothIn one cycle periodEquivalent toA preliminary cycle period is provided. In FIG. 5 (a), there is a period of one cycle, for example, eight cycles, in one horizontal period, compared to the case of FIG. 4 (a).periodIndicates a data access period (write / read area period) for actually writing and reading data. The eighth cycle is a cycle of one cycle provided to absorb a shift (clock skew) between the data write speed and the read speed at a time other than the data access period.ReserveDue to the presence of this spare period, which is based on clock skewProblems, for exampleIt becomes possible to repair the overflow and underflow of the buffer memory.
    That is,When data from the second memory means 12 is read and written to the first memory means 11, if the writing speed to the second memory means 12 is faster, the read time may be insufficient and an overflow may occur. However, it is possible to repair the overflow by performing reading within the preliminary period of one cycle. Further, when reading the data written in the third memory means 13 from the first memory means 11, if the reading speed of the third memory means is faster, the writing time may be insufficient and an underflow may occur. However, the overflow can be repaired by performing writing within the preliminary period of one cycle.
[0037]
FIG. 6 is a block diagram showing a configuration of the memory control circuit 15 in FIG. Here, the address signal of the memory 11 is generated, and the 12A to 12C read area signal and the 13A to 13C write area signal to the memory control circuits 16 and 17 are generated. The memory control circuit 15 includes a one-cycle counter 151, an enable signal decoder 152, write address area counters 153 to 155 for writing data from the buffer memories 12A to 12C to the memory 11, and the memory 11 to the buffer memories 13A to 13A. The read address area counters 156 to 158 for reading data to 13C and a selector 159 for selecting an address signal according to each address area are provided.
[0038]
The 1-cycle counter 151 corresponds to performing a plurality of (three in FIG. 3) writing and a plurality (three) reading in one cycle period, and each writing / reading operation in one cycle period It is a cycle counter for knowing the position of. The enable decoder 152 designates each period of A (W), B (W), C (W), A (R), B (R), and C (R) based on the output of the 1-cycle counter 151. The signal to be generated is generated.
[0039]
The 12A to 12C write address area counters 153 to 155 count addresses in each period based on the designation signal from the enable signal decoder 152. If the address map of the memory 11 is as shown in FIG. 7, for example, the A, B, and C address areas corresponding to the data A, B, and C in the memory 11 are 0 to 199, 200 to 399, and 400, respectively. When the address is ˜599, the 12A address area counter 153 counts as 0 to 3 in the first cycle period (this 4 count corresponds to 4 counts of the basic clock in FIG. 3), and the next cycle Counts 4-7 when done during the period. Thereafter, the address signal (number) is output in the same manner.
[0040]
Similarly, the 12B address area counter 154 counts as 200 to 203 in the first cycle period, and as 204 to 207 when performed in the next cycle period. Thereafter, the address signal (number) is output in the same manner. Also, the 12C address area counter 155 counts as 400 to 403 in the first cycle period, counts as 404 to 407 when it is performed in the next cycle period, and thereafter counts similarly to output an address signal (number). To do. The same applies to the read address area counters 156 to 158 of 13A to 13C.
[0041]
The selector 159 sends the address signal to the memory 11 to the memory address areas A (W), B (W), C (W), A (R), B (R), C, shown in FIG. The selection is made according to the area designation (R) (in other words, the area designation signal from the enable signal decoder 152).
[0042]
FIG. 7 shows an address map of the memory 11. The memory 11 stores three image data A, B, and C, for example, a luminance signal (Y), a color difference signal (C), and motion information (M). ). Here, the memory 11 has a memory capacity corresponding to three fields of the first to third fields for each of the A, B, and C address areas in consideration of frame delay processing. If no frame delay is considered, each address area may have a capacity for one field. 0 to 199 are assigned as the A address area, 200 to 399 as the B address area, and 400 to 599 as the C address area.
[0043]
The address area counter 153 on the write address side in FIG. 6 described above counts the addresses 0 to 199 of the memory 11, the address area counter 154 counts the addresses 200 to 399 of the memory 11, and the address area counter 155 11 addresses 400 to 599 are in charge. Similarly, the address area counters 156, 157, and 158 on the read address side are responsible for counting the addresses 0 to 199, 200 to 399, and 400 to 599 of the memory 11, respectively.
[0044]
8 shows a configuration example of data input / output between the memory control circuits 16 and 17 and the buffer memories 12A to 12C and 13A to 13C and the memory 11 in FIG.
[0045]
The memory control circuit 16 includes write address counters 161, 163, and 165 and read address counters 162, 164, and 166. The write address counters 161, 163, and 165 count and output the respective write addresses of the buffer memories 12A to 12C in response to 12A to 12C write area signals from the write area signal generating means described later (FIG. 9).
[0046]
The read address counters 162, 164, 166 are signals corresponding to the respective periods of the 12A to 12C read area signals (A (W), B (W), C (W) from the enable signal decoder 152 described above (FIG. 6). ), The read addresses of the buffer memories 12A to 12C are counted and output. The write-side buffer memories 12A to 12C are supplied with write addresses from the write address counters 161, 163, and 165, and supplied with read addresses from the read address counters 162, 164, and 166, respectively.
[0047]
Data inputs A to C are input to the buffer memories 12A to 12C on the writing side, and writing is performed according to the above writing address, or reading is performed according to the above reading address. Each data read from the buffer memories 12A to 12C according to the read address is selected by the selector 177.
[0048]
The selector 177 selects and inputs the data read from the buffer memories 12A to 12C to the memory 11 in correspondence with the count outputs from the read address counters 162, 164, and 166, respectively. At this time, the write address signal is supplied from the memory control circuit 15 described in FIG. 6 to the memory 11, and the data read from the buffer memories 12A to 12C is transmitted to the memory 11 according to the address signal. It is written using 177.
[0049]
On the other hand, the memory control circuit 17 includes write address counters 171, 173, and 175 and read address counters 172, 174, and 176. The write address counters 171, 173, 175 are signals corresponding to the periods of the 13A to 13C write area signals (A (R), B (R), C (R) from the enable signal decoder 152 described above (FIG. 6). ), The write addresses of the buffer memories 13A to 13C are counted and output.
[0050]
On the other hand, the read address counters 172, 174, and 176 count and output the respective read addresses of the buffer memories 13A to 13C in response to 13A to 13C read area signals from the read area signal generating means described later (FIG. 10). . Write addresses are supplied from the write address counters 171, 173, and 175, and read addresses are supplied from the read address counters 172, 174, and 176 to the buffer memories 13 A to 13 C on the read side.
[0051]
In addition, data A to c read from the memory 11 are input to the read side buffer memories 13A to 13C in response to a read address signal from the memory control circuit 15 in FIG. Or reading is performed according to the above-described reading address, and the data outputs A, B, and C are obtained.
[0052]
FIG. 9 is a block diagram showing a generation means of a write area signal (see FIG. 4C) supplied to the 12A to 12C write address counters 161, 163 and 165 shown in FIG. This write area signal generation means counts the buffer clock shown in FIG. 4B per horizontal period, and based on the H counter 41 for knowing the position in one horizontal period, and the count output of the H counter 41. As shown in FIG. 4 (c), H decoders 42 to 44 for designating writing areas 12A to 12C in the horizontal direction in one horizontal period, and horizontal synchronizing signal pulses are counted for one vertical period, Based on the V counter 45 for knowing the position in the vertical period and the count output of the V counter 45, V decoders 46 to 48 for designating each writing area of 12A to 12C in the vertical direction in one vertical period AND of the 12A write area signal from the H decoder 42 and the 12A write area signal from the V decoder 46, and the 12A write area AND circuit 49 that outputs as a signal, 12B write area signal from H decoder 43 and 12B write area signal from V decoder 47, AND circuit 50 that outputs as a 12B write area signal, and H decoder 44 And an AND circuit 51 that takes the AND of the 12C write area signal and the 12C write area signal from the V decoder 48 and outputs the result as a 12C write area signal.
[0053]
FIG. 10 is a block diagram showing a means for generating a read area signal (see FIG. 4E) supplied to the 13A to 13C read address counters 172, 174, and 176 shown in FIG. This read area signal generating means counts the buffer clock shown in FIG. 4B for one horizontal period, and based on the H counter 61 for knowing the position in one horizontal period, and the count output of the H counter 61. Thus, H decoders 62 to 64 are provided for designating the horizontal readout areas 13A to 13C in one horizontal period as shown in FIG.
[0054]
Further, the horizontal synchronization signal pulse is counted for one vertical period, and the V counter 65 for knowing the position in one vertical period, and the count output of the V counter 65, 13A to 13A in the vertical direction in one vertical period. The V decoders 66 to 68 for designating each 13C read area and the 13A read area signal from the H decoder 62 and the 13A read area signal from the V decoder 66 are ANDed and output as a 13A read area signal. AND circuit 69 which performs AND of the 13B read area signal from H decoder 63 and 13B read area signal from V decoder 67 and outputs as 13B read area signal and 13C read from H decoder 64 AND of the area signal and the 13C read area signal from the V decoder 68 It is configured to include an AND circuit 71 for outputting a 13C read area signal.
[0055]
In the embodiment described above, the 12A to 12C read area signal and the 13A to 13C write area signal from the memory control circuit 15 shown in FIG. 6 are converted into the read address counters 162, 164, and 166 shown in FIG. The write address counters 171, 173, and 175 are input as they are.
[0056]
In this connection configuration, the write (W) and read (R) to a certain buffer memory are always kept at a fixed time for the write (W) operation as shown in FIG. 11 (a). If it is performed in parallel (that is, both writing (W) and reading (R) are performed at a constant speed every horizontal period), as shown in FIG. Since the read (R) speed is reduced with respect to the write (W) speed (this is caused by the aforementioned clock skew), the write (W) operation is performed at a constant speed every horizontal period. On the other hand, when the read (R) operation is delayed in time, the read (R) is not completed within one horizontal period, and a new write is performed while reading is performed over the next horizontal period. (W) has been performed, and data cannot be read well. There may occur a cormorant problem.
[0057]
Therefore, when a problem as shown in FIG. 11B occurs, this is detected and reading from the buffer memories 12A to 12C is stopped, and writing to the buffer memories 13A to 13C is similarly performed for the buffer memories 13A to 13C. By stopping it, it is possible to prevent an abnormality in the writing / reading operation. FIG. 12 shows a configuration example for preventing such an abnormality in the read / write operation to the buffer memory. FIG. 13 shows the operation of the data number counter provided in FIG. 12 in comparison with the operation of the address counter shown in FIG.
[0058]
In FIG. 12, the 12A to 12C read area signal and the 13A to 13C write area signal from the memory control circuit 15 shown in FIG. 6 are respectively converted into the read address counters 162, 164, 166 and the write address counter 171 shown in FIG. , 173, 175 are provided on the signal supply line, and the first switch means 84 and the second switch means 94 are provided, and the buffer memories 12A to 12C or the buffer memories 13A to 13C are at the time of writing / reading abnormality or the writing / reading abnormality. 8A, when the first switch means 84 or the second switch means 94 is turned off, the 12A to 12C read area signal or the 13A to 13C write area signal is converted into the 12A to 12C read address counter shown in FIG. 162, 164, 166, or 13A-1 From being supplied to the C write address counters 171, and configured to be cut off.
[0059]
In order to detect an abnormality in the write / read operation of each of the buffer memories 12A to 12C, the write data number counters 161-1, 163-1 and 165-1 and the read data number counters 162-1, 164-1 and 166 -1 is provided. Similarly, in order to detect an abnormality in the read / write operation of each of the buffer memories 13A to 13C, the write data number counters 171-1, 173-1, 175-1 and the read data number counters 172-1, 174- 1, 176-1.
[0060]
First, the abnormality detection of the write / read operation of each of the buffer memories 12A to 12C and the stop of the read operation will be described. The write data number counters 161-1, 163-1 and 165-1 start the count operation at the rising edge of the 12A to 12C write area signal from the write area signal generating means shown in FIG. 9, and are shown in FIG. Thus, the number of write data accesses in each of the buffer memories 12A to 12C in one field period is counted and output.
[0061]
The read number counters 162-1, 164-1, and 166-1 start the count operation at each rising edge of the 12A to 12C read area signals from the enable signal decoder 152 shown in FIG. 6, as shown in FIG. The number of read data accesses in each of the buffer memories 12A to 12C in one field period is counted and output.
[0062]
The subtracter 81 takes the difference between the counter output of the write data number counter 161-1 and the counter output of the read data number counter 162-1. The subtracter 82 determines the counter output of the write data number counter 163-1. The subtracter 83 takes the difference between the counter output of the write data number counter 165-1 and the counter output of the read data number counter 166-1.
[0063]
When the read / write operation of each of the buffer memories 12A to 12C is normally performed as shown in FIG. 11A, the difference value in each field period of each of the subtracters 81 to 83 is substantially constant. However, if the read / write operation of each of the buffer memories 12A to 12C is abnormal as shown in FIG. 11B, the difference value (absolute value) of each of the subtracters 81 to 83 in one field period. Is a value greatly changed from the fixed value.
[0064]
The first switch means 84 is turned on or off depending on whether or not the change of the difference value in one field period from each of the subtracters 81 to 83 is within an allowable range. When the difference outputs of .about.83 are out of the allowable range, the signal supply lines of the 12A to 12C read area signals are shut off (turned off), and the read address counters 162, 164, 166 (see FIG. 8) By prohibiting each operation, the reading operation of each of the buffer memories 12A to 12C can be stopped.
[0065]
Next, detection of an abnormality in the writing / reading operation of each of the buffer memories 13A to 13C and cancellation of the writing operation will be described. The write data number counters 171-1, 173-1, 175-1 start the count operation at the rising edge of the 13A to 13C write area signal from the enable signal decoder 152 shown in FIG. 6, respectively, as shown in FIG. The number of write data accesses in each of the buffer memories 13A to 13C in one field period is counted and output. The read data number counters 172-1, 174-1, and 176-1 start the count operation at each rising edge of the 13A to 13C read area signals from the read area signal generating means shown in FIG. Thus, the number of read data accesses in each of the buffer memories 13A to 13C in one field period is counted and output.
[0066]
The subtracter 91 calculates the difference between the counter output of the write data number counter 171-1 and the counter output of the read data number counter 172-1. The subtracter 92 determines the counter output of the write data number counter 173-1. The subtracter 93 calculates the difference between the counter output of the write data number counter 175-1 and the counter output of the read data number counter 176-1.
[0067]
When the write / read operation of each of the buffer memories 13A to 13C is normally performed as shown in FIG. 11A, the difference value in each field period of each of the subtracters 91 to 93 is substantially constant. If the write / read operation of each of the buffer memories 13A to 13C is abnormal as shown in FIG. 11B, the difference value (absolute value) of each of the subtractors 91 to 93 in one field period. ) Is a value greatly changed from the fixed value.
[0068]
The second switch means is turned on or off depending on whether or not the change in the difference value in one field period from each of the subtracters 91 to 93 is within an allowable range. When the difference outputs of .about.93 are outside the allowable range, the signal supply lines of the 13A to 13C read area signals are shut off (off), and each of the write address counters 171, 173, 175 (see FIG. 8). By making the above operation impossible, the write operation of each of the buffer memories 13A to 13C can be stopped.
[0069]
With the configuration shown in FIG. 12, when a read / write abnormality occurs in the buffer memories 12A to 12C or the buffer memories 13A to 13C, this is detected and reading from the buffer memories 12A to 12C is stopped, or similarly By stopping writing to 13A to 13C, it is possible to prevent the writing / reading operation with respect to the buffer memory from remaining abnormal.
[0070]
According to the image storage device 10 described above, as the first memory means, one large-capacity memory for several fields corresponding to the number of image data is used, and as the second and third memory means, Since each image data can use a small memory below the line memory, even if the number of types of image data handled at a time increases, it can be configured with a single large memory chip, reducing the circuit scale and cost. Reduction can be achieved.
[0071]
Therefore, in this case, the more the number of types of image data handled at a time, the more useful. Further, the memory means performs time-division access for writing and reading a plurality of types of image data in one cycle period when writing and reading of the second and third memory means are performed asynchronously. The access cycle period is set to a predetermined number (for example, 7 cycles), and at least one cycle period is provided in addition to the access cycle period, so that the data write speed and the read speed are within one horizontal period. When the deviation occurs, it can be absorbed.
[0072]
FIG. 14 is a block diagram showing an image storage device according to another embodiment. The image storage device 10A shown here is different from the image storage device 10 of FIG. 1 in that a plurality of third memory means (13, 18, 19...) Are provided.
[0073]
That is, by increasing the buffer memory means on the reading side, the same data from the first memory means 11 (this means that a plurality of sets of the same data when a plurality of types of image data is set as a set of data). , Stored in a plurality of third memory means (13, 18, 19...), And the same data from the plurality of memory means (13, 1819...) At different timings, in other words, different horizontal, It is possible to read out in the vertical phase and display it on the screen of a display device (not shown). At this time, the memory control means 14A creates a plurality of sets of read area signals (see FIG. 4 (e) or FIG. 5 (e)), and stores the same data as a plurality of third memory means (13, 18, 19... ) Is read out at different horizontal and vertical timings.
[0074]
FIG. 15 shows an example in which the same data is displayed in different horizontal and vertical phases on the screen of the display device using the apparatus of FIG. Reference numeral 200 in the figure indicates the screen position written in the third memory means (13, 18, 19,...) In a normal horizontal / vertical phase relationship with respect to the horizontal / vertical synchronizing signal. Indicates the starting point of writing. The screens denoted by reference numerals 201 and 202 are obtained by changing the horizontal and vertical timings for reading the same data from the third memory means 13 and 18 with respect to the position 200 on the display screen. R1 and R2 indicate the reading start points of the screens 201 and 202, respectively.
[0075]
Next, FIG. 16 shows an example of a circuit configuration constituting the main body of the present invention in which the buffer memories 12A to 12C in FIG. 8 are configured as one chip and the buffer memories 13A to 13C are configured as one buffer memory.
[0076]
Here, the memory control circuit 16 includes write address counters 161, 163, 165 and read address counters 162, 164, 166 as in the case of FIG. Similarly to the case of FIG. 8, the memory control circuit 17 includes write address counters 171, 173, 175 and read address counters 172, 174, 176.
[0077]
Write data or read data of the memory 11 is temporarily stored in the buffer memories 12 and 13. In FIG. 8, three types of data are stored and processed in each of the three buffer memories, that is, the write side buffer memories 12A to 12C and the read side buffer memories 13A to 13C. In the case of FIG. The three buffer memories 12A to 12C and 13A to 13C are composed of the buffer memories 12 and 13 each having a single chip configuration.
[0078]
For this purpose, the single buffer memories 12 and 13 divide the memories 12 and 13 into three areas as shown in FIG. 17 in order to store three types of data. The write address counters 161, 163, 165 and 171, 173, 175, the read address counters 162, 164, 166, and 172, 174, 176 count the address range shown in the buffer memory address map of FIG. For example, the data A is controlled in the addresses 0 to 99 by the addresses of the write address counters 161, 163, and 165 and the read address counters 162, 164, and 166, respectively. Similarly, data B is stored at addresses 100 to 199, and data C is stored at addresses 200 to 299. Other operations are the same as those of the counter of FIG.
[0079]
The outputs of the write address counters 161, 163, 165 are input to the selector circuit 300, and the output of the write address counters 161, 163, 165 is selected by the output of the counter 301. The count operation of the counter 301 operates at a speed four times the operation speed of the write address counters 161, 163, 165, and at the time when the write address counters 161, 163, 165 count up by one, the counter circuit 301 Count up by 4. Note that the counter 301 counts from (0) to (3).
[0080]
Therefore, when the output of the counter 301 is (0), the output of the write address counter 161 is selected. Similarly, when the output of the counter 301 is (1), the output of the write address counter 163 and the output of the counter 301 are ( When the output is selected by the write address counter 165 at the time of 2), the write address can be given to the buffer memory 12 by time division.
[0081]
Similarly, a selector circuit 302 that performs a selection operation by the counter 301 is provided, and data inputs A to C are supplied to the inputs of the selector circuit 302. The data A to C selected by the selector circuit 302 are stored in the buffer memory 12. To be supplied. The selector circuit 302 receives data input A when the output of the counter 301 is (0), data input B when the output of the counter 301 is (1), and data input C when the output of the counter 301 is (2). By selecting, it is possible to input three types of data to the buffer memory 12 in a time division manner.
[0082]
On the other hand, the outputs of the read address counters 162, 164, 166 are input to the selector circuit 303. The read address counters 162, 164, and 166 do not count at the same time. When one of the read address counters is always counting, the other two counters are stopped. The selector circuit 303 selects the outputs of the read address counters 162, 164, and 166 that are performing the counting operation, and the output of the selector circuit 303 becomes the read address of the buffer memory 12. Therefore, three types of data read out from the buffer memory 12 are time-divisionally written and written into the memory 11.
[0083]
The control operation of the write-side buffer memory 12 has been described above. Similarly, the control operation of the read-side buffer memory 13 will be described. That is, the outputs of the write address counters 171, 173, and 175 are input to the selector circuit 304. The write address counters 171, 173, and 175 do not count at the same time. When one of the write address counters is always counting, the other two counters are at rest. The selector circuit 304 selects the output of the counter performing the counting operation, and the output of the selector circuit 304 becomes the write address of the buffer memory 13. Therefore, three types of time-divided data read from the memory 11 are written into the buffer memory 13.
[0084]
On the other hand, the outputs of the read address counters 172, 174, and 176 are input to the selector circuit 305 and selected by the output of the counter 306. The count operation of the counter 306 operates at a speed four times the operation speed of the read address counters 172, 174, and 176, and the counter circuit 306 has four counts at the time when the read address counters 172, 174, and 176 count up by one. Count up. Note that the counter 306 counts from (0) to (3).
[0085]
Therefore, when the output of the counter 306 is (0), the output of the read address counter 172 is selected. Similarly, when the output of the counter 306 is (1), the output of the read address counter 174 and the output of the counter 306 are ( By selecting the output of the read address counter 176 at the time of 2), the read address can be given to the buffer memory 13 by time division.
[0086]
The output from the buffer memory 13 is latched by latch circuits 307, 308, and 309 controlled by a switching signal obtained by a decode circuit 313 that decodes the counter output of the counter 306. That is, the latch circuit 307 outputs data input A when the output of the counter 306 is (0), the latch circuit 308 outputs data input B when the output of the counter 306 is (1), and the latch circuit 309 outputs the data input A. When the output is (2), the data input C is latched. Similarly, the latch circuits 310, 311, and 312 controlled by the decode circuit 307 latch the data of the latch circuits 307, 308, and 309 when the output of the counter 306 is (3), respectively, and simultaneously output the data.
[0087]
As described above, by configuring the circuit shown in FIG. 16, a large number of buffer memories 12A to 12C and 13A to 13C arranged around the memory 11 can be configured by a small number of buffer memories 12 and 13, Since the number of memories used can be reduced, a circuit configuration suitable for IC implementation can be achieved. By reducing the buffer memories 12A to 12C and 13A to 13C, not only can the space occupied by the substrate be reduced, but if the wiring length to the buffer memories 12A to 12C and 13A to 13C is increased, the inductor and capacitor components of the wiring Etc. may change and the clock timing may be delayed. For this reason, when a large number of buffer memories 12A to 12C and 13A to 13C are used, there is a possibility that the timing may vary among the individual buffer memories 12A to 12C and 13A to 13C. If this occurs, it will be very difficult to make adjustments individually for design / manufacturing. However, by using a small number of buffer memories 12 and 13 to reduce the number of units used, there will be variations. Even in such a situation, it is very easy to take individual measures, which can contribute to the efficiency of design and manufacturing.
[0088]
In the above embodiment, the case where three types of image data are input as the data inputs A, B, and C has been described. However, the present invention is not limited to this. If a large-capacity memory of more than 3 types and more than 3 fields is used, it is possible to write and read very many types of image data in a time-sharing manner in consideration of frame delay processing. The circuit scale can be reduced, and it is economically advantageous.
[0089]
【The invention's effect】
As described above, according to the present invention, a large-capacity memory is used for reading and writing a plurality of types of image data, and the memory is accessed in a time-sharing manner, so that the circuit scale can be reduced and the cost can be reduced. It is possible not only to realize an advantageous image storage device, but also to reduce the occupied area on the substrate and to make it easy to take individual measures in designing and manufacturing the memory means. Therefore, it is expected to contribute to design and manufacturing efficiency.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an image storage device having a basic configuration according to an embodiment of the present invention.
2 is a block diagram showing a more specific configuration of the image storage device of FIG. 1;
FIG. 3 is a diagram showing the timing of a write / read operation to / from a large-capacity memory 11;
FIG. 4 is a diagram showing timing when a data write operation to the buffer memories 12A to 12C and a data read operation from the buffer memories 13A to 13C are performed in synchronization.
FIG. 5 is a diagram showing timing when data write operations to buffer memories 12A to 12C and data read operations from buffer memories 13A to 13C are performed asynchronously;
6 is a block diagram showing a configuration of a memory control circuit 15 in FIG. 2. FIG.
FIG. 7 is a diagram showing an address map of the large capacity memory 11;
8 is a block diagram showing a configuration example of the memory control circuits 16 and 17 in FIG. 2 and a configuration example of data input / output between the buffer memories 12A to 12C and 13A to 13C and the memory 11. FIG.
9 is a block diagram showing a writing area signal generating means to be supplied to the 12A to 12C write address counters 161, 163 and 165 shown in FIG.
10 is a block diagram showing a read area signal generating means to be supplied to the 13A to 13C read address counters 172, 174, and 176 shown in FIG.
FIG. 11 is a diagram for explaining a defect that occurs when the read (R) speed is reduced with respect to the write (W) speed.
12 is a block diagram showing another configuration between the memory control circuits 15 to 17 for preventing the problem described in FIG. 11;
13 is an explanatory diagram showing the operation of the data number counter shown in FIG. 12 in comparison with the operation of the address counter shown in FIG.
FIG. 14 is a block diagram showing another embodiment of the image storage device of the present invention.
15 is a diagram showing an example in which the same data is displayed in different horizontal and vertical phases on the screen of the display device using the device of FIG. 14;
16 is a block diagram showing a case where the buffer memories 12A to 12C and 13A to 13C shown in FIG. 8 are each configured by one memory chip.
FIG. 17 is an explanatory diagram showing an address map of the buffer memories 12 and 13 shown in FIG. 16;
FIG. 18 is a block diagram showing a conventional image storage device.
[Explanation of symbols]
10, 10A: Image storage device
11: First memory means (large capacity memory)
12: Second memory means (buffer memory)
12A, 12B, 12C: Buffer memory
13: Third memory means (buffer memory)
13A, 13B, 13C: buffer memory
14, 14A: Memory control means
15, 16, 17: Memory control circuit
21, 22, 23: Data input terminals
31, 32, 33, 34, 35, 36, 37, 38, 39: data output terminals
300, 302, 303, 304, 305: selector circuit
301, 306: Counter
307, 308, 309, 310, 311, 312: latch circuit

Claims (4)

First memory means capable of storing a plurality of types of image data;
Second memory means for storing image data to be written to the first memory means;
Third memory means for storing image data read from the first memory means;
First selection means for selecting the plurality of types of image data in a time-sharing manner and supplying the second memory means to the second memory means ;
Second selection means for reading out the data stored in the third memory means in a time-sharing manner;
Reading data from the second memory and writing to the first memory means, and reading data from the first memory means and writing to the third memory means based on the first clock. And at least one of data writing to the second memory means and data reading from the third memory means based on a clock different from the first clock. Memory control means that controls asynchronously with the clock of
The memory control means further performs an operation of writing the plurality of types of image data in the first memory and an operation of reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to one cycle period is set, the writing / reading speed of the first memory means, the writing speed to the second memory means, or the reading speed from the third memory means An image storage device characterized in that an overflow or underflow caused by a difference from the above is repaired in the preliminary period . First memory means capable of storing a plurality of types of image data;
Second memory means for storing image data to be written to the first memory means;
Third memory means for storing image data read from the first memory means;
First selection means for selecting the plurality of types of image data in a time-sharing manner and supplying the second memory means to the second memory means ;
Second selection means for reading out the data stored in the third memory means in a time-sharing manner;
Reading data from the second memory and writing to the first memory means, reading data from the first memory means and writing to the third memory means, and the third memory The reading of data from the means is controlled synchronously based on a first clock, and the writing of data to the second memory means is read based on a second clock different from the first clock. and a said memory control means for controlling asynchronously with,
The memory control means further performs an operation of writing the plurality of types of image data in the first memory and an operation of reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a spare period corresponding to one cycle period is set, and an overflow or underflow caused by a difference between the writing / reading speed of the first memory means and the writing speed to the second memory means is detected in the spare period. An image storage device characterized in that the image is restored . First memory means capable of storing a plurality of types of image data;
Second memory means for storing image data to be written to the first memory means;
Third memory means for storing image data read from the first memory means;
First selection means for selecting the plurality of types of image data in a time-sharing manner and supplying the second memory means to the second memory means ;
Second selection means for reading out the data stored in the third memory means in a time-sharing manner;
Reading data from the second memory and writing to the first memory means, and reading data from the first memory means and writing to the third memory means are based on a first clock. The third memory means for controlling the writing of data to the second memory means asynchronously with the reading based on a second clock different from the first clock. Memory control means for controlling the reading of data from the first and second clocks asynchronously with respect to the writing based on a third clock different from the first and second clocks;
The memory control means further performs an operation of writing the plurality of types of image data in the first memory and an operation of reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to one cycle period is set, and the difference between the writing speed to the second memory means and the reading speed of the third memory means with respect to the writing / reading speed of the first memory means An image storage device characterized in that an overflow or underflow due to is repaired in the preliminary period . First memory means capable of storing a plurality of types of image data;
Second memory means for storing image data to be written to the first memory means;
Third memory means for storing image data read from the first memory means;
First selection means for selecting the plurality of types of image data in a time-sharing manner and supplying the second memory means to the second memory means;
Second selection means for reading out the data stored in the third memory means in a time-sharing manner;
Reading data from the second memory and writing to the first memory means, and reading data from the first memory means and writing to the third memory means based on the first clock. And at least one of writing to the second memory means and reading from the third memory means based on a clock different from the first clock, Equipped with memory control means to control asynchronously,
The memory control means further performs an operation for writing the plurality of types of image data in the first memory and an operation for reading from the first memory by a predetermined number of clocks in a time-sharing manner, and writing in the time-sharing manner. As a data access period within one horizontal period for the first memory means, a first data access period corresponding to a predetermined number of cycle periods, and the first data In addition to the access period, a preliminary period corresponding to at least one cycle period is set, and the writing / reading speed of the first memory means and the writing speed to the second memory means or reading from the third memory means An image storage device characterized in that an overflow or underflow caused by a difference from the speed is repaired in the preliminary period .

Images