JP3768475B2 - Semiconductor integrated circuit and trimming adjustment method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a trimming adjustment method thereof, and more particularly, to a semiconductor integrated circuit and a trimming adjustment method thereof that realize improvement in product accuracy and efficiency from design to commercialization.
[0002]
[Prior art]
In general, as a trimming method used in a semiconductor integrated circuit, for example, there is a circuit that selects a predetermined voltage. FIG. 12 shows an example of this trimming circuit. This circuit includes a trimming circuit 21 and a constant voltage circuit 22. The trimming circuit 21 includes P-channel MOS transistors M4, M5, and M6, NPN transistors Q1, Q2, and Q3, which are referred to as bipolar transistors above, constant current sources CI1, CI2, and CI3, and a control signal input pad IN1, IN 2 and IN 3 and wirings D, E, and F, the source of the P-channel MOS transistor is at the power supply potential VDD, the gate is at the control potential VG, the drain is any of the wirings D, E, and F and the collector of the NPN transistor The base of the NPN transistor is commonly connected to the constant current source and the control signal input pad, and the emitter is grounded.
[0003]
The constant voltage circuit 22 includes an amplifier AMP1, resistors R1 to R5 constituting an output voltage dividing circuit, and N-channel MOS transistors M1, M2, and M3 having sources and drains connected in parallel to R1 to R3, respectively. The gates of the N-channel MOS transistors M1, M2, and M3 are connected to wirings D, E, and F, respectively, and the amplifier AMP1 is supplied with Vref as a (+) input, and the output voltage VR as a (−) input is a predetermined voltage. A voltage divided by the division ratio is given, and there is a relationship of VR = Vref × (R1 + R2 + R3 + R4 + R5) / (R1 + R2 + R3 + R4). The resistors R1 to R3 are trimming targets, and VR can be adjusted to a desired value by performing trimming.
[0004]
In the trimming circuit 21, the current drive capability of the constant current sources CI1, CI2, and CI3 is I1, the collector current drive capability of the NPN transistors Q1, Q2, and Q3 is I2 (= hfe × I1), the P-channel MOS transistors M4, M5, The current drive capability I1 and P channel of the constant current sources CI1, CI2, CI3 so that I3 <I2 when the control signal input pads IN1, IN2, IN3 are open, with the source / drain current drive capability of M6 as I3 The gate control potential VG of the MOS transistors M4, M5, M6 is set.
[0005]
By doing this, when the control signal input pad is opened, the collector current I2 of the NPN transistors Q1, Q2, and Q3 is forcibly set to the same value as I3, so that the collector voltage becomes Lo level, and the gate is connected to this. The N-channel MOS transistors M1, M2, and M3 in the constant voltage circuit 2 are turned off. In this state, the resistors R1 to R3 are connected to the other elements before and after being short-circuited. That is, trimming is not performed in this state.
[0006]
When performing prior confirmation of trimming, 0V is applied to the selected control signal input pad, and the base voltage of the corresponding one of the NPN transistors Q1, Q2, and Q3 is set to 0V. Since the selected NPN transistor is cut off, its collector voltage becomes Hi level, and the corresponding one of the N channel MOS transistors in the constant voltage circuit 2 is turned on. In this state, corresponding ones of the resistors R1 to R3 are short-circuited. That is, in this state, a temporary trimming state appears. As a result, it is possible to know before the trimming is performed whether the control voltage input pad to which 0 V is applied is selected in what combination the output voltage VR of the constant voltage circuit 2 becomes a desired value.
[0007]
Next, when performing trimming, the selected NPN is selected by applying a voltage higher than the withstand voltage from the corresponding control signal input pad to the base and emitter of the NPN transistor in the combination confirmed in advance as described above. The transistor is destroyed and its hfe is lowered as shown in FIG. As a result, the collector voltage of the destroyed NPN transistor is maintained at the Hi level even if the control signal input pad is opened, so that the corresponding N-channel MOS transistor in the constant voltage circuit 22 is always in the ON state, and the trimming state is fixed. Is done.
[0008]
In a semiconductor integrated circuit incorporating this type of analog circuit, characteristics may fluctuate drastically due to manufacturing errors, leading to a decrease in yield. In order to solve this problem, high-precision design and verification have been required at the design stage.
[0009]
In addition, as a conventional semiconductor integrated circuit manufacturing process, as shown in the flowchart of FIG. 13, a trimming circuit using a resistance tap or the like is provided in advance as a technique for dealing with a large variation in characteristics due to a manufacturing error. As a result, sufficient characteristics were evaluated in the evaluation of the prototype product, and trimming was optimized before commercialization.
[0010]
That is, in FIG. 13, first, the wafer 10 is designed with high accuracy at the design stage of step S101a. According to this design, the wafer 10 is prototyped at the trial stage of the next step S102, and the evaluation stage of step S103. In step S104, if the specification (standard) is not satisfied, the process returns to step S101a and the design is re-executed. If the specification is satisfied, optimal trimming is performed with the design value in step S104b. . For the product sample 11 as well, the sample 11 is designed at the design stage of step S101a, the sample 11 is prototyped at the prototype stage of the next step S102, and the sample 11 is evaluated at the evaluation stage of step S103. If the specification is not satisfied in step S104, the process returns to step S101a and the design is performed again. If the specification is satisfied, trimming is performed with the design value in step S104b.
[0011]
Based on the result of trimming, mass production of the wafer 10a is performed in step S105, and primary inspection of the wafer 10a is performed in step S106. If the inspection result of the wafer 10a is not good, it is processed as a defective product in step S110. If the inspection result is good, the process proceeds to step S107, and mass production of the product 11a is performed. In step S108, a secondary inspection of the product 11a is performed. If the inspection result of the product 11a is not good, the product is processed as a defective product in step S110. If the inspection result is good, the process proceeds to step S109 and shipped as a good product 11a.
[0012]
[Patent Document 1]
JP-A-10-335593
[0013]
[Problems to be solved by the invention]
As described above, as a conventional semiconductor integrated circuit (IC) trimming method, trimming is uniformly performed with the trimming amount determined by the evaluation data at the time of prototyping, so individual accuracy can be improved. There is no problem. There was also a method of performing trimming by measuring individually, but because there was only one measurement condition, there was a problem that it could not be sufficiently guaranteed for measurement data with temperature dependence and power supply voltage dependence. It was.
[0014]
In the conventional manufacturing process, high-accuracy design and verification that fully considers manufacturing variations and temperature dependence are required at the design stage, and the optimal trimming value is based on the evaluation results of the prototype. Therefore, a sufficient design study was required. In addition, when there is a difference in characteristics between the prototype and the mass-produced product, the product standard is not achieved, and there is a problem that stable product shipment is not possible.
[0015]
An object of the present invention is to provide an IC capable of improving the accuracy of a product and improving the efficiency from design to commercialization, and a trimming adjustment method for the IC.
[0016]
[Means for Solving the Problems]
The configuration of the semiconductor integrated circuit of the present invention stores the first measurement data of the circuit measured under the first measurement condition and the second measurement data of the circuit measured under the second measurement condition. Non-volatile storage means and the circuit constants of the analog circuit are corrected by a predetermined arithmetic expression so that the first measurement data and the second measurement data from the non-volatile storage means fall within a predetermined standard, and the trimming amount is set. And a trimming circuit for changing a circuit constant of the analog circuit in accordance with an output of the computing means, wherein the first and second measurement conditions are parameters such as temperature, voltage characteristics or frequency characteristics. It is determined by.
[0017]
According to the configuration of the semiconductor integrated circuit trimming adjustment method of the present invention, the semiconductor integrated circuit obtains the first measurement data of the circuit under the first measurement condition, and stores the first measurement data in the nonvolatile storage means. A first procedure; a second procedure for obtaining second measurement data of the circuit under a second measurement condition; and storing the second measurement data in the nonvolatile storage means; and the nonvolatile storage element. Including a third procedure for reading out the first measurement data and the second measurement data from the first calculation data and obtaining a trimming amount based on a predetermined arithmetic expression, and a third procedure for performing trimming with the trimming amount. The first and second measurement conditions are determined by parameters such as temperature, voltage characteristics or frequency characteristics.
[0018]
In the present invention, the first measurement condition may be normal temperature, the second measurement condition may be a temperature that is at least 60 ° C. higher than normal temperature, the power supply voltage is measured under the first measurement condition, The voltage at which the power supply voltage changes can be measured under the second measurement condition, the predetermined oscillation frequency in the circuit can be measured under the first measurement condition, and the frequency at which the oscillation frequency has changed under the second measurement condition. In addition, the detection voltage of the power-on-clear circuit can be measured under the first measurement condition, and the voltage at which the detection voltage of the power-on-clear circuit has changed can be measured under the second measurement condition. .
[0019]
According to the configuration of the present invention, in a semiconductor integrated circuit having temperature dependency, measurement results under different conditions are stored in an internal storage circuit for a semiconductor integrated circuit in which manufacturing errors and characteristic variations should be sufficiently taken into consideration at the design stage. Means for performing trimming based on the result, and writing measurement values under different conditions to the internal storage circuit, and in the second (final) step under the different conditions. Since the measured value is calculated based on a predetermined calculation formula and the trimming value is determined, the product specifications have not been achieved and stable product shipment cannot be achieved when there is a difference in characteristics between the prototype evaluation product and the mass-produced product. Is solved, and it becomes possible to carry out stable and highly accurate product shipment. At the same time, high-accuracy design and verification that fully considers manufacturing variations and temperature dependence are not necessary at the design stage, which was necessary in the past, and the optimal trimming value is fully examined based on the evaluation results of the prototype. There is also a feature that efficiency is improved from design to commercialization.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. 1A and 1B are flow charts of an IC trimming process for explaining an embodiment of the present invention, and FIG. 2 is a block diagram of an example of an IC that realizes the trimming process.
[0021]
Referring to FIG. 2, the circuit configuration of the present embodiment includes a power regulator circuit 1 to be trimmed, a nonvolatile storage element 5 such as EEPROM or FLASH for storing measurement data in the chip, and writing of measurement data. And a test circuit 3 for controlling reading, a port (PORT) circuit 4 as an I / F of measurement data, and a trimming circuit 2 for correcting an output value of the power supply regulator circuit 1, and these are internal buses. 6 is configured as a semiconductor integrated circuit connected at 6. Reference numeral 7 denotes an input / output terminal.
[0022]
In the inspection process for inspecting the semiconductor integrated circuit of FIG. 2, a test is performed using an LSI test apparatus. Based on the inspection flow of the present embodiment of FIG. 1A by the LSI test apparatus, first, in the first inspection step S10, the power regulator circuit 1 that is output to the external output terminal under the condition of the temperature of 85 degrees. The output value is measured (step S11). The measured voltage value is converted into a digital value by the inspection program, and then in step S12, the test mode for writing the digital value to the internal nonvolatile memory element 5 is drawn, and the internal nonvolatile memory is connected via the PORT circuit 4. The measurement data is stored in the sexual memory element 5. In step S13, a normal inspection is performed.
[0023]
Next, in the second inspection step S20, the output value of the power supply regulator circuit 1 output to the external output terminal under the condition of a temperature of 25 degrees is measured (step S14). After the measurement data in the first inspection step S10 is drawn into the test mode for reading out the internal nonvolatile memory element 5, the data is read out through the PORT circuit 4 in step S15 and measured in the second inspection step S20. On the basis of the measured data and the data measured in the first inspection step S10, in step S16, the trimming value is calculated on the inspection program, and the test mode is drawn in order to perform the trimming correction. The trimming value is transferred to the trimming circuit to perform trimming correction. In step S17, a normal inspection is performed.
[0024]
Further, the flow from design to product shipment of this embodiment is as shown in the flowchart of FIG. That is, in FIG. 3, first, the simplified design of the wafer 10 is performed at the design stage of step S101, and the wafer 10 is prototyped at the prototype stage of the next step S102 according to this design, and the evaluation stage of step S103. Then, a simplified evaluation is performed, and if the specification (standard) is not satisfied in step S104, the process returns to step S101 and the design is performed again. If the specification is satisfied, the product sample 11 is also designed.
[0025]
That is, the simplified design of the sample 11 is performed at the design stage of step S101, the sample 11 is prototyped at the trial production stage of the next step S102, and the simplified evaluation of the sample 11 is performed at the evaluation stage of step S103. If the specification is not satisfied in step S104, the process returns to step S101, and the design is re-executed. If the specification is satisfied, the process proceeds to the mass production stage of step S105 without performing trimming as in the prior art.
[0026]
Based on the fact that the product specifications are satisfied, mass production of the wafer 10a is performed in step S105, and primary inspection of the wafer 10a is performed in step S106. If the inspection result of the wafer 10a is not good, it is processed as a defective product in step S110. If the inspection result is good, the process proceeds to step S107, and mass production of the product 11a is performed. Further, in step S108, a secondary inspection of the product 11a is performed. If the inspection result of the product 11a is not good, the product is processed as a defective product in step S110. If the inspection result is good, the process proceeds to step S109 and shipped as a good product 11a.
[0027]
In the present embodiment, measurement values under different conditions are written in the internal storage element 5, and in the second (final) step S20, the measurement values under the different conditions are calculated based on a predetermined arithmetic expression to obtain trimming values. Therefore, it is possible to simplify the design and the evaluation even if the design stage S101 is not sufficiently examined and the evaluation stage S103 is simple. In the past, when there was a difference in the characteristics between the prototype evaluation product and the mass-produced product, the production specification was not achieved, and there was a problem that the product could not be shipped. Shipment will be possible.
[0028]
The details of the flow of the trimming value calculation and trimming step S16 in FIG. 1A are as described in the flowchart of FIG. 1B, and this calculation example is shown in steps S21 to S28 in the flowchart. . First, in step S21, it is determined whether or not trimming is possible using the measurement data. In this determination, an upper limit value and a lower limit value are set so as to satisfy the product specifications. If the slope of the data is larger than the slope of the upper limit and the lower limit, correction is impossible and a failure occurs (step S22). Next, if it is determined in step S21 that trimming is possible, in step S23, the upper limit value of the product spec is subtracted from the measured value at high temperature, this value is set to A, and in step S24, the product spec is calculated from the measured value at low temperature. The lower limit value is subtracted, and this value is set to B. In step S25, (A−B) / 2 is calculated as a correction value. In step S26, it is determined whether or not the correction value is positive. If the correction value is negative in step S26, trimming for the + correction value is performed in step S28.
[0029]
Next, a specific measurement example of this embodiment will be described with reference to the graphs of FIGS. As these trimming adjustment methods, an LSI test apparatus is used to measure the output voltage value of the power supply regulator at high temperature (85 degrees C) and low temperature (25 degrees C), respectively, and within a predetermined standard (spec) S range. The correction calculation is performed to determine whether trimming is possible. In the specific trimming examples shown in FIGS. 4 and 5, since the inclination of the measurement data is smaller than the inclinations of the upper limit and the lower limit, correction is possible, and the product becomes a non-defective sample and trimming is performed on the arrow side in the figure.
[0030]
That is, in FIG. 4, the measurement values x and y of the measurement data at the high temperature measurement temperature of 85 ° C. and the low temperature measurement temperature of 25 ° C. are 5.0V and 3.5V, and the upper limit X = 3 of the product specification S. .8V and lower limit Y = 2.2V,
A = measured value at high temperature x-upper limit value X = 5.0-3.8 = 1.2 V,
B = Measured value at low temperature y−Lower limit value Y = 3.5−2.2 = 1.3V
Therefore, C = average difference between upper limit and lower limit = (A + B) ÷ 2 = 1.25V. Therefore, the trimming value is 1.25 V. When each measurement value is corrected by this trimming correction value, the correction value x ′ is 3.7 V (upper limit value 3.8), and the correction value y ′ is It becomes 2.2 V (lower limit value 2.3), and is within the product specification S.
[0031]
Further, in FIG. 5, at the same high and low measurement temperatures, the measurement values x and y of the measurement data are 1.4 V and 2.8 V, the upper limit X of the product specification S is 3.8 V, and the lower limit Y = Assuming 2.2V
A = Measured value at high temperature x−Upper limit value X = 1.4-3.8 = −2.4V,
B = Measured value at low temperature y−Lower limit value Y = 2.8−2.2 = 0.6V
Therefore, C = average difference between upper limit and lower limit = (A + B) ÷ 2 = −0.9V. Therefore, the trimming value is 0.9 V, and the trimmed value is 2.3 V (upper limit value 2.2) for the lower limit value x ′ and 3.7 V (upper limit value 3.8) for the upper limit value y ′. )
[0032]
As shown in FIGS. 4 and 5, trimming is possible if the slope of the measurement data is equal to or smaller than the slopes of the upper limit and lower limit, and calculation is performed based on the trimming calculation flow of FIG. Is called.
[0033]
On the other hand, in FIG. 6, the measurement data measured values x and y are 4.6 V and 2.2 V at the same high and low measurement temperatures, and the product specification S upper limit X = 3.8 V and lower limit. If Y = 2.2V,
A = Measured value at high temperature x−Upper limit value X = 4.6-3.8 = 0.8 V,
B = Measured value at low temperature y−Lower limit value Y = 2.2−2.2 = 0.0V
Therefore, C = average of difference between upper limit and lower limit = (A + B) ÷ 2 = 0.4V. Therefore, the trimming value is 0.4 V, and after trimming, the upper limit value x ′ is 4.2 V (upper limit value 3.8), and the lower limit value y ′ is 1.8 V (lower limit value 2.2). )
[0034]
In the specific trimming example of FIG. 6, since the slope of the measurement data is larger than the slopes of the upper limit and the lower limit, the correction cannot be made and a defective sample is obtained.
[0035]
In the present embodiment and specific examples, the first and second measurement conditions are measured at high and low temperatures. However, the first and second measurement conditions are voltage characteristics or frequency characteristics in addition to temperature. It can also be determined by parameters such as
[0036]
FIG. 7 is a block diagram more specifically showing the embodiment of FIG. In this circuit configuration, as shown in the figure, a CPU 8 is mounted, a trimming operation processing firmware is stored in the storage means 9 which can execute instructions by the CPU 8 and becomes a trimming operation FIRMROM, and the firmware is executed in the inspection process. In this mode, the trimming operation is realized by pulling in the mode. In addition, trimming correction can be realized by correcting the conversion accuracy of the A / D and D / A circuits instead of the power supply regulator circuit.
[0037]
FIG. 8 is a flowchart for trimming illustrating the second embodiment of the present invention. According to the inspection flow of FIG. 8, the standard deviation is calculated by a statistical method for the trimming value so far for a certain inspection quantity, and if it is less than the threshold value, the trimming optimum value is calculated, and thereafter the trimming value of the inspection device By performing trimming with an optimized trimming value without performing each calculation, parallel inspection and shortening of inspection time are realized.
[0038]
That is, if the trimming value has not been optimized in step S31, the inspection quantity is checked in step S32. If the trimming value has been optimized in step S31, the process proceeds to step S36 to perform trimming. In step S32, the inspection quantity is checked to see if it is the inspection quantity n. If the inspection quantity n is not completed, the trimming operation in step S16 described above is repeated. If the trimming operation has been completed in step S31, the process proceeds to step S37.
[0039]
If there is an inspection quantity n in step S32, a standard deviation is calculated in step S33 based on each trimming value stored on the inspection program. In step S34, it is determined whether or not the standard deviation is equal to or smaller than a certain threshold value. If it is equal to or smaller than the threshold value, an optimum trimming value is calculated in step S35, and trimming with the optimum trimming value is performed in step S36. The normal test in step S17 is performed.
[0040]
If the standard deviation is not less than the threshold value in step S34, the process proceeds to the trimming operation in step S16 described above. In step S37, the optimum trimming value is stored in the memory on the inspection program, and the normal test in step S17 is performed. carry out.
[0041]
When calculating the standard deviation from this measurement data, assuming that n correction values xi are obtained from each measurement data, this correction average value x = x _i / N, and its standard deviation is Σ (x _i -X) It is calculated | required by the square root of 2 / (n-1). In this case, the correction average value x of the measurement data becomes a correction value, and a standard deviation allowed for the correction value is set as a predetermined threshold value. For example, assuming that the average value for 50 times measurement data is 1.35, the standard deviation value threshold is 0.18, and the standard deviation value is less than or equal to the threshold, the trimming correction value is 1. At 35, all trimming corrections are performed.
[0042]
FIG. 9 is a graph illustrating a third embodiment of the present invention. This is a case where trimming correction is performed to correct the return accuracy of the A / D and D / A conversion circuits instead of the power supply regulator circuit. In this D / A circuit, the analog output voltage obtained by converting the digital input voltage by the D / A circuit is measured and corrected based on the trimming operation shown in FIG. For example, in the trimming correction in the 8-bit D / A circuit, when AVref = 3V, the measured value 1.34V at the high temperature and the measured value 1 at the low temperature are compared with the expected value 1.3124944 of “01111111 (7F)”. It is assumed that the upper limit value is “81” and the lower limit value is “7D”.
[0043]
1.34-1.3359318 (81) = 0.0040682 ... (A)
1.32-1.289057 (7D) = 0.030943 (B)
Therefore, (A + B) /2=0.0350112/2=0.0175056
Becomes the correction value, and the corrected value at high temperature and low temperature is
1.34-0.0175056 = 1.224944
1.32-0.0175056 = 1.0244944
As shown in the graph of FIG.
[0044]
FIG. 10 is a graph for explaining the fourth embodiment of the present invention. This realizes trimming correction by correcting the output frequency value of the ring oscillator circuit instead of the power regulator circuit. That is, the output frequency of the ring oscillator circuit is measured and corrected based on the trimming calculation. The output frequency of this ring oscillator circuit is assumed to be an expected value of 500 Hz, an upper limit value of 540 Hz, and an upper limit value of 460 Hz, a high temperature measurement of 560 Hz, and a low temperature measurement value of 520 Hz.
[0045]
The trimming operation in this case is the difference
Frequency at high temperature-upper limit value = 560-540 = 20 (Hz) (A)
Low temperature frequency-lower limit value = 520-460 = 60 (Hz) (B)
Therefore, the average of the difference between the upper limit value and the lower limit value is
(A + B) / 2 = 40 Hz, and the trimming correction is performed at 40 Hz as shown in FIG. Obviously, it can be realized by correcting the oscillation characteristics of a normal oscillation circuit instead of the ring oscillator circuit.
[0046]
FIG. 11 is a graph for explaining the fifth embodiment of the present invention. In this case, trimming correction is realized by correcting the detection level value of the POC (power on clear) circuit instead of the power regulator circuit. For example, the upper limit value of the detection voltage of the power-on-clear circuit is 1.6V, the lower limit value is 1.4V, the detection value at high temperature is 1.65V, and the detection value at low temperature is 1.6V.
[0047]
The trimming operation in this case is the difference
Detection voltage at high temperature-upper limit value = 1.65-1.6 = 0.05 V (A)
Detection voltage at low temperature-lower limit value = 1.6-1.4 = 0.2 V (B)
Therefore, the average of the difference between the upper limit value and the lower limit value is
(A + B) /2=0.125V, and the trimming correction is performed at 0.125V as shown in FIG.
[0048]
【The invention's effect】
As described above, according to the method of the present invention, the measurement values under different conditions are written in the internal storage circuit as in the flow of FIG. 6, and the different conditions are written in the second (final) step. Since the measured value at the point is calculated based on a predetermined calculation formula and the trimming value is determined, the product specifications have not been achieved and stable product shipment can be achieved if there is a difference in the characteristics between the prototype evaluation product and the mass-produced product. It is possible to solve the problem that is not present at the same time and to carry out stable and high-precision product shipment. In addition, high-accuracy design and verification that fully considers manufacturing variations and temperature dependence are not necessary at the design stage, which was necessary in the past, and the optimal trimming value is fully examined based on the evaluation results of the prototype. There is also an advantage that efficiency is improved from design to commercialization.
[Brief description of the drawings]
FIGS. 1A and 1B are an inspection flowchart for explaining an embodiment of the present invention and a flowchart at the time of trimming thereof.
FIG. 2 is a block diagram of an IC that implements the embodiment of FIG. 1;
FIG. 3 is a flowchart for explaining a manufacturing process in the embodiment of FIG. 1;
FIG. 4 is a temperature characteristic diagram of an output voltage in Trimming Example 1 of the present embodiment.
FIG. 5 is a temperature characteristic diagram of an output voltage of a specific trimming example 2 of the present embodiment;
FIG. 6 is a temperature characteristic diagram of an output voltage of a specific trimming example 2 of the present embodiment;
FIG. 7 is a block diagram of an IC for explaining a specific example of the embodiment of FIG. 2;
FIG. 8 is an inspection flowchart for explaining a second embodiment of the present invention.
FIG. 9 is a temperature characteristic diagram at the time of trimming for explaining a third embodiment of the present invention;
FIG. 10 is a temperature characteristic diagram at the time of trimming for explaining a fourth embodiment of the present invention;
FIG. 11 is a temperature characteristic diagram at the time of trimming for explaining a fourth embodiment of the present invention;
FIG. 12 is a circuit diagram of an example of a circuit that performs trimming according to a conventional example.
FIG. 13 is a flowchart for explaining a manufacturing process during general trimming.
[Explanation of symbols]
1 Power supply regulator circuit
2,21 Trimming circuit
3 Test circuit
4 I / O port circuit
5 Nonvolatile memory elements
6 Internal bus
7 I / O terminals
8 CPU
9 Memory element for trimming
10, 10a wafer
11, 11a Product sample
22 Constant voltage circuit
S11-S37 Inspection flow
S101-S110 Manufacturing flow

Claims (6)

A semiconductor integrated circuit having a trimming target circuit whose characteristics are adjusted by the trimming circuit, and having nonvolatile storage means for storing first measurement data which is an output characteristic of the trimming target circuit under a first measurement condition The trimming circuit is second measurement data which is output characteristics of the trimming target circuit measured under a second measurement condition after measurement of the first measurement data and the first measurement data from the nonvolatile storage means. And adjusting the output characteristics of the circuit to be trimmed based on the above . A trimming method for a semiconductor integrated circuit having a trimming target circuit whose characteristics are adjusted by a trimming circuit, wherein first measurement data which is an output characteristic of the trimming target circuit under a first measurement condition is stored in a nonvolatile storage means. And a first characteristic of the trimming target circuit measured under a second measurement condition after the measurement of the first measurement data and the first measurement data from the nonvolatile storage means. And a second procedure for adjusting the output characteristics of the circuit to be trimmed by the trimming circuit based on measurement data. A semiconductor integrated circuit having a trimming target circuit whose characteristics are adjusted by a trimming circuit, the first measurement data being the output characteristics of the trimming target circuit under a first measurement condition, and the trimming target under a second measurement condition Non-volatile storage means for storing second measurement data as output characteristics of the circuit, respectively, and the trimming circuit is based on the first measurement data and the second measurement data from the non-volatile storage means. A semiconductor integrated circuit characterized by adjusting output characteristics of a circuit to be trimmed . A trimming method for a semiconductor integrated circuit having a trimming target circuit whose characteristics are adjusted by a trimming circuit, wherein first measurement data which is an output characteristic of the trimming target circuit under a first measurement condition is stored in a nonvolatile storage means. A second procedure for storing second measurement data, which is output characteristics of the circuit to be trimmed under a second measurement condition, in the nonvolatile storage means; and And a third procedure for adjusting the output characteristics of the circuit to be trimmed by the trimming circuit based on the first measurement data and the second measurement data. A trimming method for a semiconductor integrated circuit having a trimming target circuit whose characteristics are adjusted by a trimming circuit, wherein first measurement data that is an output characteristic of the trimming target circuit under a first measurement condition is obtained in a first inspection step. A first procedure stored in the non-volatile storage means; a second measurement data obtained by measuring an output characteristic of the circuit to be trimmed under a second measurement condition in a second inspection step; and the second measurement data from the non-volatile storage means. And a second procedure for adjusting the output characteristics of the trimming target circuit by the trimming circuit based on one measurement data. 4. The semiconductor integrated circuit according to claim 1, wherein the first measurement condition and the second measurement condition are temperature, voltage, or frequency.

Images