JP3769700B2 - Clock extraction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock extraction circuit that extracts an electrical clock signal from an optical signal in an optical transmission system.
[0002]
[Prior art]
In recent years, with the widespread use of the Internet and the like, the transmission capacity of the trunk line is required to increase more and more. In order to meet these demands, studies on terabit-class optical transmission systems using wavelength division multiplexing technology have been actively conducted, and research and development for ultra-high speed is also underway in optical transceivers. Among these, optical receivers use optical signals to compensate for waveform distortion due to dispersion during optical fiber transmission and deterioration of transmission characteristics due to optical amplifier noise in repeaters and terminal stations. A timing function is required.
[0003]
Among these, the extraction of the clock signal necessary for the retiming function is usually performed in the electrical stage using a relatively large circuit such as a PLL configuration. However, the operation of these electric circuits greatly depends on the performance of the transistor, and as the operation speed is increased, the power consumption increases and it is difficult to realize an ultrahigh-speed operation of about 100 Gbit / s or more. Expected. In addition, an external loop filter having a large time constant and requiring precise adjustment is required, and there is a problem that complete integration is difficult.
[0004]
In order to overcome the limitations of this electric circuit, an opto-electric clock extraction circuit using a light injection locking oscillator in which a light receiving element and an electric oscillator are combined has been devised. A conventional example (Electron Lett., Vol. 34, No. 14, pp. 1424-1425, July 1998) composed of an individual light receiving element 5 for receiving an optical signal from the optical fiber 1 and an electric injection locking oscillator 6 is used. FIG. 13 shows a conventional example in which an optical signal from the optical fiber 1 is directly input to an active element (phototransistor) (not shown) in the light injection synchronous oscillator 2 (IEEE Trans. Microwave Theory Tech., Vol. 49, pp. 1921- 1925, Oct. 2001) is shown in FIG.
[0005]
These conventional examples have a high-speed and broadband optical interface compared to electricity, so they can operate at high speed compared to all electrical circuits, have a large time constant, and require external adjustment. Since a loop filter is not required, the configuration is simple and low power consumption is easy to achieve.
[0006]
[Problems to be solved by the invention]
However, when optical data signals composed of various frequency components are input, the electrical signals photoelectrically converted by the light receiving element 5 in FIG. 13 and the phototransistor (not shown) in the light injection synchronous oscillator 2 in FIG. In addition to the clock signal frequency component, a signal having a very wide frequency component from DC to the bit rate frequency is included. Along with this, there is a problem that not only a few of these frequency components exist in the output of the oscillator, but also the jitter of the extracted clock signal increases.
[0007]
An object of the present invention is to solve the above-mentioned conventional problems and to provide a circuit configuration capable of greatly reducing jitter in a clock extraction circuit using an electric or light injection locking oscillator.
[0008]
[Means for Solving the Problems]
The invention according to claim 1 oscillates at a frequency in the vicinity of 1 / n or n times the bit rate of the optical signal (where n = 1, 2, 3,...) And inputs the optical signal. an optical injection locking oscillator for outputting a clock signal synchronized with the optical signal, comprising a high-pass type provided on the output side of the optical injection locking oscillator filter, the filter is a low-pass with passing said clock signal A clock extraction circuit in which a cut-off frequency is set to 1/3 or more of the frequency of the clock signal , wherein the filter is formed of any one of a spiral inductor, a MIM capacitor, a microstrip line, and a coplanar line, and the light injection synchronous oscillator In addition , the clock extraction circuit is characterized by being monolithically integrated on a semiconductor substrate .
[0009]
The invention according to claim 2 is a photoelectric conversion means for converting an optical signal into an electrical signal, and the vicinity of 1 / n or n times (where n = 1, 2, 3,...) Of the bit rate of the optical signal. An oscillator that oscillates at a frequency of the same, inputs an electrical signal generated by the photoelectric converter and outputs a clock signal synchronized with the electrical signal, and a high-pass type provided on at least one of the input side or the output side of the oscillator A clock extracting circuit that allows the clock signal to pass therethrough and sets a low-frequency cutoff frequency to 1/3 or more of the frequency of the clock signal , wherein the filter is a spiral inductor, MIM capacitor Monolithic integration on a semiconductor substrate together with the photoelectric conversion means and the oscillator And a clock extraction circuit, characterized in that it is.
[0010]
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the first optical distribution means for distributing the input optical signal to the first and second optical signals, and the second optical signal as the first optical signal. An optical delay means for causing the optical carrier to be out of phase with respect to the first optical signal and delaying the optical signal by more than 0 bit and less than 2 bits; and delayed by the first optical signal and the optical delay means In addition, the clock extraction circuit includes an optical interferometer having an optical combining unit that combines the second optical signal.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a diagram showing a clock extraction circuit according to the first embodiment of the present invention. This embodiment relates to claim 1. This clock extraction circuit is an optical injection locking oscillator that self-oscillates at a frequency in the vicinity of 1 / n or n times the bit rate of the optical signal of the optical transmission system (where n = 1, 2, 3,...). 2 and a high-pass filter 3 that passes the clock signal frequency. Reference numeral 1 denotes an optical fiber.
[0012]
Here, the light injection synchronous oscillator 2 is, for example, as a negative resistance element of a microwave oscillator as described in “IEEE Trans. Microwave Theory Tech., Vol. 49, pp. 1921-1925, Oct. 2001”. In the configuration using the phototransistor 21 (FIG. 3), when the transmission bit rate frequency is within the lock range of the light injection synchronous oscillator 2, an electric clock signal synchronized with the optical signal can be extracted.
[0013]
However, the optical signal includes a signal having a very wide frequency component from DC to the bit rate frequency regardless of the sign of RZ, NRZ or the like. In particular, the lower the frequency, the higher the level, and there is a concern that jitter increases due to the leakage component.
[0014]
Here, since the high-pass filter 3 has a characteristic of passing the clock signal frequency band, it is possible to filter unnecessary low-frequency components in the clock signal, and as a result, it is possible to reduce jitter. In addition, since the high-pass filter required for this apparatus does not have to have a steep cutoff characteristic (= high Q value), a semiconductor using a lumped constant element such as a spiral inductor or MIM capacitor or a distributed constant element using a transmission line. It can be easily realized on a substrate, can be monolithically integrated with the light injection synchronous oscillator 2, and can contribute to downsizing and no adjustment of the apparatus.
[0015]
FIG. 2 is a modification of the first embodiment, and is different in that a band-pass filter 4 that passes the clock signal frequency is applied instead of the high-pass filter 3 in FIG. By applying the bandpass filter 4 in this way, in addition to signal components less than the clock frequency, frequency components higher than the clock frequency present in the digital signal can be suppressed, and jitter can be further reduced. It becomes.
[0016]
[Second Embodiment]
FIG. 4 is a diagram showing a clock extraction circuit according to the second embodiment of the present invention. This embodiment relates to claim 2. The clock extraction circuit includes a light receiving element 5 that converts an optical signal transmitted through the optical fiber 1 into an electric signal, an electric injection locking oscillator 6 that self-oscillates at a frequency near the bit rate of the optical transmission system, and a clock signal frequency. And a high-pass filter 3 that passes through.
[0017]
Here, the electric injection locking oscillator 6 self-oscillates at a frequency in the vicinity of 1 / n or n times the bit rate of the optical signal (where n = 1, 2, 3,...), And the transmission bit rate frequency. Is within the lock range of the electric injection synchronous oscillator 6, the electric clock signal synchronized with the optical signal can be extracted.
[0018]
However, the electrical signal output from the light receiving element 5 includes a signal having a very wide frequency component from DC to the bit rate frequency regardless of the sign such as RZ and NRZ. In particular, the lower the frequency, the higher the level, and there is a concern that jitter increases due to the leakage component.
[0019]
Here, since the high-pass filter 3 has a characteristic of passing the clock signal frequency band, it is possible to filter unnecessary low-frequency components in the clock signal, and as a result, jitter of the clock signal output from the electric injection locking oscillator 6 Can be reduced. Further, since the high-pass filter 3 required for this apparatus does not have to have a steep cutoff characteristic (= high Q value), a lumped constant element such as a spiral inductor or an MIM capacitor or a distributed constant element using a transmission line is used. It can be easily realized on a semiconductor substrate, can be monolithically integrated with the electric injection synchronous oscillator 6 and the light receiving element 5, and can contribute to downsizing and no adjustment of the apparatus.
[0020]
FIG. 5 shows a first modification of the second embodiment, which is different in that a band pass filter 4 that allows a clock signal frequency to pass is used instead of the high pass filter 3 in FIG. By applying the bandpass filter 4 in this way, in addition to the signal component less than the clock frequency, a frequency component higher than the clock frequency present in the digital signal can be suppressed, and further jitter reduction is possible. Become.
[0021]
6 and 7 show second and third modifications of the second embodiment, and FIG. 6 corresponds to FIG. 4 and FIG. 7 corresponds to FIG. This modification is different in that the filter 3 or 4 is disposed between the light receiving element 5 and the electric injection locking oscillator 6, and unnecessary frequency components other than the clock signal component are removed from the input signal to the electric injection locking oscillator 6. As a result, the jitter of the clock signal output from the electric injection synchronous oscillator 6 can be reduced.
[0022]
FIG. 8 and FIG. 9 show the fourth and fifth modifications of the second embodiment, which are different in that the filter 3 or 4 is arranged at both the input and output of the electric injection locking oscillator 6. Here, FIG. 8 shows a configuration in which the high-pass filter 3 is arranged for both input and output, and FIG. 9 shows a configuration in which the high-pass filter 3 is arranged on the input side and the band-pass filter 4 is arranged on the output side. By applying two filters in this way, a further jitter reduction effect can be obtained. In addition, since the high-pass filter 3 is applied to the filter between the light receiving element 5 and the electric injection locking oscillator 6, the components from the light receiving element 5 to the electric injection locking oscillator 6 can be easily monolithically integrated. It has become.
[0023]
[Third Embodiment]
FIG. 10 is a diagram showing a clock extraction circuit according to the third embodiment of the present invention. This embodiment relates to claim 3. The clock extraction circuit includes a light injection locking oscillator 2 that self-oscillates at a frequency in the vicinity of 1 / n or n times the bit rate of the optical transmission system (where n = 1, 2, 3,...) And a clock signal. In addition to the high-pass filter 3 that passes the frequency, a Mach-Zehnder interferometer 7 is provided.
[0024]
Here, the light injection synchronous oscillator 2 is configured as shown in FIG. 3 using, for example, a phototransistor. When the transmission bit rate frequency is within the lock range of the light injection synchronous oscillator 2, an electric clock signal synchronized with the optical signal is extracted. It can be done. Further, the Mach-Zehnder interferometer 7 includes an optical distribution unit 71, an optical delay unit 72, and an optical combining unit 73. The optical delay unit 72 in the delay path is τ time (delay time τ exceeds 2 bits with respect to 2 bits). The optical signal is delayed by less than a bit (preferably 1/2 bit), and the optical combiner 73 combines the two optical signals of the delay path and the through path so that the optical carriers are in opposite phases.
[0025]
By adopting such a configuration, a clock signal component can be generated in the optical domain from an NRZ code having almost no clock signal frequency component (= transmission bit rate frequency component). It will be able to greatly improve. Therefore, it is possible to extract a clock signal with little jitter from an optical signal transmitted by the NRZ code. In this embodiment, the Mach-Zehnder interferometer 7 is provided in the configuration of the first embodiment shown in FIG. 1, but it can be applied to the configuration shown in FIG. The Mach-Zehnder interferometer 7 can be provided in the configuration shown in FIG. A Mach-Zehnder interferometer having such characteristics can be easily realized by a planar lightwave circuit (PLC) technology.
[0026]
[Other embodiments]
In all the above-mentioned embodiments, it is preferably monolithically integrated on a semiconductor substrate such as InP or hybrid integrated on a PLC platform. Thereby, further miniaturization of the apparatus is achieved.
[0027]
[Experimental example]
Most of the signal power transmitted by the NRZ code is distributed in a frequency region of 1/2 or less of the bit rate frequency. Therefore, a sufficient jitter suppression effect can be expected if the cutoff frequency fc on the low frequency side of the high-pass filter 3 or the band-pass filter 4 used in the clock extraction circuit is about 1/3 of the clock frequency or higher.
[0028]
FIG. 11 shows the calculation result of the insertion loss of the Butterworth high-pass filter. The calculation results of insertion loss at 2.5 GHz (1/4 of the clock frequency), 5 GHz (1/2 of the clock frequency), and 10 GHz (clock frequency) are shown assuming that the clock frequency is 10 GHz. The low frequency side 3 dB cutoff frequency fc is calculated with three parameters of 3.33 GHz (1/3 of the clock frequency), 5 GHz (1/2 of the clock frequency), and 7.5 GHz (3/4 of the clock frequency). went. FIG. 11A shows insertion loss of 2.5 GHz and 5 GHz, and FIG. 11B shows insertion loss of 10 GHz.
[0029]
When the number of filter stages is 2, the insertion loss at 2.5 GHz is 6.2 dB (3 dB cut-off frequency fc = each) as shown in the characteristics (5), (3), and (1) in FIG. 3.33 GHz), 12.3 dB (3 dB cutoff frequency fc = 5 GHz), 19.1 dB (3 dB cutoff frequency fc = 5 GHz). The insertion loss at 5 GHz is 0.8 dB (3 dB cutoff frequency fc = 3.33 GHz) and 3.0 dB, respectively, as shown in the characteristics of (6), (4), and (2) in FIG. (3 dB cutoff frequency fc = 5 GHz) and 7.8 dB (3 dB cutoff frequency fc = 5 GHz). Furthermore, the insertion loss at the clock frequency (10 GHz) is 0.05 dB (3 dB cutoff frequency fc = 3.33 GHz), 0.26 dB (3 dB cutoff frequency fc = 5 GHz), respectively, as shown in FIG. .19 dB (3 dB cutoff frequency fc = 7.5 GHz) Thus, it can be seen that the leakage data signal can be suppressed by the above-described setting of the cut-off frequency with almost no attenuation of the clock signal component.
[0030]
A filter having a cutoff characteristic corresponding to up to about three filter stages can be easily realized by a spiral inductor, MIM capacitor, microstrip line, or coplanar line formed on a semiconductor substrate. Monolithic integration is possible.
[0031]
FIG. 12 shows a measurement result (with a filter) obtained by actually making a prototype of the apparatus of the embodiment shown in FIG. 10 and extracting a clock from a 10.66 Gbit / s NRZ pseudorandom optical modulation signal. The low-pass 3 dB cutoff frequency fc of the high-pass filter is 4.3 GHz corresponding to about 2/5 of the clock frequency. For comparison, a measurement result (without filter) of a configuration in which no filter is applied is also shown. When the measurement result observed on the frequency axis is seen in FIG. 12 (a), the frequency component of about 5 GHz or less is applied to the output signal from the light injection locking oscillator 2 by applying the filter as compared with the case without the filter. (It is a case where the characteristic of the light color is no filter). When the result of observing both on the time axis is seen in FIG. 12B, it can be confirmed that the jitter is greatly reduced by applying the filter, and the effect of the present invention is proved.
[0032]
【The invention's effect】
As described above in detail, the clock extraction circuit according to the present invention includes a light injection locking oscillator or a combination of a light receiving element and an electric injection locking oscillator, a low-frequency cutoff frequency of 1/3 or more of the clock signal frequency, and a clock signal. It is constituted by a high-pass type or band-pass type filter that passes through. For this reason, it is possible to suppress a high-level frequency component, particularly less than the clock frequency, included in the transmitted signal, and to reduce the jitter of the extracted clock signal. Furthermore, since a sufficient effect can be obtained even with a filter having a low Q value, monolithic integration including an oscillator is extremely easy, contributing to downsizing, economy, low power consumption, and no adjustment of the device. be able to.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a clock extraction circuit according to a first embodiment of this invention.
FIG. 2 is a configuration diagram of a clock extraction circuit according to a modification of the first embodiment.
FIG. 3 is a configuration diagram of a light injection synchronous oscillator.
FIG. 4 is a configuration diagram of a clock extraction circuit according to a second embodiment of this invention.
FIG. 5 is a configuration diagram of a clock extraction circuit according to a first modification of the second embodiment;
FIG. 6 is a configuration diagram of a clock extraction circuit according to a second modification of the second embodiment.
FIG. 7 is a configuration diagram of a clock extraction circuit of a third modified example of the second embodiment.
FIG. 8 is a configuration diagram of a clock extraction circuit of a fourth modification example of the second embodiment;
FIG. 9 is a configuration diagram of a clock extraction circuit of a fifth modification example of the second embodiment;
FIG. 10 is a configuration diagram of a clock extraction circuit according to a third embodiment of this invention.
11A is a characteristic diagram of insertion loss of a high-pass filter with cutoff frequencies of 3.33 GHz, 5 GHz, and 7.5 GHz when the input signal frequency is 2.5 GHz and 5 GHz, and FIG. 11B is an input signal frequency. It is a characteristic figure of the insertion loss of the high pass filter whose cutoff frequency at the time of 10 GHz is 3.33 GHz, 5 GHz, and 7.5 GHz.
FIG. 12 is a characteristic diagram when a 10.66 Gbit / s NRZ pseudo-random optical modulation signal is input, (a) is a characteristic diagram seen on the frequency axis, and (b) is a characteristic diagram seen on the time axis.
FIG. 13 is a configuration diagram of a conventional clock extraction circuit.
FIG. 14 is a configuration diagram of another conventional clock extraction circuit.
[Explanation of symbols]
1: optical fiber, 2: light injection locking oscillator, 21: phototransistor, 3: high pass filter, 4: band pass filter, 5: light receiving element, 6: electric injection locking oscillator, 7: Mach-Zehnder interferometer.

Claims (3)

A clock signal that oscillates at a frequency in the vicinity of 1 / n or n times the bit rate of the optical signal (where n = 1, 2, 3,...) And is synchronized with the optical signal by inputting the optical signal. an optical injection locking oscillator for outputting a light injected and a high pass type filter provided on the output side of the synchronous oscillator, the filter frequency of the clock signal cut-off frequency of the low frequency with passing said clock signal A clock extraction circuit set to 1/3 or more of
A clock extraction circuit , wherein the filter is formed of any one of a spiral inductor, a MIM capacitor, a microstrip line, and a coplanar line, and is monolithically integrated on a semiconductor substrate together with the light injection synchronous oscillator . Photoelectric conversion means for converting an optical signal into an electrical signal; and oscillation at a frequency in the vicinity of 1 / n or n times the bit rate of the optical signal (where n = 1, 2, 3,...) comprising an oscillator for outputting a clock signal synchronized with the electrical signal by inputting the electrical signals generated by the transducer, and a high-pass type filter provided in at least one of the input side or output side of the oscillator, the filter Is a clock extraction circuit that allows the clock signal to pass through and sets a low-frequency cutoff frequency to 1/3 or more of the frequency of the clock signal ,
A clock extraction circuit , wherein the filter is composed of any one of a spiral inductor, a MIM capacitor, a microstrip line, and a coplanar line, and is monolithically integrated on a semiconductor substrate together with the photoelectric conversion means and the oscillator . In claim 1 or 2,
First optical distribution means for distributing an input optical signal into first and second optical signals;
An optical delay means for delaying the second optical signal by an amount of time in which the optical carrier is in reverse phase with respect to the first optical signal and exceeds 0 bit and less than 2 bits of the optical signal;
A clock extraction circuit comprising: an optical interferometer having an optical combining unit that combines the first optical signal and the second optical signal delayed by the optical delay unit.

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