JP3769832B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
Relates to a manufacturing method of the present invention is a semiconductor device, more particularly, to a method of manufacturing a semiconductor device characterized by a gate electrode structure of the MOS transistor.
[0002]
[Prior art]
In a conventional MOS type semiconductor device, a polycrystalline silicon film (polysilicon film) in which impurities such as phosphorus are diffused has been used as a gate electrode material. However, in recent years, with the increase in the speed and integration of MOS type semiconductor devices, the resistance of the polysilicon film is large, so that the signal propagation speed becomes a problem, and it is difficult to achieve high speed of the MOS type semiconductor device. It has become to.
Also, due to the demand for higher integration of MOS type semiconductor devices, the source / drain diffusion layer of a miniaturized short channel MOS type transistor becomes increasingly thinner and a shallow PN junction trench structure is required. The resistance increases, and this has become an obstruction requirement for semiconductor devices aiming at higher integration and higher speed.
[0003]
As one of the means for solving the above problems, a polysilicon film of a polysilicon gate electrode for which a technique for obtaining a good Si-SiO ₂ interface state has been established, and the purpose of reducing the resistance of the gate electrode A source / drain structure in which a polycide gate film using a composite metal silicide film, usually a composite film with a refractory metal silicide film, is used as the gate electrode, and a refractory metal silicide layer is also formed on the source / drain diffusion layer The MOS type semiconductor device was developed. As this refractory metal silicide, titanium silicide (TiSi ₂ ) having the smallest specific resistance is considered most promising.
The sheet resistance of the polysilicon gate electrode by conventional thickness 30 [Omega / □ on the order, also, the sheet resistance of the source-drain diffusion layers of a shallow PN junction is a 100 [Omega / □ extent, Ya gate electrode TiSi ₂ film By forming the source / drain diffusion layers, the sheet resistance can be set to 2 to 5Ω / □.
[0004]
By using the TiSi ₂ film as described above, the sheet resistance of the gate electrode and the source / drain diffusion layer can be reduced, but there are the following problems.
Polycide gate electrode formation using a TiSi ₂ film as a refractory metal silicide film is performed by depositing a Ti film on the polysilicon film and performing a heat treatment to cause an alloy reaction between the polysilicon film and the Ti film. Only the upper part of the film is a TiSi ₂ film, but at the time of this alloy reaction, the diffusion of Ti along the grain boundary proceeds faster than the diffusion of Ti in the polycrystalline polysilicon film, Ti reaches a gate oxide film in a part of the polysilicon film and diffuses into the gate oxide film to cause a problem of deterioration of the gate electrode breakdown voltage. In addition, a significant portion under the polycide gate electrode causes TiSi ₂ If the film is state to contact with the gate oxide film occurs, the work function phi _M and the doped polysilicon film and TiSi ₂ film differences and, in MOS transistors other Si-SiO ₂ interfacial state change such as Problem of changing the threshold voltage V _TH is or generated.
[0005]
A gate electrode portion of a MOS transistor having a polycide gate electrode in a state in which a TiSi ₂ film reaching a gate oxide film at a part of the polysilicon film is formed by diffusion of Ti along the crystal grain boundary described above is shown. This is shown in FIG. The polycide gate electrode by conventional TiSi ₂ film, the boundary surface between the polysilicon film and TiSi ₂ film, although there are some irregularities to the influence of the early diffusion along the grain boundaries of Ti, schematic planar boundary surfaces However, there are often polycide gate electrode MOS transistors that have an abnormally grown portion of the TiSi ₂ film until it reaches the inside of the polysilicon film or reaches the gate oxide film as shown in FIG. In general, such a MOS transistor causes breakdown voltage deterioration.
On the other hand, impurity ions doped in the polysilicon film, such as As, may be diffused into the TiSi ₂ film during the alloy reaction, which may increase the sheet resistance.
[0006]
As a countermeasure against the above problems, a semiconductor device including a MOS transistor having a gate electrode trench structure using a polycide film composed of a polycrystalline silicon film, a diffusion prevention film, and a refractory metal silicide film, and a conventional example of a manufacturing method thereof, This will be described with reference to FIGS.
First, as shown in FIG. 4 (a), selectively forming a LOCOS (Local Oxidation of Silicon) film 12 as a field oxide film on a semiconductor substrate 11 of P-type. Thereafter, a gate oxide film 13 is formed on the MOS transistor portion 1 by a thermal oxide film. Thereafter, a first polysilicon film 14 doped with impurities is deposited to a thickness of about 150 nm.
[0007]
Next, a Si0 ₂ film diffusion prevention film 15 by CVD SiO ₂ film or SiN film, or the like, or by a CVD method, by heat treatment.
Since these diffusion prevention films 15 are insulating films, the film thickness of the diffusion prevention film 15 is set to 0. 0 in order to ensure conductivity between the first polysilicon film 14 and the second polysilicon film 16 described later. A tunnel current is used as a thin film of about 6 nm to 3 nm.
Next, a second polysilicon film 16 doped with impurities is deposited to a thickness of about 150 nm.
[0008]
Next, as shown in FIG. 4B, the second polysilicon film 16 / diffusion preventive film 15 / first polysilicon film 14 / gate oxide film 13 are patterned using a photolithography technique to form a MOS transistor. A gate electrode portion 2 is formed in the portion 1. Thereafter, in order to form an LDD (Lightly Doped Drain) layer 18 which will be described later, low dose ion implantation using As ions is performed on the source / drain portion 3 by ion implantation.
Then, deposited by Ri CVD oxide film in the CVD method, followed by RIE (Reactive Ion Etching) using an anisotropic etching method using such a CVD oxide film is etched back, side walls of the gate electrode 2 A wall oxide film 17 is formed. Thereafter, in order to form a source / drain layer to be described later, high dose ion implantation using As ions is performed on the source / drain portion 3 by ion implantation. Further, after that, heat treatment is performed for both activation and diffusion of As ions implanted into the source / drain portion 3 to form the source / drain layer 19 having the LDD layer 18.
[0009]
Next, as shown in FIG. 4 (c), deposited by Ri Ti film sputtering, then, RTA by (Rapid Thermal Annealing) method, in a nitrogen atmosphere, the first heat treatment temperature of about 650 ° C Then, TiSi ₂ films 20 and 21 are formed on the surface of the second polysilicon film 16 of the gate electrode part 2 and the surface of the source / drain layer 19 of the source / drain part 3 where the Ti film is in contact with silicon.
Next, the TiN film on the surface of the Ti film such as on the insulating film and the unreacted Ti film formed inside by this RTA are removed with a mixed solution of sulfuric acid and hydrogen peroxide solution. Thereafter, a _second heat treatment at a temperature of about 800 ° C. is performed for the purpose of reducing the resistance of the TiSi ₂ films 20 and 21. The heat treatment of this twice, the gate electrode 2 and the source and drain portions 3, a self was aligned manner is silicided, so-called salicide (S elf- Ali gned Sili cide) was of a low resistance TiSi ₂ film 20 , 21 are formed.
Here, the TiSi ₂ films 20 and 21 formed by the first heat treatment at a temperature of about 650 ° C. are TiSi ₂ crystals called a C49 phase having a low-temperature stable phase and a high resistance. The TiSi ₂ films 20 and 21 formed by the heat treatment 2 are TiSi ₂ crystals called a C54 phase having a high temperature stable phase and low resistance.
[0010]
Next, as shown in FIG. 5, an interlayer insulating film 22 made of BPSG (Boro-Phospho Silicate Glass) or the like is deposited, and the surface of the interlayer insulating film 22 is planarized by a reflow method, CMP (Chemical Mechanical Polishing), or the like. Thereafter, the interlayer insulating film 22 is patterned to form contact hole openings 23 in the source / drain portions 3 and the like of the MOS transistor portion 1.
[0011]
Next, a Ti film and a TiN film are deposited as a barrier film 24 by a sputtering method or the like, and then a blanket W film 25 is deposited by a CVD method, and then etch back is performed as an embedded plug in the opening 23 of the contact hole. The tungsten plug 26 is formed.
Next, a TiN film 27 and an Al alloy film 28 containing Si are deposited, and then patterned to form a wiring 29 connected to the tungsten plug 26 and the like.
Thereafter, although illustration is omitted, a semiconductor device is manufactured by forming a passivation film, opening a pad window, and the like.
[0012]
However, in the semiconductor device and the manufacturing method thereof described above, the thickness of the diffusion preventing film 15 inserted between the first polysilicon film 14 and the second polysilicon film 16 of the gate electrode is so small that a tunnel current flows. It is extremely difficult to form a film having such a homogeneity that the anti-diffusion effect can be reliably expected with such a thin film.
Therefore, the thickness of the first polysilicon film 14 and the second polysilicon film 16 is increased to about 150 nm as in this conventional example, and only the surface portion of the second polysilicon film 16 is TiSi _2. and film 20, to lower the probability of abnormal formation of the TiSi ₂ when TiSi ₂ film 20 is formed and the heterogeneity of (see FIG. 3) and the diffusion preventing film 15 overlap, the abnormal formation of the TiSi ₂ film 20 is the gate oxide The effect of preventing deterioration of the gate electrode breakdown voltage is improved so as not to reach the film 13.
For the reasons described above, the gate electrode film becomes thicker, and it becomes difficult to satisfy the demand for size reduction in the direction perpendicular to the surface of the semiconductor substrate accompanying element miniaturization due to higher integration of the semiconductor device. There is a problem that makes it difficult.
[0013]
[Problems to be solved by the invention]
An object of the present invention is to solve the problems in the method for manufacturing a semiconductor device described above. That is, the problem of the present invention is that even if the polycide gate electrode film thickness is reduced by the polycide film composed of the polycrystalline silicon film, the diffusion prevention film, and the metal silicide film, the gate electrode breakdown voltage degradation and the threshold voltage V _TH are reduced. An object of the present invention is to provide a method of manufacturing a semiconductor device including a MOS transistor having a polycide gate electrode structure without any change.
[0014]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device of the present invention, Ru der proposes to solve the problems described above.
[0015]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a gate electrode structure MOS transistor including a polycrystalline silicon film, a diffusion prevention film, and a metal silicide film. Forming a silicon film; depositing a refractory metal nitride film as a diffusion preventing film on the first silicon film; forming a second silicon film on the refractory metal nitride film; The second silicon film / refractory metal nitride film / first silicon film / gate oxide film are patterned to form a gate electrode portion, a refractory metal film is deposited, and heat treatment is performed to form a gate. a second silicon film and the source and drain portions of the electrode portion and the refractory metal film is an alloy reaction, and a step of forming a silicide film, in the step of forming the silicide film The silicide leaving unreacted refractory metal film on the membrane, unreacted refractory metal on said silicide film of the source and drain portions while all the silicide film using the second silicon layer of the gate electrode portion It is characterized by not leaving a film.
[00 16 ]
According to the present invention, in a MOS transistor having a gate electrode structure composed of a polycrystalline silicon film, a diffusion prevention film, and a metal silicide film, the diffusion prevention film is made of a refractory metal nitride film, whereby the conductivity of the diffusion prevention film is increased. Since a tunnel current is not used for securing, the film thickness of the diffusion preventing film can be increased, so that the diffusion of the refractory metal can be almost certainly prevented during the silicidation alloy reaction. Therefore, it is possible to manufacture a MOS transistor having a polycide gate electrode structure in which the polycide gate electrode breakdown voltage is not deteriorated and the threshold voltage V _TH is not changed.
Further, since the diffusion prevention film made of the refractory metal nitride film can almost certainly prevent the diffusion of the refractory metal, the thickness of the first and second silicon films can be reduced, so that the polycide gate electrode The overall thickness of the semiconductor device can be reduced, and a highly integrated semiconductor device can be manufactured in order to meet the demand for size reduction in the direction perpendicular to the surface of the semiconductor substrate accompanying the miniaturization of elements due to high integration of the semiconductor device.
[00 17 ]
【Example】
Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. Components similar to those in FIGS. 4 and 5 referred to in the description of the prior art are denoted by the same reference numerals.
[00 18 ]
This embodiment is an example of applying the present invention to the manufacturing method of the semiconductor device will be described which with reference to FIGS.
First, as shown in FIG. 1A, a LOCOS film 12 as a field oxide film is selectively formed on a P-type semiconductor substrate 11. Thereafter, a gate oxide film 13 having a thickness of about 20 nm is formed on the MOS transistor portion 1 by a thermal oxide film.
Next, a first silicon film, for example, a first amorphous silicon film 31 doped with P (hereinafter referred to as a first a-Si film 31) is formed by a CVD method using a vertical LPCVD apparatus or the like. Deposit about 50 nm thick. The CVD conditions for the first a-Si film 31 are, for example, as follows.
[CVD conditions for first a-Si film 31]
SiH ₄ gas flow rate:: 500 sccm
PH ₃ gas flow rate: 0.35 sccm
Gas pressure: 133 Pa
Temperature: 533 ° C
[00 19 ]
Next, a refractory metal nitride film, for example, a TiN film 32 as a diffusion preventing film is deposited by sputtering to a thickness of about 30 nm. The TiN film 32 is deposited using, for example, a magnetron sputtering apparatus under the following reactive sputtering conditions.
[Reactive sputtering condition of TiN film 32]
N ₂ gas flow rate: 100 sccm
Gas pressure: 1 Pa
Substrate temperature: 200 ° C
Power supply: 6 kW
[00 20 ]
Next, a second silicon film, for example, a second amorphous silicon film 33 doped with P (hereinafter referred to as a second a-Si film 33) is formed by a CVD method using a vertical LPCVD apparatus or the like. Deposit about 50 nm thick. The CVD apparatus and CVD conditions for the second a-Si film 33 are the same as, for example, when the first a-Si film 31 is deposited.
[00 21 ]
Next, as shown in FIG. 1B, the second a-Si film 33 / TiN film 32 / first a-Si film 31 / gate oxide film 13 are patterned using a photolithography technique, A gate electrode portion 2 of the MOS transistor portion 1 is formed. Etching at the time of forming the gate electrode portion 2 uses an ECR plasma etching apparatus, and the etching conditions are as follows, for example.
[Etching conditions when forming the gate electrode 2]
Cl ₂ gas flow rate: 100 sccm
O ₂ gas flow rate: 100 sccm
Gas pressure: 0.4 Pa
Substrate temperature: 20 ° C
First step RF power: 80 kW
Second step RF power: 30 kW
[00 22 ]
Next, in order to form an LDD (Lightly Doped Drain) layer to be described later, ions are implanted into the source / drain portion 3 by ion implantation, for example, using As ions, with an implantation energy of about 25 keV and a dose of about 5E13 / cm ^2. Make an injection.
[00 23 ]
Next, a CVD oxide film having a film thickness of about 300 nm is deposited by the CVD method, and then the CVD oxide film is etched back by using an anisotropic plasma etching method such as RIE. A wall oxide film 17 is formed.
Thereafter, a thermal oxide film (not shown) is formed on the surface of the source / drain portion 3 and the surface of the second a-Si film 33 of the gate electrode portion 3 to a thickness of about 10 nm, and then the MOS transistor portion 1 is formed by ion implantation. The source / drain portion 3 is subjected to ion implantation for forming a source / drain layer to be described later. This ion implantation is performed using, for example, As ions, with an implantation energy of about 20 keV and a dose of about 2E15 / cm ² . The implantation energy value is desirably set so that the projected range Rp is closer to the surface side than the center of the second a-Si film 33.
[00 24 ]
Next, a heat treatment for activating and diffusing the implanted ions, for example, a heat treatment for about 30 seconds at about 1000 ° C. by the RTA (Rapid Thermal Annealing) method is performed to form the source / drain layers 19 having the LDD layers 18. To do.
Thereafter, the thermal oxide film on the surface of the second a-Si film 33 of the gate electrode portion 2 and the surface of the source / drain layer 19 of the source / drain portion 3 is removed with a diluted hydrofluoric acid solution.
It should be noted that the first and second a-Si films 31 and 33 are polycrystallized after the thermal oxide film and the heat treatment process such as activation described above, and at this stage, the first a-Si films 31 and 33 are changed to polysilicon films. .
[00 25 ]
Next, as shown in FIG. 1C, a refractory metal such as a Ti film is deposited to a thickness of about 40 nm by sputtering. Thereafter, a first heat treatment in a nitrogen gas atmosphere by the RTA method is performed at about 650 ° C. for about 30 seconds.
By this heat treatment, the second a-Si film 33 of the gate electrode part 2 and the silicon of the source / drain part 3 cause an alloy reaction with the Ti film, and the Ti film is a silicon layer having a thickness of about 2.3 times the Ti film thickness. It reacts with silicon to form a TiSi ₂ film about 2.5 times as thick as the Ti film thickness. Therefore, when the Ti film of this embodiment is about 40 nm, the source / drain portion 3 is formed with the TiSi ₂ film 35 of about 100 nm, and the gate electrode portion 2 is provided with the TiN film 32 as a diffusion preventing film. Therefore, the silicon of only the second a-Si film 33 that has become a polysilicon film reacts with the Ti film, and a TiSi ₂ film 34 of about 54 nm is formed.
At this time, only the Ti film having a thickness of about 22 nm on the second a-Si film 33 side is used for forming the TiSi ₂ film 34 and the remaining Ti film is unreacted Ti. It remains as a film.
The TiSi ₂ films 34 and 35 formed here are TiSi ₂ crystals called a C49 phase having a low temperature stable phase and a high resistance.
[00 26 ]
Next, the unreacted Ti film of the gate electrode portion 2 and the TiN film formed on the surface of the unreacted Ti film, the unreacted Ti film on the insulating film such as the sidewall oxide film 17 and the LOCOS film 12, and the The TiN film formed on the surface of the unreacted Ti film is removed with a selective etching solution in which sulfuric acid and hydrogen peroxide are mixed at a ratio of 3: 1.
Thereafter, a second heat treatment in a nitrogen gas atmosphere by the RTA method is performed at about 800 ° C. for about 30 seconds. By this heat treatment, cold TiSi ₂ films 34 and 35 is a TiSi ₂ crystals in the stable phase is said C49 phase of high resistance, TiSi ₂ film 34 is a TiSi ₂ crystals called C54 phase of low resistance at a high temperature stable phase , 35.
In this manner, low-resistance TiSi ₂ films 34 and 35 are formed as silicide films, so-called salicide films, formed in a self-aligned manner on the gate electrode portion 2 and the source / drain portions 3.
[00 27 ]
Next, as shown in FIG. 2, an interlayer insulating film 22 made of BPSG or the like is deposited, the surface of the interlayer insulating film 22 is flattened by a reflow method or CMP, and then the interlayer insulating film 22 is patterned to form a MOS transistor. Contact hole openings 23 are formed in the source / drain portions 3 and the like of the portion 1.
[0028]
Next, by depositing a Ti film and a TiN film as a barrier film 24 Ri by the sputtering method or the like, followed by depositing a blanket W film 25 Ri by the CVD method, followed by performing etch back, contact hole openings 23 A tungsten plug 26 is formed as an embedded plug.
Next, a TIN film 27 and an Al alloy film 28 containing Si are deposited, and then patterned to form a wiring 29 connected to the tungsten plug 26 and the like.
Thereafter, although illustration is omitted, a semiconductor device is manufactured by forming a passivation film, opening a pad window, and the like.
[00 29 ]
In the above-described embodiment of the present invention, the N-type MOS transistor having the polycide gate electrode has been described. However, a P-type MOS transistor having the polycide gate electrode can be similarly manufactured. Further, by combining the N-type MOS transistor forming step of the polycide gate electrode and the P-type MOS transistor forming step of the polycide gate electrode, it is possible to manufacture a semiconductor device having a polycide gate electrode formed with a CMOS trench.
In the above-described embodiment, the second a-Si film 33 in which the second silicon film is doped with impurities is used. However, as in the above-described embodiment, the second a-Si film 33 is entirely formed of TiSi _2. When a thick Ti film is used instead of the film 34, the second a-Si film 33 not doped with impurities may be used.
[0030]
Above semiconductor device, the diffusion preventing film is composed of a MOS transistor of the polycide gate electrode was TiN film 32, the film thickness of the TiN film 32 is also about 30 nm, 1 order of magnitude or more Ri good conventional diffusion preventing film 15 Since the film thickness is large, the effect of preventing diffusion of Ti to the first a-Si film 31 is large on the entire surface of the diffusion prevention film, and even if the first and second a-Si films 31 and 33 are thin, It is possible to manufacture a semiconductor device that does not deteriorate the gate electrode breakdown voltage or change the threshold voltage V _TH . Therefore, the film thickness of the polycide gate electrode of the MOS transistor can be made much thinner than that of the conventional polycide gate electrode, and a highly integrated semiconductor device can be manufactured.
[00 31 ]
Although the present invention has been described with reference to the embodiments, the present invention is not limited to the embodiments.
For example, in this embodiment, the TiN film is used as the diffusion preventing film, but a refractory metal nitride film such as a WN film or a MoN film may be used.
Further, although the amorphous silicon film doped with impurities has been described as the first and second silicon films, a polysilicon film doped with impurities may be used.
In addition, the process apparatus and process conditions can be changed as appropriate within the scope of the technical idea of the present invention.
[00 32 ]
【The invention's effect】
As is apparent from the above description, the method of manufacturing a semiconductor device according to the present invention uses a TiN film as a diffusion prevention film, so that even with a thin polycide gate electrode, gate electrode breakdown voltage degradation and threshold voltage V A MOS transistor having a polycide gate electrode with no change in _TH can be manufactured. Therefore, a highly integrated semiconductor device can be manufactured.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor device, illustrating the first half of the steps of an embodiment to which the present invention is applied, in the order of steps. FIG. 1 (a) is a gate oxide film, a first a-Si film, TiN on a semiconductor substrate. A state in which a film and a second a-Si film are formed, (b) a state in which a gate electrode portion is formed, a sidewall oxide film is formed, and a source / drain layer having an LDD layer is formed, (c) in FIG. In this state, a TiSi ₂ film is formed on the gate electrode portion and the source / drain portions.
FIG. 2 is a schematic cross-sectional view of a semiconductor device, illustrating the second half of the steps of an embodiment to which the present invention is applied, in the order of steps, in which an interlayer insulating film is formed, a tungsten plug is formed, and then a wiring is formed. .
FIG. 3 is a schematic cross-sectional view of a part of a MOS transistor part for explaining a gate electrode breakdown voltage deterioration phenomenon in a conventional polycide gate electrode MOS transistor without a diffusion prevention film.
4A and 4B are schematic cross-sectional views of a semiconductor device, illustrating the first half of the steps of a conventional method for manufacturing a semiconductor device in order of steps, wherein FIG. 4A is a gate oxide film, a first polysilicon film, and a diffusion prevention layer on a semiconductor substrate; A state in which a film and a second polysilicon film are formed, (b) is a state in which a gate electrode portion is formed, a sidewall oxide film is formed, and a source / drain layer having an LDD layer is formed, (c) is a gate In this state, a TiSi ₂ film is formed on the electrode part and the source / drain part.
FIG. 5 is a schematic cross-sectional view of a semiconductor device, illustrating the second half of the steps of a conventional method for manufacturing a semiconductor device in order of steps, in which an interlayer insulating film is formed, a tungsten plug is formed, and then a wiring is formed. .
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... MOS transistor part, 2 ... Gate electrode part, 3 ... Source / drain part, 11 ... Semiconductor substrate, 12 ... LOCOS film | membrane, 13 ... Gate oxide film, 14 ... 1st polysilicon film, 15 ... Diffusion prevention film, 16 ... second polysilicon film, 17 ... side wall oxide film, 18 ... LDD layer, 19 ... drain layer, 20, 21 ... TiSi ₂ film, 22 ... layer insulating film, 23 ... opening, 24 ... barrier Membrane, 25 ... Blanket W film, 26 ... Tungsten plug, 27 ... TiN film, 28 ... Аl alloy film, 29 ... Wiring, 31 ... First a-Si film, 32 ... TiN film, 33 ... Second a- Si film, 34, 35... TiSi ₂ film

Claims (1)

In a method of manufacturing a semiconductor device including a MOS transistor having a gate electrode structure formed of a polycrystalline silicon film, a diffusion prevention film, and a metal silicide film,
Forming a first silicon film on the gate oxide film;
Depositing a refractory metal nitride film as the diffusion preventing film on the first silicon film;
Forming a second silicon film on the refractory metal nitride film;
Patterning the second silicon film / the refractory metal nitride film / the first silicon film / the gate oxide film to form a gate electrode portion;
Depositing a refractory metal film;
A step of alloying the second silicon film and source / drain portions of the gate electrode portion with the refractory metal film by heat treatment to form a silicide film,
In the step of forming the silicide film, the second silicon film in the gate electrode portion is entirely made into a silicide film, and an unreacted refractory metal film is left on the silicide film, and the silicide in the source / drain portions is formed. A method for manufacturing a semiconductor device, wherein an unreacted refractory metal film is not left on the film.

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