JP3770201B2 - Image output device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a clock generation circuit for generating a clock having an arbitrary frequency.Output device withIt is about.
[0002]
[Prior art]
  In recent years, in the field of photographic processing, based on digital image data obtained by reading an image on a photographic film with a scanner or the like, printing is performed by irradiating photographic paper with red, green, and blue monochromatic light for each pixel. Digital exposure to be performed is performed. Various configurations for performing this digital exposure have been proposed. As an example, there is a configuration in which photographic paper is scanned and exposed while modulating laser light in accordance with digital image data. The image output apparatus having such a configuration includes a light source that generates laser beams of red, green, and blue, and performs a printing operation in the following procedure.
[0003]
  First, the image processing circuit outputs analog data whose amplitude is modulated based on the input digital image data of each color component. The intensity of the laser light of each color component is modulated by the analog data. Further, the modulated laser light of each color component is deflected in the main scanning direction by a deflector such as a polygon mirror, and is irradiated onto the photographic paper through an optical system such as an fθ lens. At the same time, scanning exposure is performed by transporting and moving the photographic paper in the sub-scanning direction, and a two-dimensional color image is printed on the photographic paper.
[0004]
  By the way, in the image output device, since the refractive index of the optical system such as the fθ lens is slightly different depending on the wavelength of the light, a phenomenon in which the focal lengths of the color components do not match in the laser light emitted from the fθ lens or the like. So-called chromatic aberration occurs. As a result, color misregistration occurs in the image reproduced on the photographic paper. In order to absorb such chromatic aberration, it is necessary to correct the chromatic aberration by finely adjusting the intensity of the laser beam for each color component. Therefore, conventionally, the reference clock for converting digital image data into analog data has been adjusted for each color component by finely adjusting the frequency for each color component to correct the chromatic aberration. It was. Therefore, the image processing circuit is required to have a configuration capable of adjusting the frequency of the reference clock at fine intervals as means for generating the reference clock. Here, DDS (Direct Digital Synthesizer) or PLL (Phase Looked Loop) can be considered as a configuration capable of adjusting the reference clock at fine intervals.
[0005]
[Problems to be solved by the invention]
  However, the DDS, due to its nature, requires a clock having a frequency three times that of the reference clock after frequency adjustment as a clock before frequency adjustment, which is not preferable for measures against EMI (Electro Magnetic Interference) in peripheral circuits. Occurs. On the other hand, the means having the PLL does not cause the above-described problem in the DDS. Further, it is advantageous in terms of cost to provide a PLL rather than a DDS in the image processing circuit. However, the PLL has the following problems.
[0006]
  Here, FIG. 5 shows a schematic configuration of a PLL provided in a conventional image processing circuit. In this PLL, if the pre-adjustment frequency of the reference clock is F (REF), the frequency division ratio is 1 / N, and the post-adjustment frequency F (OUT) of the reference clock is F (OUT) = N × F (REF). . Therefore, in order to adjust the frequency of the reference clock at fine intervals by the PLL, it is only necessary to make F (REF) as small as possible and increase the value that N can take as much as possible.
[0007]
  However, increasing the value that N can take increases the maximum value that N can take. Here, in the PLL, the jitter (frequency error) of the reference clock is also amplified N times as N increases. Therefore, if the value of N is set too large, the jitter of the adjusted reference clock increases. On the other hand, if F (REF) is made as small as possible, one cycle of F (REF) becomes longer, so that the interval for feeding back an error signal to a VCO (Voltage Controlled Oscillator), which is a component of the PLL, also becomes longer. . Therefore, when the voltage holding time is long in the VCO, the accuracy of the feedback control is lowered, and the jitter of the reference clock after frequency adjustment is increased. That is, if the frequency of the reference clock is adjusted at a fine interval by the PLL, the jitter increases, and this hinders the design and manufacture of the image processing circuit.
[0008]
  The present invention has been made in order to solve the above-described problems. The object of the present invention is to adjust the frequency that the output clock can take at fine intervals while suppressing the jitter (frequency error) amplified by the PLL. Clock generation)With circuitAn object is to provide an image output apparatus.
[0009]
[Means for Solving the Problems]
  In order to solve the above problems, the image output apparatus of the present invention modulates the intensity of each color light beam emitted from the light source for each color according to image data, and uses the modulated light beam as a photosensitive material. An image output apparatus for condensing, comprising: a clock generation circuit that generates a clock for performing intensity modulation of the light beam; and a computer that controls the clock generation circuit, wherein the clock generation circuit includes:Division ratio1 / mThe frequency of the PLL from which the clock is output from the first frequency dividing means whose frequency is variable is controlled by feedback, and the frequency of the clock of the original oscillation is controlled, and this clock is input to the PLL.1 / nA second frequency dividing means that is variable;The computer includes a memory that stores a table in which a frequency of a clock output from the PLL is associated with a combination of n and m so as to be the frequency, and a clock output from the PLL Means for inputting the frequency, means for detecting the frequency closest to the input frequency with reference to the table, and means for selecting a combination of n and m associated with the detected frequency And means for controlling the frequency dividing ratio of the first frequency dividing means and the second frequency dividing means in accordance with the selected combination of n and m.
[0010]
  In the above configuration, assuming that the frequency dividing ratio of the second frequency dividing means is 1 / n (n is a natural number) and the frequency of the original oscillation clock is f, the frequency of the clock input to the PLL is f / n. Further, when the frequency dividing ratio of the first frequency dividing means is 1 / m (m is a natural number), the PLL performs feedback control of the frequency of the clock from the first frequency dividing means, so the clock output from the PLL is mf / n. In other words, in the above configuration, the frequency of the clock can be controlled to m / n times, and by changing the frequency division ratio of the first frequency divider and the frequency division ratio of the second frequency divider, The frequency can be set in m × n ways.
[0011]
  On the other hand, the clock generation circuit having the conventional configuration includes a PLL, but the frequency of the clock input to the PLL is fixed. Therefore, when the frequency dividing ratio of the PLL frequency dividing means is 1 / N, Only N output clock frequencies can be set. Therefore, in order to adjust (high resolution) the frequency that the output clock can take at a fine interval with the clock generation circuit of the conventional configuration, the value that N can take must be increased and the clock of the original oscillation must be made low frequency. I must. However, there is a problem that the jitter (frequency error) of the output clock is amplified as the value of N is higher or the frequency of the original oscillation clock is lower.
[0012]
  Here, in the clock generation circuit of the present invention, since the frequency of the clock input to the PLL can be changed to n ways by the first frequency dividing means, the possible values of the frequency of the output clock from the PLL are mxn ways. It becomes. Therefore, as compared with the conventional clock generation circuit that changes the frequency of the output clock only by the PLL, the maximum value that m, which is the frequency dividing ratio of the first frequency dividing means provided in the PLL, can be suppressed. The value that can be taken by the frequency of the output clock can be increased while suppressing the jitter (frequency error) amplified by the PLL, and the frequency that the output clock can take can be adjusted (high resolution) at fine intervals. it can.
[0013]
  In addition, since the value that can be taken by the frequency of the output clock can be increased, even if the frequency of the original oscillation clock is set high, the frequency that can be taken by the output clock can be adjusted (with high resolution) at fine intervals. As a result, jitter contained in the original oscillation clock can be suppressed.
[0014]
  In addition to the above configuration, the image output apparatus of the present invention hasThe PLL includes detection means for detecting a phase difference between the input clock and the clock from the first frequency dividing means, and adjustment means for adjusting the frequency of the output clock based on the phase difference. The first frequency dividing means divides the clock output from the adjusting means.It may be configured.
[0015]
  According to the above configuration, the detecting unit compares the phase difference between the clock from the first frequency dividing unit and the input clock. And a control means adjusts the frequency of an output clock based on the said phase difference, and outputs a clock. Further, the clock output from the control means is frequency-divided by the first frequency dividing means and then detected by the detecting means. As described above, in the PLL, the detection unit and the adjustment unit constitute a feedback control circuit, and the frequency of the clock from the first frequency dividing unit is brought close to the frequency of the clock input to the PLL. Therefore, the frequency of the output clock from the PLL can be adjusted as a result of feedback control of the frequency of the clock from the first frequency divider.
[0016]
  In the image output apparatus according to the present invention, in addition to the above-described configuration, the PLL includes a detection unit that detects a phase difference between the input clock and the clock from the first frequency dividing unit, and converts the phase difference into correction data. Means and adjusting means for adjusting the frequency of the clock output based on the correction data, and the first frequency dividing means may divide the clock output from the adjusting means.
[0017]
  In addition to the above configuration, the image output apparatus of the present invention may generate a reference clock for modulating the intensity of the light beam for each color by the clock generation circuit.
[0018]
  According to the above configuration, the clock generation circuit can generate a reference clock for each color. Then, according to the image data, the digital image data is converted to analog data in accordance with the rising edge or falling timing of the reference clock generated for each color. In addition, the light beamThemodulationDoThe means modulates the intensity of the light beam of each color emitted from the light source for each color based on the analog data for each color.
[0019]
  And the modulated light beam for each color isThe light beam of each color is deflected in the main scanning direction.Deflected in the main scanning direction by the deflecting means;Concentrate light beams for each color on photographic paperIt is condensed on the photographic paper by optical means. At this time, so-called chromatic aberration is generated by the optical means, and at the same time, a deviation occurs in the deflection of the light beam for each color in the deflection means. Here, in order to eliminate the chromatic aberration and the deviation of the deflection of the light beam, a means capable of finely shifting the reference clock frequency of each color for each color is required.
[0020]
  However, according to the above configuration, since the clock generation circuit generates the reference clock for each color, the frequency of the reference clock for each color can be shifted at fine intervals for each color. Therefore, the frequency of the reference clock can be finely shifted for each color so as to eliminate the chromatic aberration and the deviation of the deflection of the light beam, for example, at the time of factory shipment. Note that chromatic aberration refers to a phenomenon in which the focal length does not match for each color component of light emitted from an optical system.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
  The clock generation circuit of the present invention is suitably used as a circuit that generates a clock (hereinafter referred to as a reference clock) that serves as a reference for a high-frequency signal modulated based on image data in an image output device such as a laser printer. Is. Therefore, here, a mode in which the clock generation circuit of the present invention is applied to an image output apparatus will be described with reference to the drawings.
[0022]
  FIG. 2 is an explanatory diagram showing a schematic configuration of an image output apparatus according to an embodiment of the present invention. As shown in the figure, the image output apparatus includes an image printing unit 1 and a development processing unit 2.
[0023]
  The image printing unit 1 is a block that performs printing processing by irradiating light corresponding to input image data onto a photographic paper 3 as a photosensitive material. Details of the image printing unit 1 will be described later.
[0024]
  The development processing unit 2 includes a development processing unit and a drying unit. The development processing unit has processing tanks for storing various processing solutions such as a color developer, a bleaching solution, a fixing solution, and a stabilizing solution. The photographic paper 3 on which the image has been printed in the image printing unit 1 is developed by being immersed in these processing solutions in sequence. The drying unit is a block that performs a drying process by blowing hot air on the photographic paper 3 developed in the development processing unit. The photographic paper 3 dried in the drying unit is discharged as a finished print 4 to the outside of the apparatus.
[0025]
  As described above, the image output apparatus according to the present embodiment is configured to continuously perform exposure, development processing, and drying processing of photographic paper under unified management. Therefore, it is possible to continuously print a large amount of images without imposing an operation burden on the user.
[0026]
  Next, details of the configuration of the image printing unit 1 will be described. As shown in FIG. 2, the image printing unit 1 is provided with magazines 5 and 5, a cutter 6, an exposure unit 7, and a control unit 8.
[0027]
  The magazines 5 and 5 each store unexposed and undeveloped photographic paper 3 in a roll state. These magazines 5 and 5 store roll-shaped printing papers 3 having different widths from each other, and according to the required size of the printing paper, these are switched and conveyed to the exposure position. ing.
[0028]
  The cutter 6 cuts the photographic paper 3 drawn out from the magazines 5 and 5 into a set print size. The photographic paper 3 cut by the cutter 6 is then conveyed to an exposure position facing the exposure unit 7. The position where the cutter 6 is provided is not particularly limited, and it may be configured such that the photographic paper 3 is transported to the exposure position in an uncut state and cut after exposure.
[0029]
  The exposure unit 7 is a block composed of an exposure engine of a laser exposure system, and modulates laser light of each color component of R (red), G (green), and B (blue) according to image data, and sets the exposure position. The laser light is irradiated toward the arranged photographic paper 3. Details of the exposure unit 7 will be described later.
[0030]
  The control unit 8 performs overall control of various operations in the image output apparatus. For the exposure unit 7, image data obtained by reading a negative / positive film or a reflective original with a scanner, image data processed by a personal computer, image data taken by a digital camera, etc. Will be sent. Although not shown in FIG. 2, the control unit 8 is connected to a PC (personal computer), and the control unit 8 receives image data from the PC.
[0031]
  The photographic paper 3 is printed at an exposure position facing the exposure unit 7 by the image printing unit 1 having the above-described configuration. Specifically, by inputting the image data of each color component to the exposure unit 7, the image data of each color component of BGR is printed on the photographic paper 3 at the same time. The photographic paper 3 is conveyed at a speed synchronized with the driving of the exposure unit 7, and a color image for one frame is printed on the photographic paper by a scanning exposure method.
[0032]
  Next, the configuration of the exposure unit 7 and the control unit 8 will be described. FIG. 3 is an explanatory diagram showing a schematic configuration of the exposure unit 7 and the control unit 8.
[0033]
  The exposure unit 7 converts each color laser beam emitted from the red laser light source (light source) 10R, the green laser light source (light source) 10G, and the blue laser light source (light source) 10B into an AOM (Acousto-Optic Modulator) 11R / 11G / 11B, respectively. The photographic paper (not shown) is exposed by scanning each modulated laser beam through the polygon mirror (deflecting means) 18 and the fθ lens (optical means) 19. ing.
[0034]
  On the optical axis from the red laser light source 10R, the green laser light source 10G, and the blue laser light source 10B to the polygon mirror 18, the AOM 11R / 11G / 11B, the first mirror 12R / 12G / 12B, and the expander lens unit 13R / 13G. 13B, second mirrors 14R, 14G, and 14B, cylinder lenses 15R, 15G, and 15B, apertures 16R, 16G, and 16B, and prism 17 are provided in this order.
[0035]
  The red laser light source 10R, the green laser light source 10G, and the blue laser light source 10B are light sources that emit red laser light, green laser light, and blue laser light, respectively. As a laser beam emission source, an LD (Laser Diode), a SHG (Second Harmonic Generation) laser unit, or the like is used. The red laser light source 10R, the green laser light source 10G, and the blue laser light source 10B are set so as to emit laser light of each color with a constant intensity.
[0036]
  AOMs (light beam modulation means) 11R, 11G, and 11B are optical modulators that utilize a diffraction phenomenon, that is, so-called acousto-optic diffraction, in which a refractive index distribution created in a transparent medium by sound waves acts as a phase diffraction grating, The intensity of the diffracted light is modulated by changing the intensity of the applied ultrasonic wave. A driving board 21 in the control unit 8 is connected to these AOMs 11R, 11G, and 11B, and analog data whose amplitude is modulated according to digital image data of each color component is input from the driving board 21.
[0037]
  When analog data is input to the AOMs 11R, 11G, and 11B, ultrasonic waves corresponding to the high-frequency signals are propagated in the acoustooptic medium. When laser light passes through such an acousto-optic medium, diffraction occurs due to the acousto-optic effect. Therefore, the laser beams of the respective colors incident on the AOMs 11R, 11G, and 11B are emitted as diffracted light composed of laser beams having an intensity corresponding to the amplitude of analog data based on the digital image data.
[0038]
  In the present embodiment, as described above, the AOM 11R, 11B, and 11G are used as the configuration for modulating the intensity of the laser light of each color component, but the present invention is not limited to this, and the laser light of each color component is used. Any configuration may be used as long as it can change the intensity of the light. For example, instead of the above AOM, for example, an electro-optic modulation element (EOM) or a magneto-optic modulation element (MOM) may be applied to modulate the intensity of laser light.
[0039]
  Alternatively, the intensity of the laser light may be modulated by directly modulating the outputs themselves from the red laser light source 10R, the green laser light source 10G, and the blue laser light source 10B without providing an AOM.
[0040]
  The respective color laser beams emitted from the AOMs 11R, 11G, and 11B are reflected by the first mirrors 12R, 12G, and 12B, and enter the expander lens units 13R, 13G, and 13B, respectively.
[0041]
  The expander lens units 13R, 13G, and 13B are lens units that include an expander lens that expands incident light, a collimator lens that emits incident light as parallel light, and the like. The color laser beams incident on the expander lens units 13R, 13G, and 13B are converted into parallel light and emitted.
[0042]
  The color laser beams emitted from the expander lens units 13R, 13G, and 13B are reflected by the second mirrors 14R, 14G, and 14B, and enter the cylinder lenses 15R, 15G, and 15B, respectively.
[0043]
  The cylinder lenses 15R, 15G, and 15B are lenses that condense incident color laser beams on the reflection surface of the polygon mirror 18 in the sub-scanning direction. The cylinder lenses 15R, 15G, and 15B perform correction (surface tilt correction) when a surface tilt error (an error in which the normal direction of the reflective surface deviates from the normal main scanning surface) occurs on the reflective surface of the polygon mirror 18. Is to do.
[0044]
  The respective color laser beams emitted from the cylinder lenses 15R, 15G, and 15B are incident on the prism 17 through the openings of the apertures 16R, 16G, and 16B. By appropriately setting the sizes of the apertures of the apertures 16R, 16G, and 16B, it is possible to set the diameter of the laser beam, that is, the size of the dots when irradiated onto the photographic paper.
[0045]
  The prism 17 includes a wavelength selection film 17R / 17G / 17B inside. The wavelength selection film 17R reflects the red component laser light incident from the aperture 16R in the direction in which the polygon mirror 18 is disposed. This wavelength selection film 17R has a property of reflecting only light of the red component wavelength and transmitting light of other wavelengths. Similarly, the wavelength selection film 17G reflects only the green component laser light, and the wavelength selection film 17B reflects only the blue component laser light in the direction in which the polygon mirror 18 is disposed.
[0046]
  The wavelength selection films 17G and 17B are arranged on the optical path from the wavelength selection film 17R to the polygon mirror 18. That is, the red laser light reflected by the wavelength selection film 17R passes through the wavelength selection films 17G and 17B and reaches the polygon mirror 18. Further, the green laser light reflected by the wavelength selection film 17G passes through the wavelength selection film 17B and reaches the polygon mirror 18. Therefore, the laser beam emitted from the prism 17 to the polygon mirror 18 becomes a laser beam including all of the red component, green component, and blue component laser beams modulated in accordance with the image data.
[0047]
  The polygon mirror 18 is a rotating body provided such that a plurality of reflecting surfaces form a regular polygon, and is rotated by a polygon driver (not shown). The laser light emitted from the prism 17 is reflected by one reflecting surface of the polygon mirror 18 and travels in the direction of the photographic paper. The reflection direction of the laser light from the polygon mirror 18 moves in the main scanning direction according to the rotation of the polygon mirror 18. When the reflection of the laser beam on one reflecting surface is finished by the rotation of the polygon mirror 18, the irradiation of the laser beam moves to the reflecting surface adjacent to the reflecting surface, and the reflecting direction of the laser beam is changed in the main scanning direction within the same range. Moving. In this way, one scanning line is scanned by one reflecting surface, and the next scanning line is scanned by an adjacent reflecting surface, so that the time lag between adjacent scanning lines in the sub-scanning direction is extremely small. It can be made smaller.
[0048]
  The fθ lens 19 is an optical system for correcting image distortion in the vicinity of both ends of the scanning surface due to the laser light applied to the photographic paper from the polygon mirror 18, and is composed of a plurality of lenses. The distortion of the image in the vicinity of both ends of the scanning plane is caused by the difference in the length of the optical path from the polygon mirror 18 to the photographic paper.
[0049]
  As described above, the exposure unit 7 in the present embodiment exposes the photographic paper while moving the laser light corresponding to each color of red, green, and blue modulated according to the image data in the main scanning direction. At the same time, a two-dimensional image is formed on the photographic paper by conveying the photographic paper in the sub-scanning direction.
[0050]
  The control unit 8 includes an R signal processor 20R, a G signal processor 20G, a B signal processor 20B, a drive board 21, and an image processing board 22.
[0051]
  The image processing board 22 includes a correction calculation unit (exposure correction calculation device) 22A, a memory 22B, and an LUT 22C, and is connected to the PC 9. The correction calculation unit 22A is a block that performs correction calculation, and includes, for example, a microprocessor, a RAM (Random Access Memory) as a work area, a ROM (Read Only Memory) that stores a correction calculation program, and the like. The memory 22B is a storage unit that stores image data, and includes a RAM or the like. The LUT 22C is a storage unit that stores a coefficient for performing gamma correction on the image data.
[0052]
  The image data transmitted from the PC 9 is first stored in the memory 22B. Thereafter, the correction calculation unit 22A reads the image data stored in the memory 22B, and a correction calculation described later is performed. The corrected image data is stored again in the memory 22B, corrected by the LUT 22C, and then output to the drive substrate 21.
[0053]
  The drive substrate 21 is a block that converts digital image data into analog data in accordance with the rising edge or falling timing of the reference clock according to the image data of each color input from the image processing substrate 22. Here, the drive board 21 is provided with a clock generation circuit for generating the reference clock. The configuration of the clock generation circuit will be described later.
[0054]
  The R signal processor 20R, the G signal processor 20G, and the B signal processor 20B are blocks that convert analog data generated in the drive board 21 into analog data that is optimal for driving the AOMs 11R, 11G, and 11B.
[0055]
  The PC 9 has functions of storing original image data to be output of an image and performing various image editing processes and controlling various operations in the image output apparatus. Note that a scanner for scanning photographic film or the like may be connected to the PC 9.
[0056]
  Next, a clock generation circuit for generating the reference clock and adjusting the frequency, which is a feature of the present embodiment, will be described with reference to FIG.
[0057]
  The clock generation circuit 30 includes a crystal oscillator 31, a variable frequency divider (second frequency dividing means) 32, and a PLL (Phase Looked Loop) 33.
[0058]
  The crystal oscillator (piezoelectric oscillator) 31 is an oscillator that generates the reference clock using the piezoelectric effect, and the oscillation frequency depends on the nature of the crystal. In the present embodiment, it is assumed that the crystal oscillator 31 generates a clock a (original oscillation clock).
[0059]
  The variable frequency divider 32 is a circuit that receives the clock a output from the crystal oscillator 31, divides the frequency of the clock a by 1 / n, and outputs this as the clock b. The clock b output from the variable frequency divider 32 is input to the PLL 33. Note that n in the frequency division ratio 1 / n is a natural number and variable.
[0060]
  The PLL 33 is a circuit that brings the frequency of the clock d (the clock from the first frequency dividing means) close to the frequency of the clock b by controlling the frequency of the clock c output from the VCO 36, and is a phase comparator (detecting means). 34, a low-pass filter (LPF) 35, a voltage controlled oscillator (VCO) 36, and a variable frequency divider (first frequency dividing means) 37.
[0061]
  The phase comparator 34 detects the phase difference between the clock b input from the variable frequency divider 32 and the clock d input from the variable frequency divider 33, outputs the clock b to the LPF 35, and converts the phase difference into an error signal. Is output to the LPF 35.
[0062]
  The LPF 35 removes a noise component included in the clock b input from the phase comparator 34, then outputs the clock b to the VCO 36, converts an error signal input from the phase comparator 34 into correction data, and performs the correction. This is for outputting data to the VCO 36.
[0063]
  The VCO 36 is an oscillator that can control the frequency of the input clock by controlling the DC voltage. The clock b and the correction data are input from the LPF 35 so that the frequency of the clock d approaches the frequency of the clock b based on the correction data. In addition, the frequency of the clock c is adjusted. That is, since the VCO 36 is controlled based on the error signal output from the phase comparator 34, the phase comparator 34, the LPF 35, and the VCO 36 constitute a feedback control circuit. The VCO 36 outputs the adjusted clock c (output clock) as a reference clock, and outputs the clock c to the variable frequency divider 37. In this embodiment, the phase comparator 34 detects the error signal, and the LPF 35 converts the error signal into correction data, and then transmits the correction data to the VCO 36. However, the phase comparator 34 detects the error signal. While detecting the signal, the error signal may be converted into correction data, and the correction data may be transmitted directly to the VCO 36.
[0064]
  The variable frequency divider 37 is a circuit that receives the clock c output from the VCO 36, divides the frequency of the clock c by 1 / m, and outputs this as the clock d. The clock d output from the variable frequency divider 37 is input to the phase comparator 34. Note that m at the frequency division ratio 1 / m is a natural number and is variable.
[0065]
  Next, the operation of the PLL 33 will be described as follows. First, the phase difference between the clock b input to the PLL 33 and the clock d divided by the variable frequency divider 37 is detected by the phase comparator 34 as an error signal. Thereafter, the LPF 35 converts the error signal into a correction value. Next, the VCO 36 adjusts the frequency of the clock c based on the correction value so that the frequency of the clock d approaches the frequency of the clock b. The clock c is output from the PLL 33. That is, the PLL 33 functions as a feedback control circuit for bringing the frequency of the clock d close to the frequency of the clock b divided by the frequency divider 37.
[0066]
  Here, since the frequency division ratio 1 / m of the variable frequency divider 37 is variable, the PLL 33 can set the frequency of the output clock c in m ways. Furthermore, in this embodiment, since the frequency division ratio 1 / n of the variable frequency divider 32 provided in the upper stage of the PLL 33 is also variable, the variable frequency divider 32 has a clock b input to the PLL. Can be set in n ways. Here, when the frequency of the clock a is f (REF0), the frequency of the clock b is f (REF1), the frequency of the clock c is f (OUT), and the frequency of the clock d is f (REF2), the following relationship is established. To do.
[0067]
  Since the variable frequency divider 32 divides the frequency of the clock a by 1 / n,
f (REF1) = f (REF0) / n (n is a natural number)...(1)
Since the variable frequency divider 37 divides the frequency of the clock c by 1 / m,
f (REF2) = f (OUT) / m (m is a natural number)(2)
Since the VCO 36 adjusts the frequency of the clock d so as to approach the frequency of the clock b,
f (REF1) ≈f (REF2)...(3)
(1) (2) (3)Than
f (OUT) = f (REF0) × m / n
  That is, the clock generation circuit 30 can change the frequency of the clock a generated by the crystal oscillator 31 to m / n. In other words, the clock circuit 30 can set the frequency of the output clock c in m × n ways by combining the variable frequency divider 32 provided in the upper stage of the PLL 33 and the PLL 33.
[0068]
  On the other hand, in the conventional image output apparatus, the frequency of the clock generated from the crystal oscillator 31 is variably controlled only by the PLL, and this is used as the reference clock. In other words, in the conventional configuration, the frequency of the reference clock can only be set to m. In this regard, according to the present embodiment, since the variable frequency divider 32 is further provided in the upper stage of the PLL 33, the frequency of the reference clock can be set in m × n ways. Adjustment (high resolution) can be made at intervals. For example, it can be said that it is higher resolution to change the frequency in increments of 100.0 KHz, 100.1 KHz, 100.3 KHz,... And 0.1 KHz than to change the frequency in increments of 1 KHz, such as 101 KHz, 102 KHz, 103 KHz.
[0069]
  Furthermore, according to the above configuration, since the PLL 33 is used instead of the DDS (Direct Digital Synthesizer) in the clock generation circuit 30, a means for adjusting the clock frequency at a low price can be configured. Further, according to the above configuration, since the frequency of the reference clock can be set in m × n ways, the frequency of the reference clock is adjusted at fine intervals while suppressing the m value at the division ratio 1 / m of the variable frequency divider 37. can do. Therefore, the PLL 33 can suppress amplification of the jitter (frequency error) of the reference clock, and can output a reference clock with low jitter. Furthermore, according to the above configuration, since the frequency of the reference clock can be set to m × n, even if the frequency of the clock a output from the crystal oscillator 31 is increased, the frequency of the reference clock can be adjusted at fine intervals. it can.
[0070]
  The clock generation circuit 30 can generate a reference clock necessary for modulating the digital image data for each color into analog data on the drive substrate 21. Then, the drive substrate 21 converts the digital image data into analog data in accordance with the rising edge or the falling timing of the reference clock according to the digital image data of each color. Further, the AOMs 11R, 11G, and 11B modulate the intensity of each color laser beam emitted from the light sources 10R, 10G, and 10B for each color based on the analog data. The modulated laser light for each color is deflected in the main scanning direction by the polygon mirror 18 and condensed on the photographic paper by the Fθ lens 19. At this time, so-called chromatic aberration is generated by the Fθ lens 19 and, at the same time, a deviation occurs in the deflection of the light beam in the polygon mirror 18 for each color. Here, since the clock generation circuit generates the reference clock for each color, the frequency of the reference clock for each color can be shifted in advance at fine intervals for each color. Therefore, the frequency of the reference clock can be finely shifted for each color so as to eliminate the chromatic aberration and the deviation of the deflection of the light beam, for example, at the time of factory shipment. Note that chromatic aberration refers to a phenomenon in which the focal length does not match for each color component of light emitted from an optical system.
[0071]
  The frequency of the reference clock that can be set when the frequency of the clock a oscillated from the crystal oscillator 31 is 10.000 (MHz) is shown in the table of FIG. Here, m can take a value from 1 to 20, and n can take a value from 1 to 20, so the frequency of the reference clock can be set to 400. However, since there are overlapping values in the 400 frequencies, if the overlapping values are eliminated, there are 240 frequencies that can be substantially set (values in the enclosed portions in the figure).
[0072]
  Further, the frequency of the reference clock that can be set may be tabulated and stored in the memory 22B. In this case, the table shown in FIG. 4 is stored in the memory 22B in advance, and the operator inputs an arbitrary frequency from a PC (not shown). Then, the PC detects the frequency closest to the above-mentioned arbitrary frequency from the table shown in FIG. 4, and selects the values of n and m so that the detected frequency is obtained. Further, the PC controls the frequency dividing ratios of the variable frequency dividers 32 and 37 based on the selected values of n and m. With this configuration, the frequency of the reference clock can be controlled to an arbitrary value by the operator.
[0073]
  Further, in the clock generation circuit 30 of the present embodiment, since the crystal oscillation 31 generates the original oscillation clock, the clock generation circuit 30 can generate a low jitter clock.
[0074]
  Here, in this embodiment, the clock generation circuit 30 is applied to the image output apparatus, but the present invention is not limited to this. The clock generation circuit 30 is preferably used for a device that is required to variably adjust the clock frequency at fine intervals. For example, it can be used for a television that receives video signals, a radio that receives audio signals, and the like.
[0075]
  The clock generation method according to the present embodiment divides the output clock, and in the clock generation method using the PLL that feedback-controls the frequency of the divided clock, the clock of the original oscillation before being input to the PLL The frequency division ratio of the output clock and the frequency division ratio of the original oscillation clock can be made variable.
[0076]
  In the above procedure, assuming that the frequency division ratio for dividing the original oscillation clock is 1 / n (n is a natural number) and the frequency of the original oscillation clock is f, the frequency of the clock input to the PLL is f / n. . If the output clock division ratio in the PLL is 1 / m (m is a natural number), the PLL divides the output clock, and feedback control is performed on the frequency of the divided clock. The frequency of the output clock is mf / n. That is, in the above procedure, the frequency of the original oscillation clock can be controlled to m / n times, and by changing the frequency division ratio of the output clock and the frequency division ratio of the original oscillation clock, the clock output from the PLL can be changed. The frequency can be set in m × n ways.
[0077]
  On the other hand, in the conventional clock generation method, although the clock frequency is adjusted by the PLL, the frequency of the clock input to the PLL is fixed. Therefore, if the frequency division ratio in the PLL is 1 / N, the output clock Can be set only in N ways. Therefore, in order to adjust (high resolution) the frequency that can be taken by the output clock at fine intervals by the conventional method, the value that can be taken by N must be increased and the clock of the original oscillation must be made low frequency. However, there is a problem that the jitter (frequency error) of the output clock is amplified as the value of N is higher or the frequency of the original oscillation clock is lower.
[0078]
  Here, in the clock generation method of the present embodiment, since the frequency of the original oscillation clock input to the PLL can be changed to n ways, the possible values of the frequency of the output clock from the PLL are mxn ways. Compared to the conventional clock generation method that changes the frequency of the output clock only with the PLL, the maximum value that m, which is the frequency division ratio of the clock output from the PLL, is suppressed, and the frequency of the original oscillation clock is increased. Even so, the possible value of the output clock frequency can be increased, and the possible frequency of the output clock can be adjusted (high resolution) at fine intervals.
[0079]
  In addition, since the value that can be taken by the frequency of the output clock can be increased, even if the frequency of the original oscillation clock is set high, the frequency that can be taken by the output clock can be adjusted (with high resolution) at fine intervals. As a result, the jitter contained in the original oscillation clock can be suppressed. Can do.
[0080]
  Finally, the embodiment described above does not limit the scope of the present invention, and various modifications can be made within the scope of the present invention.
[0081]
【The invention's effect】
  As described above, the image output apparatus of the present invention modulates the intensity of each color light beam emitted from the light source for each color according to the image data, and condenses the modulated light beam on the photosensitive material. An output device, comprising: a clock generation circuit that generates a clock for performing intensity modulation of the light beam; and a computer that controls the clock generation circuit, wherein the clock generation circuit includes:Division ratio1 / mThe frequency of the PLL from which the clock is output from the first frequency dividing means whose frequency is variable is controlled by feedback, and the frequency of the clock of the original oscillation is controlled, and this clock is input to the PLL.1 / nA second frequency dividing means that is variable;The computer includes a memory that stores a table in which a frequency of a clock output from the PLL is associated with a combination of n and m so as to be the frequency, and a clock output from the PLL Means for inputting the frequency, means for detecting the frequency closest to the input frequency with reference to the table, and means for selecting a combination of n and m associated with the detected frequency And means for controlling the frequency dividing ratio of the first frequency dividing means and the second frequency dividing means in accordance with the selected combination of n and m.
[0082]
  Therefore, as compared with the conventional clock generation circuit that changes the frequency of the output clock only by the PLL, the maximum value that m, which is the frequency dividing ratio of the first frequency dividing means provided in the PLL, can be suppressed. Therefore, while suppressing the jitter (frequency error) amplified by the PLL, the value that the output clock frequency can take can be increased, and the frequency that the output clock can take can be adjusted (high resolution) at fine intervals. Can do.
[0083]
  In addition, since the value that can be taken by the frequency of the output clock can be increased, even if the frequency of the original oscillation clock is set high, the frequency that can be taken by the output clock can be adjusted (with high resolution) at fine intervals. As a result, the jitter contained in the original oscillation clock can be suppressed.
[0084]
  In addition to the above configuration, the image output apparatus of the present invention hasThe PLL includes detection means for detecting a phase difference between the input clock and the clock from the first frequency dividing means, and adjustment means for adjusting the frequency of the output clock based on the phase difference. The first frequency dividing means divides the clock output from the adjusting means.It may be configured.
[0085]
  According to the above configuration, the detecting unit compares the phase difference between the clock from the first frequency dividing unit and the input clock. And a control means adjusts the frequency of an output clock based on the said phase difference, and outputs a clock. Further, the clock output from the control means is frequency-divided by the first frequency dividing means and then detected by the detecting means. As described above, in the PLL, the detection unit and the adjustment unit constitute a feedback control circuit, and the frequency of the clock from the first frequency dividing unit is brought close to the frequency of the clock input to the PLL. Therefore, the frequency of the output clock from the PLL can be adjusted as a result of feedback control of the frequency of the clock from the first frequency divider.
[0086]
  In the image output apparatus according to the present invention, in addition to the above-described configuration, the PLL includes a detection unit that detects a phase difference between the input clock and the clock from the first frequency dividing unit, and converts the phase difference into correction data. And adjusting means for adjusting the frequency of the clock output based on the correction data. The first frequency dividing means is configured to divide the clock output from the adjusting means. It is good also.
[0087]
  In addition to the above configuration, the image output apparatus of the present invention may generate a reference clock for modulating the intensity of the light beam for each color by the clock generation circuit.
[0088]
  According to the above configuration, since the clock generation circuit generates the reference clock for each color, the frequency of the reference clock for each color can be shifted at fine intervals for each color. Therefore, the frequency of the reference clock can be finely shifted for each color so as to eliminate the chromatic aberration and the deviation of the deflection of the light beam, for example, at the time of factory shipment.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a clock generation circuit according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a schematic configuration diagram of an image output apparatus provided with the clock generation circuit.
FIG. 3 is an explanatory diagram showing a schematic configuration of an exposure unit and a control unit provided in the image output apparatus.
FIG. 4 is an explanatory diagram showing frequencies that an output clock of the clock generation circuit can take.
FIG. 5 is a block diagram showing a configuration of a conventional PLL circuit.
[Explanation of symbols]
  10R / 10G / 10B Light source
  11R / 11G / 11B AOM (light modulation means)
  18 Polygon mirror (deflection means)
  19 Fθ lens (optical means)
  30 Clock generation circuit
  31 Crystal oscillator
  32 Variable frequency divider (second frequency dividing means)
  33 PLL
  34 Phase comparator (detection means)
  35 LPF
  36 VCO (Adjustment means)
  37 Variable frequency divider (first frequency dividing means)
        Clock a (original oscillation clock)
        Clock b
        Clock c (output clock)
        Clock d (clock from the first frequency dividing means)

Claims (4)

An image output device that modulates the intensity of a light beam of each color emitted from a light source for each color according to image data, and focuses the modulated light beam on a photosensitive material,
A clock generation circuit for generating a clock for performing intensity modulation of the light beam, and a computer for controlling the clock generation circuit,
The clock generation circuit
A PLL that outputs a clock by feedback-controlling the frequency of the clock from the first frequency dividing means in which the frequency division ratio 1 / m is variable;
A second frequency dividing means for controlling the frequency of the original oscillation clock and inputting the clock to the PLL, wherein the frequency division ratio 1 / n is variable ,
The computer
A memory for storing a table in which a frequency of a clock output from the PLL and a combination of n and m so as to be the frequency are associated;
Means for inputting a frequency of a clock output from the PLL;
Means for detecting the frequency closest to the input frequency with reference to the table;
Means for selecting a combination of n and m associated with the detected frequency;
Means for controlling the frequency division ratio of the first frequency dividing means and the second frequency dividing means in accordance with the selected combination of n and m. The PLL includes a detection unit that detects a phase difference between the input clock and the clock from the first frequency dividing unit, and an adjustment unit that adjusts the frequency of the output clock based on the phase difference.
2. The image output apparatus according to claim 1, wherein the first frequency dividing means divides the clock output from the adjusting means. The PLL includes a detecting unit that detects a phase difference between an input clock and a clock from the first frequency dividing unit, a unit that converts the phase difference into correction data, and a frequency of a clock that is output based on the correction data. And adjusting means for adjusting,
2. The image output apparatus according to claim 1, wherein the first frequency dividing means divides the clock output from the adjusting means. 4. The image output apparatus according to claim 1, wherein a reference clock for modulating the intensity of the light beam is generated for each color by the clock generation circuit. 5.

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