JP3771638B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device having a high voltage MOS transistor.
For example, the present invention can be applied to a semiconductor device having a high voltage MOS transistor used in a DRAM bootstrap word line driving circuit.
[0002]
[Prior art]
In DRAM, in order to reliably write data by applying a sufficiently high voltage to a capacitor of a memory cell, the voltage of the word line is generally boosted to a power supply voltage or higher.
[0003]
FIG. 25 shows a bootstrap word line driving circuit for applying a boosted voltage to the word line. In the figure, the first Nch type MOS transistor M1 and the second Nch type MOS transistor M2 are connected in series, and the drain d3 of the third Nch type MOS transistor M3 is connected to the gate g1 of the first MOS transistor M1. Connected with A.
[0004]
A boosted voltage V0 from a booster circuit (not shown) is applied to the drain d1 of the transistor M1, and a power supply (not shown) voltage Vcc is applied to the gate g3 of the transistor M3. An output signal of a decoder (not shown) is applied to the source s3 of the transistor M3. The gate g2 of the transistor M2 is connected to the reset signal line RL. The source s1 of the transistor M1 and the drain d2 of the transistor M2 are connected at the node C, and the node C is connected to the word line WL. The source s2 of the transistor M2 is grounded.
[0005]
When the transistor M3 is selected and turned on by the decoder output signal, the potential of the source s3 becomes Vcc. The potential of the drain d3 of the transistor M3 (the potential of the node A) is Vcc-Vth3 (Vth3 is the threshold voltage of the transistor M3). Therefore, the transistor M1 is turned on and the transistor M3 is turned off. At this time, the drain d3 of the transistor M3 is in a floating state. Here, the potential of the node A becomes the potential Vr boosted to the boosted voltage V0 or more by the gate capacitance coupling of the transistor M1. Accordingly, the boosted voltage V 0 is applied to the word line WL via the node C without voltage drop.
[0006]
A voltage Vr obtained by double boosting the power supply voltage Vcc is applied to the drain d3 of the transistor M3. For this reason, the breakdown voltage of the diffusion layer constituting the drain d3 is very important. If the diffusion layer constituting the drain of the transistor M3 does not have a sufficient breakdown voltage, the breakdown voltage of the node A gradually decreases, and the voltage applied to the word line WL cannot be maintained at the boosted voltage V0.
[0007]
Furthermore, during a burn-in test in which a high voltage exceeding the standard power supply voltage range is applied as the power supply voltage, such as for screening pinholes in the gate oxide film, the transistor M3 is further subjected to the normal use. A large voltage will be applied.
[0008]
Conventionally, the transistor M3 is a high voltage MOS transistor, thereby improving the breakdown voltage of the drain diffusion layer of the MOS transistor and preventing the potential drop at the node A.
Figures 26 and 27 show a conventional example. The Nch type high breakdown voltage MOS transistor 1 shown as conventional example 1 in FIG. 26 is formed in a low concentration P type well, and the drain diffusion layer is formed by a relatively low concentration and wide N type layer. Widening the depletion layer at the interface with the P-type well (substrate) makes it possible to increase the breakdown voltage of the drain diffusion layer.
[0009]
The Nch type high breakdown voltage MOS transistor 2 shown as conventional example 2 in FIG. 27 is formed by forming a drain diffusion layer at a relatively low concentration and making the gate electrode a ring shape in the same manner as the transistor shown in FIG. In addition to the means for increasing the breakdown voltage of the transistor shown in FIG. 26, it avoids electric field concentration at the intersection of the gate electrode and the field oxide film, thereby enabling the breakdown voltage of the drain diffusion layer to be increased.
[0010]
[Problems to be solved by the invention]
Conventional methods for improving the breakdown voltage of MOS transistors are limited as devices become smaller.
[0011]
For example, in the high-breakdown-voltage MOS transistor structure shown in FIGS. 26 and 27, it is necessary to provide a wide low-concentration diffusion layer that constitutes the drain. However, as the device becomes finer, the low-concentration drain diffusion layer cannot be sufficiently widened.
[0012]
In addition, when the gate oxide film of a MOS transistor becomes thinner due to miniaturization, the electric field applied to the junction surface between the drain N-type layer and the P-type well (substrate) becomes stronger in the vicinity of the gate electrode. Will break down (Gated Junction Breakdown).
[0013]
A specific explanation will be given using the Nch MOS transistor shown in FIG. First, Vg is applied to the gate of the MOS transistor in FIG. 28 and Vbb is applied to the substrate so that Vg = Vbb = 0v. Next, a positive voltage Vd is applied to the drain. Here, when the gate insulating film is thinner than the depletion layer width of the PN junction between the drain and the substrate, the electric field E1 in the vicinity of the gate electrode is inversely proportional to the thickness of the gate insulating film, and the PN excluding the vicinity of the gate electrode. The magnitude of the electric field E2 applied to the junction is inversely proportional to the depletion layer width. Since the thickness of the gate insulating film is thinner than the depletion layer width of the PN junction, E1> E2. Therefore, when Vd is increased, breakdown begins near the gate electrode of the PN junction.
[0014]
In order to avoid this, there is a method of increasing the thickness of the gate oxide film, but it goes against the recent trend of thinning the gate oxide film with the miniaturization of devices.
The most serious problem is that when the PN junction between the drain diffusion layer and the P-type well (substrate) completely breaks down near the gate electrode, the breakdown voltage of the drain diffusion layer is degraded. When the PN junction breaks down, a hole-electron pair is generated. When a breakdown occurs near the gate, the generated hole or electron is injected into the gate oxide film. At that time, an interface state is created at the interface between the gate oxide film and the P-type well (substrate), which acts as a path for the reverse leakage current of the PN junction, increasing the leakage current, that is, degrading the breakdown voltage.
[0015]
In addition, at the intersection of the drain diffusion layer and the field oxide film, if breakdown occurs in the vicinity of the drain diffusion layer, the leakage current increases due to the same breakdown.
We confirmed by the following experiment that breakdown voltage degradation caused by this breakdown also occurs in a conventional high breakdown voltage MOS transistor in which the drain diffusion layer is composed of a low concentration diffusion layer.
[0016]
FIG. 29 shows the high voltage MOS transistor used in the experiment. In the figure, 401 is a P-type substrate, 402 is a P-type well, 403 is a P-type channel stop, 404 is a field oxide film, 405 is a relatively low concentration N-type drain diffusion layer, and 406 is an N-type source diffusion of an LDD structure. 407 is a gate oxide film, 408 is a gate Poly-Si electrode, 409 is an oxide film spacer, 410 is an interlayer oxide film, 411 is a drain Poly-Si electrode, and 412 is a source Poly-Si electrode. Terminal b is output from the P-type well, terminal g is output from the gate electrode, terminal d is output from the drain electrode, and terminal s is output from the source electrode.
[0017]
A voltage of Vg = 3.3v is applied to the gate electrode of this high voltage MOS transistor, Vbb = 0v is applied to the P-type well, Vs = 0v is applied to the source electrode, and a positive voltage Vd is applied from 0v to the drain electrode. The drain current Id is measured.
[0018]
FIG. 30 shows the result. Id = 1 × 10 around Vd = 10v ^-Ten It increases to A, and a rapid increase in Id can be confirmed from around Vd = 13v.
Next, as shown in FIG. 31, a voltage of Vg = 3.3v is applied to the gate, Vs = 3.3v is applied to the source, Vbb = −1v is applied to the substrate, and stress is applied under the condition that a constant current Id is applied to the drain. From the results shown in Fig. 30, the stress current Id is 1 × 10 ^-Ten The current is A or more. After applying this stress, the drain leakage current Id-leak is measured under the conditions of Vg = 0v, Vbb = 0v, and Vd = 7v.
[0019]
The relationship between the stress time and the drain leakage current Id-leak is shown in the graph of FIG. In this graph, it can be confirmed that the leak current Id-leak increases rapidly when stress is applied for about 1 second under any stress current conditions. This is due to the occurrence of an interface state at the interface between the gate oxide film and the substrate, indicating that breakdown occurs near the gate electrode. It shows that the breakdown voltage of the drain diffusion layer has deteriorated due to stress.
[0020]
The graph in Fig. 33 shows the amount of change in the Vth of the MOS transistor with respect to the stress time, but it appears that Vth has changed despite the difference due to the magnitude of the constant current Id given by the stress. Yes.
[0021]
From the above experimental results, the present inventors have confirmed that breakdown of the drain diffusion layer occurs in the vicinity of the gate electrode in the conventional high breakdown voltage MOS transistor, which causes breakdown voltage degradation of the drain diffusion layer.
[0022]
If the gate junction breakdown voltage of the drain diffusion layer is lower than the high voltage applied during the burn-in test, the burn-in test will cause breakdown voltage degradation. Therefore, the gate junction breakdown voltage of the drain diffusion layer needs to be higher than the voltage applied during the burn-in test, but as mentioned above, it is difficult to increase the breakdown voltage with the miniaturization of devices.
[0023]
In addition, a higher voltage may be applied instantaneously due to noise during the Burn In test. In this case, even if the gate junction breakdown voltage of the drain diffusion layer is higher than the voltage during the Burn In test, breakdown voltage degradation occurs.
[0024]
Therefore, in the conventional method, the breakdown voltage degradation when the drain diffusion layer of the high breakdown voltage MOS transistor breaks down, particularly the breakdown voltage breakdown due to breakdown during the Burn In test, is a major problem.
[0025]
An object of the present invention is to prevent the breakdown voltage deterioration of the drain diffusion layer of a high breakdown voltage MOS transistor.
[0026]
[Means for Solving the Problems]
The solutions to the above problems are as follows: 1) one-conductivity type semiconductor substrate A gate electrode formed on a substrate via a gate oxide film, and the semiconductor substrate separated by the gate electrode and having a reverse conductivity type is a MOS First and second diffusion regions serving as the drain and source of the transistor, and the first and second diffusion regions And element isolation region Spaced apart from these areas And a third diffusion region that is continuously present, below the first and second diffusion regions and the element isolation region, and above the third diffusion region and the same as the semiconductor substrate. A fourth diffusion region of conductivity type, and the impurity concentration of the third diffusion region is higher than the impurity concentration of the semiconductor substrate and the fourth diffusion region, and the highest impurity concentration is the first and the second diffusion regions. A depletion layer between the drain region and the third diffusion region in a region of 0.4 μm or more and 0.65 μm or less from the surface of the diffusion region 2 and spaced from the gate electrode and the element isolation region Breakdown in the area This is achieved by a semiconductor device having
[0027]
In the present invention, a region having a concentration higher than the substrate concentration is formed in a portion deeper than the source and drain diffusion layers of the high voltage MOS transistor.
The structure of a high voltage MOS transistor using the present invention is shown in FIG. In the figure, 901 is a P-type Si substrate, 902 is a high-concentration P-type diffusion region (third diffusion region), 903 is a P-type channel stop diffusion region (fourth diffusion region), and 904 is a P-type diffusion region (channel) 905 is a field oxide film, 906 is a gate oxide film, 907 is a relatively low concentration N-type drain diffusion layer, 908 is an N-type source diffusion layer of LDD structure, 909 is a gate Poly-Si electrode, and 910 is An oxide film spacer, 911 is an interlayer oxide film, 912 is a drain polysilicon (Poly-Si) electrode, and 913 is a source Poly-Si electrode.
[0028]
A channel stop diffusion region 903 is distributed under the drain 907 and source 908 diffusion layers, and a high-concentration P-type diffusion region 902 is distributed thereunder. A P-type well is formed by the P-type diffusion region 902, the channel stop diffusion region 903 and the P-type diffusion region 904.
[0029]
The breakdown voltage breakdown caused by breakdown is caused by the fact that the breakdown occurs near the gate or near the field oxide film, so that the generated holes or electrons are injected into the gate insulating film or field oxide film, and an interface state is formed. ing.
[0030]
In the present invention, the depletion layer of the PN junction between the drain diffusion layer and the P type well extends to the high concentration P type diffusion region 902. In the high-concentration P-type diffusion region 902, due to the high concentration, the spread of the depletion layer is suppressed and breakdown occurs. The profile is controlled so that the place where breakdown occurs is sufficiently separated from the gate oxide film and the field oxide film.
[0031]
Since the breakdown location is separated from the gate oxide film and the field oxide film, the generated holes or electrons are not injected into the gate oxide film or the field oxide film, and no interface state is generated. Therefore, no fluctuation or deterioration of characteristics occurs.
[0032]
The inventors confirmed the effect of the present invention by the following experiment.
The high-voltage MOS transistor used in the experiment has the same structure as the high-voltage MOS transistor shown in Fig. 1, with terminal b from the P-type well, terminal g from the gate electrode, terminal d from the drain electrode, and terminal s from the source electrode. .
[0033]
Applying a voltage of Vg = 3.3v to the gate electrode of this high voltage MOS transistor, Vbb = 0v to the substrate, Vs = 0v to the source electrode, and applying a positive voltage Vd from 0v to the drain electrode, the drain current at that time Measure Id.
[0034]
Figure 2 shows the results. Id = 1 × 10 around Vd = 10v ^-Ten A rapid increase in current over A can be confirmed. Compared with the breakdown voltage characteristics of the drain diffusion layer of the conventional high breakdown voltage MOS transistor shown in FIG. 30, the result shown in FIG. 2 shows a sharp increase in current at a lower voltage.
[0035]
Next, as shown in FIG. 31, stress is applied under the condition that a voltage of Vg = 3.3v is applied to the gate, Vs = 3.3v is applied to the source, Vbb = −1v is applied to the substrate, and a constant current Id is supplied to the drain. Stress current Id is the current at which breakdown started 1 × 10 ^-Ten The current is A or more. After applying this stress, the drain leakage current Id-leak is measured under the conditions of Vg = 0v, Vbb = 0v, and Vd = 7v.
[0036]
The graph in Fig. 3 shows the relationship between stress time and drain leakage current Id-leak. Regardless of the stress time, Id-leak is a constant value, indicating that the generation of interface states is suppressed. In other words, the breakdown of the high voltage MOS transistor according to the present invention occurs between the high-concentration P-type diffusion layer 902 and the drain diffusion layer, and hole electrons generated from the distance from the interface between the substrate and the oxide film are injected into the oxide film. It turns out that it is prevented from being done.
[0037]
Figure 4 shows the amount of change in Vth with respect to the stress time in this MOS transistor. The amount of change with respect to the stress time is always 0, and the characteristics do not change with respect to the stress.
[0038]
When comparing the graph of FIG. 30 with the graph of FIG. 2, the breakdown voltage of the drain diffusion layer of the high breakdown voltage MOS transistor according to the present invention is lower than the breakdown voltage of the drain diffusion layer of the high breakdown voltage MOS transistor according to the conventional method. In the conventional high voltage MOS transistor, the reverse current in the drain diffusion layer increases due to the breakdown near the gate electrode. However, in the high voltage MOS transistor according to the present invention, the gate voltage is lower than the breakdown near the gate electrode. This is because breakdown is caused in the high-concentration P-type diffusion layer far from the oxide film.
[0039]
The problem with the breakdown of the drain diffusion layer during the burn-in test and when a high voltage is applied due to noise is that the breakdown voltage of the drain diffusion layer of the high breakdown voltage MOS transistor of the bootstrap word line drive circuit is only degraded. There are no other problems.
[0040]
According to the present invention, even with a high voltage MOS transistor whose breakdown voltage is not so high, if the breakdown voltage in normal operation is guaranteed, it can be caused by the high voltage applied during the Burn In test or noise during the Burn In test. Even if a higher voltage is applied and breakdown occurs, the breakdown voltage does not deteriorate. Therefore, for example, in DRAM, device miniaturization can be advanced without being limited by the breakdown voltage of the high voltage MOS transistor of the bootstrap word line drive circuit.
[0041]
In addition, the high voltage MOS transistor of the bootstrap word line drive circuit can break down when noise occurs during the Burn In test, thus preventing noise from being directly applied to the word line WL. , It is possible to prevent the memory cell from being damaged by noise.
[0042]
In addition, the following effects can be obtained in a subword decoder system known as a technique in which a part of the DRAM word decoder is arranged adjacent to each block of the cell array to reduce the pitch of the backing lines of the word lines.
[0043]
The circuit shown as an example in FIG. 25 is configured in a word decoder circuit arranged adjacent to each cell array. A method for transmitting the boosted voltage V0 to the word line without a voltage drop can be realized by making the MOS transistor M1 in the circuit of FIG. 25 a Pch type MOS transistor in addition to the method described in the section of the prior art. In this case, however, the circuit in Fig. 1 has a CMOS structure in which Nch-type MOS transistors and Pch-type MOS transistors are mixed, and two well regions must be constructed.
[0044]
In other words, if a Pch-type MOS transistor is used, the area will be larger than if only an Nch-type MOS transistor is used. Moreover, since the circuit shown in FIG. 25 is arranged for each block of the cell array in the sub-word decoder system, the area expansion is a big problem.
[0045]
Since the word decoder using the Nch type high breakdown voltage MOS transistor according to the present invention for the MOS transistor M3 in the circuit of FIG. 1 can be composed of only the Nch type MOS transistor, it is possible to prevent the area of the sub word decoder system from being increased.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
As a first embodiment, a subword decoder type DRAM together with its manufacturing process is shown in FIGS.
[0047]
In Fig. 5 (a), after a 5 nm thermal oxide film (not shown) is grown on a P-type Si substrate (1301), a SiN film (1302) is grown to about 100 nm by CVD. The resist (not shown) is patterned in a shape that leaves the active region, and the thermal oxide film and SiN film are etched.
[0048]
Next, the resist (1303) is patterned so that the region where the N-type well is to be formed is exposed. ⁺ Energy 180keV, dose 1.5E13 cm ^-2 Inject with. The region A in the figure is an Nch type high voltage MOS transistor of the bootstrap word line drive circuit, the region B is an Nch type MOS transistor of the bootstrap word line drive circuit, and the region C is a DRAM cell array. Is done.
[0049]
In Fig. 5 (b), the ion-implanted impurities are diffused by annealing at 1100 ° C in a nitrogen atmosphere to form an N-type well (1304).
In Fig. 6 (c), a 300 nm oxide film 1305 (field oxide film) is formed using the LOCOS method to define the isolation region.
[0050]
In Fig. 6 (d), the resist is patterned so as to expose the region where the P-type well is to be formed, and B is formed as a P-type impurity by ion implantation. ⁺ 1.7E13 cm with 180 keV energy ^-2 inject. The impurities implanted here form a high-concentration P-type diffusion region through a subsequent heat treatment.
[0051]
In the present invention, the impurity profile of the P-type well is important. In particular, the impurity profile of the high-concentration P-type diffusion region is very important because it suppresses the breakdown voltage degradation of the drain diffusion layer of the high-voltage MOS transistor.
[0052]
The graphs in Figs. 13 and 14 show the results of investigating the dependence of the dose and implantation energy of the ion implantation for forming this high-concentration P-type diffusion layer on the drain diffusion layer breakdown voltage of the Nch type high-voltage MOS transistor. In the measurement, the gate voltage Vg = 0v, the substrate voltage Vbb = 0v, the source voltage Vs = 0v of the Nch type MOS transistor, the drain voltage is applied from 0v to the positive side, and the drain current Id is suddenly increased. The drain voltage when = 1nA flowed was defined as the drain diffusion layer breakdown voltage (hereinafter referred to as breakdown voltage).
[0053]
In the graph showing the dependency between the dose amount and the withstand voltage shown in FIG. 13, it is apparent that the withstand voltage decreases as the dose amount increases. In the graph showing the dependence between the implantation energy and the breakdown voltage shown in FIG. 14, the breakdown voltage increases as the implantation energy increases.
[0054]
When the breakdown voltage is high, breakdown occurs near the gate before it occurs between the high-concentration P-type diffusion region and the drain diffusion region in the substrate, and causes breakdown of the drain diffusion layer. If the withstand voltage is low, breakdown is likely to occur during normal DRAM use and during the Burn In test. In this case, breakdown occurs between the high-concentration P-type diffusion region and the drain diffusion region, but as the breakdown voltage is low, the high-concentration P-type diffusion region is shallow, and the breakdown location Is not sufficiently separated from the gate oxide film, hole electrons generated in the breakdown are injected into the gate oxide film, and the breakdown voltage of the drain diffusion layer also deteriorates.
[0055]
In the DRAM of the embodiment, the breakdown voltage is good from 9.5v to 11.5v, the dose amount is 1.3E13 to 3.5E13 from the graph of FIG. 13, and the injection energy is 130 to 190 keV from the graph of FIG. I understand that there is.
[0056]
FIGS. 15 to 19 show graphs showing respective P-type well profiles with respect to ion implantation conditions for forming a high concentration P-type diffusion region. The horizontal axis is the depth distance from the substrate surface, the vertical axis is the P-type impurity concentration, and the profile below the drain diffusion layer region. However, the drain diffusion layer profile is not shown to make the P-type well profile easier to understand. The ion implantation conditions in Fig. 15 are B ⁺ , 180keV, 1.0E13, the ion implantation conditions in Fig. 16 are B ⁺ , 180keV, 1.7E13, the ion implantation conditions in Fig. 17 are B ⁺ , 180keV, 2.4E13, the ion implantation conditions in Fig. 18 are B ⁺ , 160keV, 1.7E13, the ion implantation conditions in Fig. 19 are B ⁺ 140keV, 1.7E13.
[0057]
20 and 21 are graphs in which the peak concentration and depth of the high-concentration P-type diffusion region are plotted as a function of the ion implantation conditions based on these profiles. 20 shows the dose dependence of concentration, and FIG. 21 shows the depth implantation energy dependence.
[0058]
From the range of the ion implantation conditions for obtaining a good breakdown voltage and the graph of FIG. 20, the concentration of the high concentration P-type diffusion region is 5 × 10. ¹⁷ ~ 12 × 10 ¹⁷ cm ^-3 From the above-mentioned range of ion implantation conditions for obtaining a good breakdown voltage and the graph of FIG. 21, it can be seen that the depth of the high concentration P type diffusion region is preferably 0.40 to 0.65 μm.
[0059]
Therefore, the present inventors set B as ion implantation conditions for forming a high concentration P-type diffusion region. ⁺ 180keV, 1.7E13 were selected.
The resist pattern shown in Fig. 7 (e) and Fig. 6 (d) is used as a P-type impurity by ion implantation. ⁺ Of 4.0E12 at an energy of 100keV. The impurities implanted here form a P-type channel stop region through a subsequent heat treatment.
[0060]
With the resist pattern shown in Fig. 7 (f) and Fig. 6 (d) as the P-type impurity by ion implantation, B ⁺ Of 1.5E12 at an energy of 50 keV. The impurities implanted here form a P-type diffusion region through a subsequent heat treatment.
[0061]
In FIG. 8 (g), an impurity for controlling the Vth of the MOS transistor is implanted (not shown), the substrate surface is oxidized, and a gate oxide film (1307) is formed to 10 nm. The impurities implanted in the steps (d) to (f) are thermally diffused by heat treatment at 900 ° C. for 20 minutes during oxidation, resulting in a high concentration P-type diffusion region (1308), P-type channel stop region (1309), And a P-type diffusion region (1310). A P-type well is formed in these P-type diffusion regions.
[0062]
In Fig. 8 (h), a silicon film containing phosphorus is grown on the gate oxide film to 150 nm, patterned and etched into the shape of the gate electrode, and the gate electrode (1311) is formed.
[0063]
In Fig. 9 (i), N-type impurities are, for example, P ⁺ Is implanted at 30 keV and 2E13 to form the source and drain regions (1312) of a relatively thin MOS transistor. Here, the high-concentration P-type diffusion region (1308) has a profile distributed at a depth away from the source / drain region (1312).
[0064]
In Fig. 9 (j), an oxide film is grown to about 100 nm by CVD and anisotropically etched to form a spacer 1313 on the gate electrode sidewall.
[0065]
In FIG. 10 (k), a resist (1315) is patterned so that the source (1314) side of the high voltage MOS transistor and the region where the N-type LDD structure MOS transistor is formed are exposed. Then, N-type impurities are ion-implanted using the oxide spacer and the field oxide as a mask. For example, As ⁺ At 30keV, 5E15. The implanted region forms the source or drain diffusion layer of the LDD structure MOS transistor. The drain (1306) of the high voltage MOS transistor is not an LDD structure, but is formed only by a diffusion layer with a relatively low concentration.
[0066]
In FIG. 10 (l), for example, an interlayer insulating film (1317) is formed by an oxide film by a CVD method, and an electrode (1318) is formed by, for example, a Si film containing phosphorus connected from a hole contacting a drain / source region To do.
[0067]
In FIG. 11 (m), an oxide film containing boron and phosphorus is grown to about 200 nm by CVD and reflowed by annealing to form an interlayer insulating film (1319). A memory cell capacitor is formed in the cell array region. Thereafter, a wiring process is performed.
[0068]
Figure 22 shows the impurity profile under the drain of the Nch-type high voltage MOS transistor formed as described above, and Figure 23 shows the impurity profile under the field oxide film in the P-type well.
[0069]
In FIG. 22, peak A is a high-concentration P-type diffusion region, peak B is a P-type channel stop region, and peak C is an N-type drain diffusion region. The gradual increase in concentration from the bottom of peak B to peak C is at the bottom of the P-type diffusion region for Vth control. A P-type channel stop region is distributed under the drain, and a high-concentration P-type diffusion region is distributed thereunder. The concentration of the high concentration P-type diffusion region is 6.4 × 10 ¹⁷ cm ^-3 It can be seen that the depth from the surface is controlled to 0.6 μm.
[0070]
In FIG. 23, peak A is a high concentration P-type diffusion region, and peak B is a P-type channel stop region. The profile is such that the P-type channel stop is distributed directly under the field oxide film, and the high-concentration P-type diffusion region is distributed thereunder.
[0071]
FIG. 11 (m) shows the bootstrap word line driving circuit of the first word decoder adjacent to each block of the memory cells and the main part of the memory cell array. The upper cross-sectional view and the lower circuit diagram correspond to each other, and the drain electrode d3 of the Nch type high voltage MOS transistor M3 is connected to the gate electrode g1 of the Nch type MOS transistor M1.
[0072]
The drain d2 of the Nch type MOS transistor M2 is connected to the source s1 of the Nch type MOS transistor M1 through the diffusion layer, so that the MOS transistor M1 and the MOS transistor M2 are connected in series. This diffusion layer is connected to the cell word line WL and to the gate g4 of the MOS transistor M4. The MOS transistor M4 is a cell transistor and forms a memory cell of one transistor and one capacitor together with the capacitor c1.
[0073]
A power supply voltage Vcc is applied to the gate g3 of the MOS transistor M3, and an output signal from a decoder (not shown) is input to the source s3. The reset signal line RL is connected to the gate g2 of the MOS transistor M2, and the source s2 is grounded. A boosted voltage V0 is applied to the drain of the MOS transistor M1.
[0074]
A bit line BL is connected to the drain / source diffusion layer ds1 of the MOS transistor M4 of the cell and a voltage of Vcc / 2 is applied, and the other drain / source diffusion layer ds2 is connected to the storage node of the capacitor c1. A voltage of Vcc / 2 is applied across the capacitor.
[0075]
The second word decoder circuit for selecting the first word decoder is arranged at a remote location. An outline of these arrangements is shown in FIG. 13 (n).
Thus, a sub-word decoder type DRAM having a bootstrap word line driving circuit having a high voltage MOS transistor according to the present invention is completed.
[0076]
Next, a second embodiment is shown in FIG. FIG. 24 (a) is a plan view and FIG. 24 (b) is a cross-sectional view.
The gate electrode 1909 has a ring shape shown in FIG. 24A, and is a high breakdown voltage MOS transistor according to the present invention having a shape that does not contact the field oxide film 1907.
[0077]
In the figure, 1901 is a P-type Si substrate, 1902 is a high-concentration P-type diffusion region, 1903 is a P-type channel stop, 1904 is a P-type diffusion region, 1905 is a relatively low-concentration drain diffusion region, and 1906 is an LDD source. Diffusion region, 1907 is a field oxide film, 1908 is a gate oxide film, 1909 is a gate Poly-Si electrode, 1910 is an oxide film spacer, 1911 is an interlayer oxide film, 1912 is a Poly-Si electrode connected to the source diffusion region, 1913 is A Poly-Si electrode connected to the drain diffusion layer, 1914 is a Poly-Si electrode connected to the gate electrode.
[0078]
The manufacturing method is the same as that of the first embodiment, and the MOS transistor M3 of the bootstrap word line driving circuit shown in FIG.
[0079]
【The invention's effect】
According to the present invention, it is possible to prevent the breakdown voltage degradation when the drain diffusion layer of the high breakdown voltage MOS transistor breaks down. In particular, the effect of preventing breakdown voltage degradation due to breakdown during the burn-in test is remarkable.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an Nch type high voltage MOS FET according to the present invention.
FIG. 2 is an explanatory diagram of Vd-Id characteristics of the embodiment.
FIG. 3 is an explanatory diagram of constant current stress-drain diffusion layer leakage current characteristics of the embodiment;
FIG. 4 is an explanatory diagram of constant current stress-Vth shift amount characteristics according to the embodiment.
FIG. 5 is an explanatory diagram of an embodiment of a manufacturing process (1)
FIG. 6 is an explanatory diagram of an embodiment of a manufacturing process (2)
FIG. 7 is an explanatory view of an embodiment of a manufacturing process (3)
FIG. 8 is an explanatory diagram of an embodiment of a manufacturing process (4)
FIG. 9 is an explanatory diagram of an embodiment of a manufacturing process (5)
FIG. 10 is an explanatory view of an embodiment of a manufacturing process (6)
FIG. 11 is an explanatory diagram of an embodiment of a manufacturing process (7)
FIG. 12 is an explanatory diagram of an embodiment of a manufacturing process (8)
FIG. 13 is an explanatory diagram (1) depending on ion implantation conditions for forming a high concentration P type diffusion region of a drain diffusion layer breakdown voltage of an Nch type high breakdown voltage MOS FET in an embodiment.
FIG. 14 is an explanatory diagram of dependence on ion implantation conditions for forming a high-concentration P-type diffusion region of a drain diffusion layer breakdown voltage of an Nch-type high breakdown voltage MOS FET in an embodiment (2)
FIG. 15 is an explanatory diagram of the relationship between the ion implantation conditions for forming a high concentration P-type diffusion region and the impurity profile under the drain diffusion layer in the embodiment (1)
FIG. 16 is an explanatory diagram of the relationship between the ion implantation conditions for forming a high concentration P-type diffusion region and the impurity profile under the drain diffusion layer in the embodiment (2)
FIG. 17 is a diagram for explaining the relationship between the ion implantation conditions for forming a high concentration P-type diffusion region and the impurity profile under the drain diffusion layer in the embodiment (3)
FIG. 18 is an explanatory diagram of the relationship between ion implantation conditions for forming a high concentration P-type diffusion region and the impurity profile under the drain diffusion layer in the embodiment (4)
FIG. 19 is an explanatory diagram of the relationship between the ion implantation conditions for forming a high concentration P-type diffusion region and the impurity profile under the drain diffusion layer in the embodiment (5)
FIG. 20 is an explanatory diagram of the dependence of the concentration peak of the high concentration P-type diffusion region obtained from each profile of FIGS.
FIG. 21 is an explanatory diagram of the dependence of the concentration peak of the high-concentration P-type diffusion region obtained from the profiles of FIGS. 15 to 19 on the ion implantation conditions (2)
FIG. 22 shows the impurity profile under the drain of the Nch type high voltage MOS FET shown in the embodiment.
FIG. 23 shows an impurity profile under the field oxide film of the P-type well shown in the embodiment.
FIG. 24 is an explanatory diagram of the second embodiment.
FIG. 25: Bootstrap word line drive circuit
FIG. 26 is an explanatory diagram of the conventional example (1).
FIG. 27 is an explanatory diagram of the conventional example (2).
[Fig.28] Explanatory diagram of breakdown of Gated Junction
FIG. 29 is a sectional view of a conventional Nch type high voltage MOS transistor.
Fig. 30 Vd-Id characteristic diagram of the conventional example
[Fig.31] Explanatory diagram of constant current stress condition applied to Nch type high voltage MOS FET
FIG. 32 is a characteristic explanatory diagram of constant current stress-drain diffusion layer leakage current of a conventional example.
FIG. 33 is a characteristic explanatory diagram of constant current stress-Vth shift amount in a conventional example.
[Explanation of symbols]
901 P-type Si substrate
902 High-concentration P-type diffusion region
903 P-type channel stop diffusion region
904 P-type diffusion region
905 Field oxide film
906 Gate oxide film
907 N-type drain diffusion layer with relatively low concentration
908 N-type source diffusion layer with LDD structure
909 Gate Poly-Si electrode
910 Oxide film spacer
911 Interlayer oxide film
912 Drain Poly-Si electrode
913 Source Poly-Si electrode

Claims (1)

A one conductivity type semiconductor substrate,
A gate electrode formed on the semiconductor substrate via a gate oxide film;
First and second diffusion regions separated by the gate electrode and having a reverse conductivity type with respect to the semiconductor substrate and serving as the drain and source of the MOS transistor ;
A third diffusion region that is separated from and continuously exists below the first and second diffusion regions and the element isolation region ;
A fourth diffusion region that is under the first and second diffusion regions and the element isolation region and is present on the third diffusion region, and has the same conductivity type as the semiconductor substrate;
The impurity concentration of the third diffusion region is higher than the impurity concentration of the semiconductor substrate and the fourth diffusion region, and the highest impurity concentration is 0.4 μm or more and 0.65 μm from the surfaces of the first and second diffusion regions. Exists in the following areas,
A semiconductor device, wherein a breakdown occurs in a region where a depletion layer between the drain region and the third diffusion region extends at a position separated from the gate electrode and the element isolation region .

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