JP3772602B2 - Digital signal reproduction device - Google Patents

Description

BACKGROUND OF THE INVENTION
The present invention relates to a digital signal reproduction apparatus capable of suitably removing intersymbol interference from a differential waveform signal reproduced from, for example, a recording medium and extracting a reproduction clock.
[Prior art]
In recent years, partial responses developed in the communication field in the field of magnetic recording, in particular partial response class 4 (hereinafter referred to as PR4), have come to be applied.
When an interleaved NRZI code is used as a PR4 equalization system, both high-frequency signals and low-frequency components are small and band-pass frequency characteristics are exhibited, and the frequency characteristics are represented by (1− D ² ), And intersymbol interference having a value of −1 occurs 2 bits after the isolated pulse. The application of the partial response is intended to shape the reproduction frequency at the detection point by actively using the intersymbol interference. The frequency characteristic of PR4 can be decomposed into (1 + D) · (1-D). Generally, the (1-D) characteristic is compensated by the differential characteristic at the time of reproduction, and the (1 + D) characteristic is the data input at the current time. And integration processing of adding data one sample before at the data rate. If the data corresponding to “1” and “−1” of the ternary waveform after (1 + D) conversion is determined as “1” and the data corresponding to “0” is determined as “0”, the original signal series is reproduced. it can. The timing signal can be extracted from a waveform including a high-frequency signal after (1-D) conversion, that is, before (1 + D).
FIG. 7 is a block diagram for explaining PR4 in magnetic recording.
In FIG. 7, 1 is 1 / (1-D with respect to the input signal. ² 2 is a recording head for recording the output signal from the precoding circuit 1 on the magnetic tape 3, 4 is a reproducing head for reproducing the signal recorded on the magnetic tape 3, and 5 is a reproducing head 4. This is an equalization circuit for (1 + D) conversion of the signal reproduced in (1).
The operation of the conventional digital signal reproducing apparatus configured as described above will be described.
The recording data is stored in the precoding circuit 1 at 1 / (1-D ² ) Is precoded to PR4 and recorded on the magnetic tape 3 via the recording head 2. During reproduction, a reproduction signal is extracted from the magnetic tape 3 via the reproduction head 4. Here, the recording / reproducing system for the magnetic tape 3 has a differential characteristic (1-D) characteristic. The signal extracted from the magnetic head 4 can be decoded into the original recording data by performing ternary discrimination after (1 + D) conversion by the equalization circuit 5. That is, 1 / (1-D in precode ² ) Is erased by the differential characteristic (1-D) of the magnetic reproduction system and (1 + D) of reproduction equalization, resulting in 1, and the original recorded data is reproduced. In practice, pre-equalization may be performed before the equalization circuit 5.
FIG. 8 shows a configuration of a conventional digital signal reproducing apparatus using this PR4, and FIG. 9 shows a specific configuration example of main blocks.
In FIG. 8, the AD converter 10 samples the input reproduced differential waveform signal with a sampling clock at a rate twice as high as the data rate, and outputs it as digital data.
For example, as shown in FIG. 9, the transversal filter 11 includes 2N delay units 111 a to 111 k each having a delay unit of two sampling periods, and a multiplier 112 that multiplies each tap output by each tap coefficient from the correlator 13 described later. ˜112k and an adder 113 for adding each multiplier output, and pre-equalization is performed by suppressing intersymbol interference of the input signal by multiplying each tap output by a suitable coefficient. Here, the number of delay units (a to k) +1 is used, but the number of taps is arbitrarily set according to the performance required for the system.
The provisional ternary discrimination circuit 17 performs provisional ternary discrimination of pre-equalized digital data and outputs the discrimination result. That is, if the input digital data is larger than the positive threshold level, it is determined as “+1”, if it is smaller than the negative threshold level, it is determined as “−1”, otherwise it is determined as “0”. .
For example, as shown in FIG. 9, the equalization error calculation circuit 16 includes a subtracter 171 and a switching circuit 172, and with respect to the input from the transversal filter 11, the determination result of the provisional ternary determination circuit 17 corresponding to the input. Difference from the reference value is performed. That is, if the determination result is “+1”, it corresponds to a positive reference level (positive ref in FIG. 9), and if it is “−1”, it corresponds to a negative reference level (negative ref in FIG. 9) and the determination result. If the difference value from the digital data is “0”, the digital data corresponding to the determination result is output as an equalization error.
For example, as shown in FIG. 9, the correlator 13 includes delay units 133a to 133k for adjusting the time axis to each tap output of the transversal filter 11, and an equalization error arithmetic circuit 16 corresponding to each delay unit output. Each of the transversal filters 11 includes multipliers 132 to 132k that multiply the equalization error signal, multipliers 131 to 131k that accumulate the outputs of the multipliers, and coefficient units 130 to 130k that weight the outputs of the multipliers. The tap coefficient for each tap is output and updated.
For example, as shown in FIG. 9, the integral equalizer 14 includes a delay unit 141 that delays two sampling periods and an adder 142, and adds the data input at the current time and the data one sample before at the data rate. Equalization processing of (1 + D) is performed.
The ternary discrimination circuit 15 performs ternary discrimination on the (1 + D) digital data from the integral equalizer 14 and outputs the discrimination result. The determination method is the same as that of the provisional ternary determination circuit 17.
The phase error calculation circuit 18 multiplies the provisional discrimination result of the provisional ternary discrimination circuit 17 by the difference between the odd-numbered column sampling data immediately before and immediately after one sampling of the reproduction data that was the discrimination target, thereby sampling by AD conversion. Calculate timing error.
The voltage controlled oscillation circuit 19 outputs a sampling clock generated by adjusting the frequency based on the input phase error calculation result. That is, the frequency of the generated sampling clock is instantaneously increased if the input phase error calculation result is a positive value, and is instantaneously decreased if the input phase error calculation result is a negative value. The sampling clock is supplied to the AD converter 10 and each circuit block as it is or as a recovered clock after frequency division.
FIG. 10 is a timing chart showing the relationship between the reproduction differential waveform signal, the sampling clock, and the reproduction clock obtained by dividing the sampling clock by two in the conventional apparatus shown in FIGS.
In FIG. 10, points a to n are sampling timings by the sampling clock in the AD converter 10, and here, the values of the digital data obtained by sampling are represented by symbols “A” to “N”, respectively. .
8 and 9, the reproduced differential waveform signal is sampled by the AD converter 10 at every rising edge of the sampling clock, and the data in the portion synchronized with the rising edge of the sampling clock and the rising edge of the reproduced clock is reproduced data. “C”, “E”, “G”, “I”, “K”, “M”. The other “D”, “F”, “H”, “J”, and “L” are phase data. In order to simplify the explanation, a single frequency is used for the reproduced differential waveform signal.
FIG. 10A shows a case where the phase of the reproduced differential waveform signal and the sampling clock are matched. In this case, the determination result output by the provisional ternary determination circuit 17 is other than “0” when the determination result for “E” is “1” and the determination result for “K” is “−1”. Yes, the phase error calculation result output from the phase error calculation circuit 18 is “DF” (= {D−F} × {1}) and “L−J” (= {J−L} × {−1). }). Here, in the phase of FIG. 10A, the values of “DF” and “LJ” are almost zero, so the frequency of the sampling clock generated in the voltage controlled oscillation circuit 19 is maintained, and the phase Will remain matched to the reproduced differential waveform signal.
FIG. 10A shows a case where the phase of the sampling clock is advanced with respect to the reproduced differential waveform signal. Also in this case, the determination result output by the provisional ternary determination circuit 17 is other than “0” because the determination result for “E” is “1” and the determination result for “K” is “−1”. The error calculation results output by the phase error calculation circuit 18 are “D−F” (= {D−F} × {1}) and “L−J” (= {J−L} × {− 1}). Here, since the values of “DF” and “LJ” are both negative in the phase of FIG. 10A, the frequency of the sampling clock generated by the voltage controlled oscillation circuit 19 is instantaneously reduced. The phase shifts in a direction that is delayed with respect to the reproduced differential waveform signal, that is, in a direction in which the phases match.
FIG. 10C shows a case where the phase of the sampling clock with respect to the reproduced differential waveform signal is delayed. Also in this case, the determination result output from the ternary determination circuit 15 is other than “0” when the determination result for “E” is “1” and the determination result for “K” is “−1”. The error calculation results output from the error calculation circuit are “D−F” (= {D−F} × {1}) and “L−J” (= {J−L} × {−1}). It becomes each value of. Here, in the phase of FIG. 10C, the values of “DF” and “LJ” are both positive, so the frequency of the sampling clock generated by the voltage controlled oscillation circuit 19 increases instantaneously. The phase shifts in the direction of advance with respect to the reproduced differential waveform signal, that is, in the direction in which the phases match.
As described above, the conventional digital signal reproducing apparatus having the above-described configuration shown in FIG. 10 can detect the phase shift of the sampling clock even if there is an equalization residue in the differential waveform signal after the pre-equalization. Therefore, accurate phase detection can be performed.
[Problems to be solved by the invention]
However, the conventional configuration having the configuration shown in FIGS. 8 and 9 may cause the following problems.
(1) In order to suppress the equalization error with respect to the signal after (1 + D) that is finally input to the ternary discrimination circuit adopted as data, (1 + D) equalization is performed from the result of ternary discrimination after processing. It is necessary to perform an adaptive equalization by calculating an error. In this case, it is necessary to perform an integral equalization of (1 + D) before the adaptive equalization circuit, and a high frequency signal including a sampling timing is lost. In addition, the subsequent phase error calculation becomes impossible.
This will be described with reference to FIG.
FIG. 11 shows a signal after performing (1 + D) processing on the reproduced differential waveform signals of FIGS. 10A, 10A, and 10C by a solid line, and a signal before (1 + D) processing by a broken line. Show.
In FIG. 11, points a to n are sampling timings based on the sampling clock in the AD converter 10, and here, the values after the (1 + D) processing are respectively represented by the sign “A” for the digital data obtained by sampling. "To" N '".
8 and 9, the reproduced differential waveform signal is sampled by the AD converter 10 at every rising edge of the sampling clock, and the data in the portion synchronized with the rising edge of the sampling clock and the rising edge of the reproduced clock is reproduced data. “C ′”, “E ′”, “G ′”, “I ′”, “K ′”, “M ′”. Other “D ′”, “F ′”, “H ′”, “J ′”, and “L ′” are phase data.
FIG. 11A shows a case where the phase of the reproduced differential waveform signal and the reproduced clock are in agreement, and the discrimination result output by the provisional ternary discrimination circuit 17 is other than “0”, “E ′”, The determination result for “G ′” is “1”, the determination result for “K ′”, “M ′” is “−1”, and the phase error calculation result output by the phase error calculation circuit 18 is “ D′−H ′ ”(= {(D′−F ′) + (F′−H ′)} × {1}) and“ N′−J ′ ”(= {(J′−L ′) + ( L′−N ′)} × {−1}). Here, in the phase of FIG. 11A, the values of “D′−H ′” and “N′−J ′” are both positive, and the frequency of the sampling clock generated in the voltage controlled oscillation circuit 19 is instantaneously large. Thus, the phase changes in the direction of advance with respect to the reproduced differential waveform signal.
FIG. 11A shows a case where the phase of the reproduction clock is advanced with respect to the reproduction differential waveform signal. The determination result output by the provisional ternary determination circuit 17 is other than “0”, “E ′”. The determination result for “G ′” is “1”, the determination result for “K ′”, “M ′” is “−1”, and the phase error calculation result output by the phase error calculation circuit 18 is “ D′−H ′ ”(= {(D′−F ′) + (F−H ′)} × {1}) and“ N′−J ′ ”(= {(J′−L ′) + (L '−N ′)} × {−1}). Here, in the phase of FIG. 11A, each value of “D′−H ′” and “N′−J ′” is positive, and the frequency of the sampling clock generated in the voltage controlled oscillation circuit 19 is instantaneously large. Thus, the phase changes in the direction of advance with respect to the reproduced differential waveform signal.
FIG. 11C shows a case where the phase of the reproduction clock is delayed with respect to the reproduction differential waveform signal. The determination result output by the provisional ternary determination circuit 17 is other than “0”, “E ′”, “ The determination result for G ′ ”is“ 1 ”, the determination result for“ K ′ ”,“ M ′ ”is“ −1 ”, and the phase error calculation result output by the phase error calculation circuit 18 is“ D ”. “−H ′” (= {(D′−F ′) + (F′−H ′)} × {1}) and “N′−J ′” (= {(J′−L ′) + (L '−N ′)} × {−1}). Here, in the phase of FIG. 11C, each value of “D′−H ′” and “N′−J ′” is positive, and the frequency of the sampling clock generated in the voltage controlled oscillation circuit 19 is instantaneously large. Thus, the phase changes in the direction of advance with respect to the reproduced differential waveform signal.
As described above, in all cases, the phase advances. In the conventional digital signal reproducing apparatus having the above-described configuration shown in FIG. 11, the phase shift of the sampling clock is different from the differential waveform signal after the integration equalization. Detection is impossible and accurate phase detection cannot be performed.
(2) Also, the input reproduced differential waveform signal is input to the equalization circuit in a state in which variations in frequency characteristics of the electromagnetic conversion system or noise components applied in the electromagnetic conversion system are superimposed. The equalizing circuit needs to remove all of these factors and match the reproduced digital data to the reference level for ternary discrimination. When an equalization error is actually calculated for data before (1 + D) processing, a calculation speed for each reproduction data, that is, for each reproduction clock is required, and a wide equalization band is required in terms of circuit.
This will be described with reference to FIG.
FIG. 12 is a timing chart showing a relationship between an equalization error and a sampling clock, a reproduction clock, and a reproduction differential waveform signal in the example of the conventional apparatus shown in FIGS.
In FIG. 12, points a to n are sampling timings by the sampling clock in the AD converter 10, and here, the values of the digital data obtained by sampling are represented by symbols “A” to “N”, respectively. . Further, (a) represents the signal waveform before (1 + D) that is the output of the transversal filter 11, and (a) represents the phase error calculated from the signal waveform of (a).
8 and 9, the reproduced differential waveform signal is sampled by the AD converter 10 at every rising edge of the sampling clock, and the data in the portion synchronized with the rising edge of the sampling clock and the rising edge of the reproduced clock is reproduced data. “C”, “E”, “G”, “I”, “K”, “M”. Other “D”, “F”, “H”, “J”, “L”, “N” are phase data.
In FIG. 12, a broken line indicates a reproduction differential waveform signal from the electromagnetic conversion system when the frequency characteristic is sufficient, and each reproduction data is a positive value or a negative value reference level (positive ref, negative ref in FIG. 12) or the like. There is no conversion error component.
On the other hand, in the reproduction differential waveform signal from the electromagnetic conversion system in which the band characteristic is deteriorated by 1/2 or more of the data rate as shown by the solid line, the reproduction data of “G” and “I” has a positive or negative reference level. An error component is generated, and equalization errors are positive and negative values, respectively. In this case, it is necessary to calculate the equalization error of “I” after one reproduction clock of the equalization error of “G”, and the band of the equalization error calculation circuit is also up to a half of the data rate according to the sampling theorem. Necessary.
The present invention solves the above-mentioned conventional problems (1) and (2), so that adaptive equalization and accurate phase detection can be performed for the equalization error of the final ternary discrimination result. It is an object of the present invention to provide a digital signal reproducing apparatus.
[Means for Solving the Problems]
In order to solve each of the above problems, the digital signal reproducing apparatus of the present invention performs AD conversion sampling with a clock having a rate twice as high as the data rate, and adapts the (1 + D) processed signal to an adaptive type. An adaptive equalization means for performing the conversion, and a high frequency component output from the adaptive equalization means is not lost (1 + D). Sampling timing error of AD conversion is performed using sampling data other than reproduction data among data before processing. It is characterized by calculating.
This makes it possible to perform optimal equalization for the ternary discrimination after the (1 + D) processing for final data detection, and to generate a recovered clock with little phase jitter even when timing calculation is performed in a state where there is an equalization residue. Can be generated.
DETAILED DESCRIPTION OF THE INVENTION
According to a first aspect of the present invention, there is provided a digital signal reproducing apparatus for quantizing an input signal with a sampling clock having a rate twice as high as a data rate, and a delay output of an output of the quantization means. Adaptive equalization means using a transversal filter that suppresses intersymbol interference of the input signal by weighting and adding by multiplication with tap coefficients controlled adaptively, respectively, and the output of the quantization means The first integral equalizing means for integrating and equalizing, the second integral equalizing means for integrating and equalizing the signal pre-equalized by the adaptive equalizing means, and the adaptive equalizing means output Phase error calculating means for calculating sampling timing error in the quantizing means using odd column sampling data every other sampling clock as phase error extraction data among data to be processed Ternary discrimination means for performing ternary discrimination of positive value, zero value, or negative value by using, as reproduction data, arithmetic sequence sampling data every one sampling clock among data output from the second integration equalization means, Correlation for calculating the correlation between the equalization error calculation means for calculating the equalization error from the determination result of the ternary determination means and the output from the second integration equalization means and the output from the equalization error extraction means Value calculating means, and the tap coefficient of the adaptive equalizing means is updated as needed from the calculation result from the correlation value calculating means.
According to these configurations, in the data after AD conversion with a sampling clock twice the data rate, reproduction equalization adaptively pre-equalizes the ternary discrimination result after (1 + D) processing, When sampling timing is detected, (1 + D) an AD conversion sampling timing error is calculated from pre-equalized data before processing.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of the digital signal reproducing apparatus according to the first embodiment. FIG. 2 is a block diagram showing a specific configuration example of the main block of FIG. 1 showing a configuration example of the digital signal reproduction apparatus of the first embodiment.
In FIG. 1, 10 is an AD conversion circuit which is a quantization means for quantizing an input signal with a sampling clock having a rate twice as high as the data rate, and 11 is adapted to the delayed output of the output of the AD conversion circuit 10, respectively. A transversal filter, which is an adaptive equalization means using a transversal filter that suppresses intersymbol interference of an input signal by weighting and adding by multiplication by a tap coefficient controlled in an automatic manner, and 12 is an AD conversion circuit Reference numeral 14 denotes a first integration equalizer which is a first integration equalization means for integrating and equalizing 10 outputs, and 14 is a second integration equalization means for integrating and equalizing the output from the transversal filter 11. A certain second integration equalizer 18 is provided with odd-numbered column sampling data every other sampling clock among the data output from the transversal filter 11. A phase error calculation circuit, which is a phase error calculation means for calculating a sampling timing error in the AD conversion circuit 10 as phase data, 15 is a sampling of an even number every sampling clock out of data output from the second integration equalizer 14. A ternary discriminating circuit, which is a ternary discriminating means for performing ternary discriminating between data as reproduction data, positive value, zero value, and negative value, 16 calculates an equalization error from the discrimination result of the ternary discriminating circuit 15 and the like An equalization error calculation circuit 13 which is an equalization error calculation means, and a correlator 13 which is a correlation value calculation means for calculating the correlation between the output from the first integral equalizer 12 and the output from the equalization error calculation circuit 16. is there.
The operation of the digital signal reproducing apparatus of the present embodiment configured as described above will be described below.
In FIG. 1, an AD conversion circuit 10 as a quantizing means samples an inputted reproduced differential waveform signal with a sampling clock having a rate twice as high as the data rate and outputs it as digital data. For this digital data, every other sampling data is used as reproduction data, and the data in between is output as phase data.
As shown in FIG. 2, for example, the transversal filter 11 as an adaptive equalization means includes 2N delay units 111a to 111k having a delay unit of 2 sampling periods, and taps from a correlator 13 described later on each tap output. Multipliers 112 to 112k for multiplying the coefficients and adders 113 for adding the outputs of the respective multipliers, and pre-equalization is performed by suppressing the intersymbol interference of the input signal by multiplying each tap output by a suitable coefficient. . Here, the number of delay units (a to k) +1 is used, but the number of taps is arbitrarily set according to the performance required for the system.
As shown in FIG. 2, for example, the second integrating equalizer 14 as an integrating equalizing means includes a delay unit 141 that delays two sampling periods and an adder 142. The second integrating equalizer 14 at the current time with respect to the pre-equalized signal. (1 + D) equalization processing is performed by adding the input reproduction data and the reproduction data one sample before at the data rate.
A ternary discrimination circuit 15 as ternary discrimination means performs ternary discrimination of digital data equalized by (1 + D) by the second integrator equalizer 14 and outputs the discrimination result. That is, if the input digital data is larger than the positive threshold level, it is determined as “+1”, if it is smaller than the negative threshold level, it is determined as “−1”, otherwise it is determined as “0”. .
As shown in FIG. 2, for example, the equalization error calculation circuit 16 as an equalization error calculation means includes a subtracter 171 and a switching circuit 172. A ternary discrimination circuit corresponding to an input from the transversal filter 11 is provided. The difference with the reference value with respect to 15 discrimination results is performed. That is, if the determination result is “+1”, it corresponds to a positive reference level (positive ref in FIG. 2), and if it is “−1”, it corresponds to a negative reference level (negative ref in FIG. 2) and the determination result. If the difference value of the digital data is “0”, the digital data corresponding to the determination result is output as an equalization error.
As shown in FIG. 2, for example, the first integrating equalizer 12 as an integrating equalizing means includes a delay unit 121 that delays two sampling periods and an adder 122, and inputs AD converted data at the current time. (1 + D) equalization processing is performed by adding the reproduced data and the reproduced data one sample before at the data rate.
For example, as shown in FIG. 2, a correlator 13 serving as a correlation value calculation means includes delay units 133a to 133k for adjusting the time axis to each tap output of the transversal filter 11, and an equalization error corresponding to each delay unit output. The multipliers 132 to 132k for multiplying the equalization error signal from the arithmetic circuit 16, the multipliers 131 to 131k for multiplying the outputs of the multipliers, and the coefficient units 130 to 130k for weighting the outputs of the multipliers, The tap coefficient for each tap of the versatile filter 11 is output and updated.
The provisional ternary discriminating circuit 17 performs ternary discriminating between positive value, zero value, and negative value by using the digitized data sampled every one sampling clock among the pre-equalized digital data from the transversal filter 11 as reproduction data. And output as a provisional discrimination result. The discrimination method is the same as that of the ternary discrimination circuit 15.
As the phase error calculation means, the phase error calculation circuit 18 multiplies the provisional determination result of the provisional ternary determination circuit 17 by the difference between the odd-numbered column sampling data immediately before and after one sampling of the reproduction data to be determined. The sampling timing error in the conversion is calculated.
The voltage controlled oscillation circuit 19 outputs a sampling clock generated by adjusting the frequency based on the input phase error calculation result. That is, the frequency of the generated sampling clock is instantaneously increased if the input phase error calculation result is a positive value, and is instantaneously decreased if the input phase error calculation result is a negative value. The sampling clock is supplied to the AD converter 10 and each circuit block as it is or as a recovered clock after frequency division.
3, 4, and 5 are timing charts showing the relationship between the sampling clock, the reproduction clock obtained by dividing the sampling clock by two, and the reproduction differential waveform signal in the digital signal reproduction apparatus of the first embodiment shown in FIGS. 1 and 2. It is.
3, 4, and 5, points a to n are sampling timings by the sampling clock in the AD converter 10, and here, the values of the digital data obtained by sampling are denoted by “A” to “N”, respectively. It is represented by Further, (a) shows the signal waveform before (1 + D) that is the output of the transversal filter 11, (a) shows the signal waveform after (1 + D) that is the output of the second integrator equalizer 14, and (c). (B) represents the equalization error of the reproduction data with respect to the signal after (1 + D) of (A), and (D) represents the phase error calculated from the signal waveform of (A). In order to simplify the explanation, a single frequency is used for the reproduced differential waveform signal.
In the apparatus of the first embodiment shown in FIGS. 1 and 2, the reproduced differential waveform signal is sampled by the AD converter 10 at every rising edge of the sampling clock, and data in a portion synchronized with the rising edge of the sampling clock and the rising edge of the reproduced clock. As shown in (a), the reproduction data is “C”, “E”, “G”, “I”, “K”, “M”. The other “D”, “F”, “H”, “J”, and “L” are phase data. Also, the reproduction data in the signal after (1 + D) is “C ′”, “E ′”, “G ′”, “I ′”, “K ′”, “M ′” as shown in (A). .
FIG. 3 shows a case where the reproduced differential waveform signal and the sampling clock are in phase. In this case, the equalization error is calculated by calculating an error component with a positive or negative reference level for the data after (1 + D) of (A), and as shown in (C), “G ′”, “I A negative value, a positive value, and a positive value equalization error are calculated at the timing of the reproduction data of “” and “M”. The equalization error is multiplied by the multiplication result of each tap output of the transversal filter 11 subjected to the equalization error calculation by the correlator 13 and multiplied by the weighting coefficient of each tap to obtain a new tap coefficient, etc. It acts to minimize the conversion error.
On the other hand, the phase error is calculated for the data before (1) + (1 + D). The determination result output by the provisional ternary determination circuit 17 is other than “0” when the determination result for “E” is “1” and the determination result for “K” is “−1”. The phase error calculation result output from the calculation circuit 18 is “DF” (= {D−F} × {1}) and “L−J” (= {J−L} × {−1}). Value. Here, since the values of “DF” and “LJ” are almost zero in the phase of FIG. 3, the frequency of the sampling clock generated in the voltage controlled oscillation circuit 19 is maintained, and the phase is also reproduced and differentiated. It remains matched to the waveform signal.
FIG. 4 shows a case where the phase of the sampling clock is advanced with respect to the reproduced differential waveform signal. Even in this case, the equalization error is calculated by calculating an error component with the positive or negative reference level for the data after (1 + D) of (a), and as shown in (c), “E ′”, “ Equalization errors of positive value, negative value, negative value, positive value, and positive value are calculated at the timing of the reproduction data of G ′ ”,“ I ′ ”,“ K ′ ”, and“ M ′ ”. The tap error of the transversal filter 11 is updated by the correlator 13 with respect to the equalization error so as to minimize the equalization error.
On the other hand, the phase error is calculated for the data before (1) + (1 + D). The determination result output by the provisional ternary determination circuit 17 is other than “0” when the determination result for “E” is “1” and the determination result for “K” is “−1”. The error calculation results output from the error calculation circuit 18 are “DF” (= {D−F} × {1}) and “L−J” (= {J−L} × {−1}). Value. Here, in the phase of FIG. 4, the values of “D−F” and “L−J” are both negative, so the frequency of the sampling clock generated by the voltage controlled oscillation circuit 19 is instantaneously reduced, and the phase Moves in a direction that is delayed with respect to the reproduced differential waveform signal, that is, in phase.
FIG. 5 shows a case where the phase of the sampling clock with respect to the reproduced differential waveform signal is delayed. Even in this case, the equalization error is calculated by calculating an error component with the positive or negative reference level for the data after (1 + D) of (A), and as shown in (C), “C ′”, “ Equalization errors of positive value, positive value, negative value, negative value, and positive value are calculated at the timing of the reproduction data of E ′ ”,“ G ′ ”,“ I ′ ”,“ M ′ ”. The tap error of the transversal filter 11 is updated by the correlator 13 with respect to the equalization error so as to minimize the equalization error.
On the other hand, the phase error is calculated for the data before (1) + (1 + D). The determination result output by the provisional ternary determination circuit 17 is other than “0” when the determination result for “E” is “1” and the determination result for “K” is “−1”. The error calculation results output from the calculation circuit 21 are the values “DF” (= {D−F} × {1}) and “L−J” (= {J−L} × {−1}). It becomes. Here, in the phase of FIG. 5, the values of “DF” and “LJ” are both positive, so the frequency of the sampling clock generated by the voltage controlled oscillation circuit 19 increases instantaneously, and the phase Moves in the direction of advance with respect to the reproduced differential waveform signal, that is, the direction in phase.
FIG. 6 shows the reproduction differential waveform signal, the sampling clock, and the sampling in the digital signal reproduction apparatus of the first embodiment shown in FIGS. 1 and 2 for the reproduction differential waveform signal when the frequency characteristic of the electromagnetic conversion system is deteriorated. It is a timing chart which shows the relationship with the reproduction | regeneration clock which divided the clock by 2.
In FIG. 6, points a to n are sampling timings by the sampling clock in the AD converter 10, and here, the values of the digital data obtained by sampling are represented by symbols “A” to “N”, respectively. . Further, (a) shows the signal waveform before (1 + D) that is the output of the transversal filter 11, (a) shows the signal waveform after (1 + D) that is the output of the second integrator equalizer 14, and (c). Represents the equalization error of the reproduction data with respect to the signal after (1 + D) of (a).
In the apparatus of the first embodiment shown in FIGS. 1 and 2, the reproduced differential waveform signal is sampled by the AD converter 10 at every rising edge of the sampling clock, and data in a portion synchronized with the rising edge of the sampling clock and the rising edge of the reproduced clock. As shown in (a), the reproduction data is “C”, “E”, “G”, “I”, “K”, “M”. The other “D”, “F”, “H”, “J”, and “L” are phase data. Also, the reproduction data in the signal after (1 + D) is “C ′”, “E ′”, “G ′”, “I ′”, “K ′”, “M ′” as shown in (A). .
In FIG. 6, the reproduced differential waveform signal from the electromagnetic conversion system whose band characteristic of 1/2 or more of the data rate has deteriorated is a positive value or a negative value in the reproduction data of “G” and “I” as shown in (a). An error component with the value reference level occurs. However, as shown in (a), an equalization error occurs in the data “G ′” and “K ′” in the data after the (1 + D) processing. Accordingly, the equalization error is calculated by “K ′” after two reproduction clocks with respect to the equalization error of “G ′”. This is because the data band is halved by performing (1 + D) processing, and the band necessary for the equalization error calculation is also halved. Further, by calculating the equalization error from the data after (1 + D), the random noise component included in the data is also suppressed, and a more optimal equalization error calculation can be performed.
With the configuration described above, it is possible to adaptively equalize the reproduction data after the process of performing the final ternary discrimination (1 + D), and the reproduction before the high frequency component is not lost (1 + D) By calculating the phase error using sampling data with less distortion other than data, the phase shift of the sampling clock can be detected.
In the above description of each embodiment 1 of the present invention, the voltage-controlled oscillation circuit 19 corrects the phase of the generated clock by changing the frequency instantaneously. However, for example, a delay device is used. It is possible by other methods.
【The invention's effect】
As described above, the present invention has the following effects. A / D conversion sampling is performed with a sampling clock at a rate twice the data rate, an equalization error is calculated from the reproduced data after (1 + D) processing, and the tap coefficient of the transversal filter is updated adaptively from the equalization error By doing so, the error in the final ternary discrimination can be minimized.
Further, by calculating the equalization error from the reproduction data after the (1 + D) processing, it is possible to suppress the random noise component included in the signal.
Further, when calculating the sampling timing error of AD conversion, the phase error calculating means uses the sampling data other than the reproduction data before the processing (1 + D) which is only pre-equalized by adaptive equalization, and the phase error calculating means performs the AD conversion. By calculating the sampling timing phase error, it is possible to generate a recovered clock with little phase jitter even if the phase error calculation is performed in a state where there remains a differential waveform signal equalization residue.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital signal reproduction apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram showing a configuration example of main blocks of the digital signal reproducing apparatus according to Embodiment 1 of the present invention;
FIG. 3 is an operation explanatory diagram of the digital signal reproducing apparatus according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining the operation of the digital signal reproducing apparatus according to the first embodiment of the present invention.
FIG. 5 is an operation explanatory diagram of the digital signal reproducing apparatus according to the first embodiment of the present invention.
FIG. 6 is an operation explanatory diagram of the digital signal reproducing apparatus according to the first embodiment of the present invention.
FIG. 7 is a block diagram for explaining PR4 in magnetic recording.
FIG. 8 is a block diagram showing a configuration of a conventional digital signal reproducing apparatus.
FIG. 9 is a block diagram showing an example of the configuration of main blocks of a conventional digital signal reproducing apparatus.
FIG. 10 is a characteristic diagram for explaining the operation of a conventional digital signal reproducing apparatus.
FIG. 11 is a characteristic diagram for explaining the operation of a conventional digital signal reproducing apparatus.
FIG. 12 is a characteristic diagram for explaining the operation of a conventional digital signal reproducing apparatus.
[Explanation of symbols]
10 AD converter
11 Transversal filter
12 First integral equalizer
13 Correlator
14 Second integrator equalizer
15 Tri-value discrimination circuit
16 Equalization error calculation circuit
17 Provisional ternary discrimination circuit
18 Phase error calculation circuit
19 Voltage controlled oscillator circuit

Claims (6)

Weighting is performed by quantizing the input signal with a sampling clock at a rate twice the data rate, and multiplying the delayed output of the quantizing means by a tap coefficient that is adaptively controlled. Adaptive equalization means using a transversal filter that suppresses intersymbol interference of the input signal by adding together, and first integration equalization means for integrating and equalizing the output of the quantization means; Second integration equalization means for integrating and equalizing the output from the adaptive equalization means, and odd column sampling data every other sampling clock among the data output from the adaptive equalization means as phase data Of the data output from the phase error calculation means for calculating the sampling timing error in the quantization means and the second integration equalization means, one sampling clock Three-value discriminating means for performing ternary discrimination of positive value, zero value, or negative value using the sampling data of every digit as the reproduction data, and equalization for calculating the equalization error from the discrimination result of the ternary discriminating means Error calculation means, and correlation value calculation means for calculating the correlation between the output from the second integration equalization means and the output from the equalization error calculation means, and from the calculation result from the correlation value calculation means A digital signal reproducing apparatus configured to update the tap coefficient of the adaptive equalization means as needed. 2. The digital signal reproducing apparatus according to claim 1, wherein the integration equalization means adds the input signal and a signal obtained by delaying the input signal by 1 bit to perform a partial response (1 + D) operation. 2. The digital signal reproducing apparatus according to claim 1, wherein the equalization error calculation means calculates and outputs a difference between an input signal to the ternary discrimination means and a reference value of the ternary discrimination result. The correlation value calculating means multiplies the output of the equalization error calculation output and the output of the first integration equalization means with a delay corresponding to the result of the equalization error calculation, and performs weighting for each tap to adapt. 2. The digital signal reproducing apparatus according to claim 1, wherein the equalization coefficient of each tap of the type equalizing means is used. The phase error calculation means performs provisional ternary discrimination of positive value, zero value, or negative value by using, as reproduction data, the arithmetic sequence sampling data every one sampling clock among the data output from the adaptive equalization means, and the provisional discrimination 2. The digital signal processing apparatus according to claim 1, wherein the sampling timing error in the quantization means is calculated by multiplying the difference between the odd-numbered column sampling data immediately before and after the reproduction data to be discriminated. Signal reproduction device. 2. A digital signal reproducing apparatus according to claim 1, wherein the signal input to the quantizing means is a differential waveform.

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