JP3779385B2 - Disk array controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk array device having a plurality of disk drives, and more particularly to a disk array control for controlling access to a disk drive by including a cache memory for temporarily storing transfer data between the disk drive and a host device. Relates to the device.
[0002]
[Prior art]
The disk array device has multiple disk drives, and the data from the host device is distributed and stored in these multiple disk drives (the storage media attached to them), enabling parallel access and increasing access speed. Is intended.
[0003]
The disk array device is provided with a disk array control device for controlling access to the disk drive. This disk array control device generates parity data as data correction information for transfer data (write data) from the host device, and writes it to any of the plurality of disk drives. Thereby, even when one of the plurality of disk drives fails, the data of the failed disk drive can be restored by using the parity data and the data of the remaining disk drives. Note that the parity data write destination disk differs depending on the data distribution and arrangement method, and is fixed (as represented by a method called RAID 3) or as represented by a method (called RAID 5). ) It may be switched sequentially.
[0004]
The disk array control device generally has a cache memory (disk cache) for temporarily storing transfer data between the disk drive and the host device, and the target data exists in the cache memory. In this case, the target data can be accessed at high speed from the cache memory without accessing the disk drive (with mechanical access operation).
[0005]
[Problems to be solved by the invention]
In the conventional disk array control device described above, parity data is generated for write data from the host device, the parity data is stored in the disk drive, and the original data is restored using the parity data. However, it is necessary to configure the control device itself as a hardware device dedicated to parity data generation and data restoration by a firmware program in the control device.
[0006]
However, there is a problem of processing speed when using the firmware, and there is a problem that the circuit becomes complicated with dedicated hardware.
The present invention has been made in view of the above circumstances, and an object of the present invention is to generate parity data or restore data by using read / write data at the time of accessing the cache memory on the disk cache means side having the cache memory. It is an object of the present invention to provide a disk array control device capable of simplifying the configuration, speeding up processing, and facilitating control by providing functions.
[0007]
[Means for Solving the Problems]
The disk control apparatus of the present invention includes external input / output means for controlling input / output to / from an external host device, and N disk drives in which a data stream from the host device is divided and distributed in a predetermined size. Disk drive input / output means enabling connection with a disk drive group, disk cache means having a cache memory for temporarily storing transfer data between the disk drive and the host device, and main control for controlling each part The disk cache means includes an exclusive OR circuit for performing an exclusive OR operation in bit units between two data, read / write data to the cache memory, and the exclusive logic. First-in first-out storage means for temporarily storing either one of the exclusive OR operation results of the sum circuit Disk cache control means for controlling the entire disk cache means including access control to the cache memory, access control to the storage means, and control of the exclusive OR circuit, and the disk cache control means In other words, when data is read from the cache memory in response to an instruction from the main control means, the data read from the cache memory is written to the storage means or read from the cache memory. The exclusive OR operation of the data and the data written in the storage means at that time is performed by the exclusive OR circuit, and the exclusive OR operation result is rewritten in the storage means, or Output as cache memory read data By controlling the operation, the data written in the cache memory is used to generate parity data that is the exclusive OR operation result of the data distributed and arranged in the corresponding areas of the N disk drives. Output.
[0008]
Further, the present invention provides a function for performing the following control to the disk cache control means, that is, when data is written to the cache memory in accordance with an instruction from the main control means, the data written to the cache memory is stored in the storage means. Or the exclusive OR operation of the data written in the cache memory and the data written in the storage means at that time is performed by the exclusive OR circuit, and the result of the exclusive OR operation By having the function of controlling the operation of rewriting the data in the storage means, using the data written in the cache memory, the exclusive OR operation of the data distributed in the corresponding areas of the N disk drives Parity data as a result is generated and output.
[0009]
In the disk array control device having such a configuration, the disk cache means side has a function of generating parity data using read / write data when accessing the cache memory, thereby simplifying the configuration and processing. High speed and easy control can be achieved.
[0010]
The present invention also provides a function for performing the following sequence processing to the disk cache control means, that is, when a specific read command for instructing data reading from the cache memory is given from the main control means. N data distributed in the corresponding area of the N disk drives including the data specified by the address information attached to is sequentially read, and the first read data is directly stored in the storage means For the second to N−1th read data, the exclusive OR operation of the data and the data written in the storage means at that time is performed by the exclusive OR circuit. The exclusive OR operation result is rewritten in the storage means, and the Nth read data is The exclusive OR operation between the data and the data written in the storage means at that time is performed by the exclusive OR circuit, and the first to Nth results of the exclusive OR operation are obtained. It has a function of performing a sequence process of generating parity data of data and outputting the parity data as read data of the cache memory in response to the specific read command.
[0011]
In the present invention, when the disk cache control unit is given a function of performing the following sequence processing, that is, when a specific write command instructing data writing to the cache memory is given from the main control unit, Write consecutive N write data distributed in the corresponding area of N disk drives in order to the cache memory area specified by the address information attached to the command, and write the first data Sometimes, the data is also written to the storage means, and when the second to Nth data is written, an exclusive OR operation between the data and the data written to the storage means at that time is performed with the exclusive logic. A sequence process in which the exclusive OR operation result is rewritten in the storage means by the sum circuit. To have the function of performing, when writing the N th data, characterized in that as the parity data of the first through N-th data in the storage means is written.
[0012]
In such a disk array control device, only a specific read command or write command is given from the main control means to the disk cache control means in the disk cache means, and the cache data read operation specified by the command is executed. Alternatively, since the sequence processing for parity generation accompanying the cache data write operation is performed, the processing speed can be further increased. In particular, in the parity generation accompanying the cache data write operation, since the parity data can be generated simultaneously with writing to the cache memory, the highest speed can be achieved.
[0013]
Further, the present invention is characterized in that the disk cache control means is constituted by a programmable logic device that can be rewritten from the main control means, and the configuration of the target disk array can be changed by the logic device when the power is turned on. And
[0014]
In such a configuration, functions can be prevented from being reduced for downsizing and speeding up of the apparatus without using an unnecessarily large device.
In the present invention, whether to generate parity data when accessing the cache memory is specified by a predetermined part of the address information passed from the main control means to the disk cache control means for accessing the cache memory. It is characterized by that.
[0015]
In such a configuration, when accessing the cache memory, it is possible to switch between normal cache read / write using only a predetermined portion of the address information and parity generation using cache read / write data.
[0016]
According to the present invention, the external input means, the disk drive input / output means, the disk cache means, and the main control means are interconnected by a standard bus, and the disk cache control means connects the cache memory to the standard bus. It is characterized in that the access is made according to the procedure.
[0017]
In this way, the disk cache means can be connected to the standard bus as an independent configuration, and by connecting to the standard bus of an existing system having disk drives, only a control program is provided and special hardware changes are made. Therefore, it is possible to construct a highly reliable disk subsystem.
[0018]
The present invention is characterized in that the main control means notifies the logic device of the value of N (the number of data stream divisions) via a control register circuit accessible by the main control means. And
[0019]
In such a configuration, the configuration of the disk array can be freely changed from the main control means via the control register circuit even during the operation of the system.
In the present invention, a disk drive different from the N disk drives is assigned as a dedicated disk (parity data storage disk) for storing parity data of data distributed and arranged in the N disk drives. In the disk array configuration in which the N disk drives also serve as parity data storage disks, the parity generation at the time of cache read / write is applied to data restoration, and the disk cache control means The next function, that is, when one of the N disk drives fails, the operation of restoring the data of the disk drive is performed in accordance with an instruction from the main control means. Data and its parity data. The data in the failed disk drive is restored by using the N data excluding the data in the disk drive in the disk cache means and obtaining the exclusive OR operation result of the N data. It is characterized by having a function. If the restored data is stored in a backup disk drive (hot spare disk) in the disk drive group, it can be used in place of the failed disk drive.
In such a configuration, the data on the failed disk can be restored using the read / write data when accessing the cache memory.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a disk array device including a disk array control device according to an embodiment of the present invention.
[0021]
The disk array apparatus of FIG. 1 is composed of a plurality of, for example, six disk drives 10-0 to 10-6 and a disk array control apparatus 20 for controlling access to the disk drives 10-0 to 10-6. .
[0022]
The disk drives 10-0 to 10-5 are, for example, hard disk drives (HDD). Four disk drives 10-0 to 10-3 are for data storage (for data disks), and the disk drive 10-4 is for data correction. Assume that the disk drive 10-5 is allocated for storing parity data as information (for a parity disk) and for a backup disk (referred to as a hot spare disk).
[0023]
Here, a mode is adopted in which the data stream is divided into units of a certain size S, for example, 4 Kbytes (S = 4 Kbytes) and distributed to the disk drives 10-0 to 10-3. . In this case, if the data stream is divided into chunks A0, B0, C0, D0, A1, B1, C1, D1,... Of size S (= 4 Kbytes), chunk Ai (i = 0, 1...) Is a disk. In the drive 10-0, the chunk Bi is arranged in the disk drive 10-1, the chunk Ci is arranged in the disk drive 10-2, and the chunk Di is arranged in the disk drive 10-3. The validators Pi of the chunks Ai to Di are arranged in the disk drive 10-4. These Ai, Bi, Ci, Di, Pi are generally arranged in the same disk area of the disk drives 10-0, 10-1, 10-2, 10-3, 10-4. Here, the number of chunks Ai to Di is called the number of divisions for the data stream.
[0024]
The disk array control device 20 includes a control unit 21, an external input / output unit 22, disk input / output units 23-0 to 23-5, and a disk cache unit 24. The control unit 21, the external input / output unit 22, the disk input / output units 23-0 to 23-5, and the disk cache unit 24 are connected by a local bus, for example, a PCI bus (Peripheral Component Interconnect Bus) 25 known as a standard bus. Interconnected.
[0025]
The control unit 21 includes a microprocessor 211 and a firmware memory (F / W memory) 212 (configured by ROM or RAM), and an F / W program (firmware program) stored in the F / W memory 212. Accordingly, the external input / output unit 22, the disk input / output units 23-0 to 23-5, and the disk cache unit 24 are controlled, and the data transfer performed between them is controlled. The control unit 21 has an interface (control unit interface) 213 for condition-designed programming and the like, and through this interface 213, an operation circuit (logic) of an FPGA (field programmable gate array) 244 described later is provided. decide.
[0026]
The external input / output unit 22 is connected to an external host device (not shown) and controls a procedure for performing data transfer with the PCI bus 25. Specifically, the external input / output unit 22 controls the transfer of data from the host device to the disk cache unit 24 and the disk input / output units 23-0 to 23-5 via the PCI bus 25, and further the disk cache unit. 24. Control is performed to transfer data from the disk input / output units 23-0 to 23-5 to the host device.
[0027]
The disk input / output units 23-0 to 23-5 are connected to the disk drives 10-0 to 10-5, and perform data transfer between the PCI bus 25 and the disk drives 10-0 to 10-5. Control of the procedure of Specifically, data transfer between the external input / output unit 22 and the disk cache unit 24 connected to the PCI bus 25 and the disk drives 10-0 to 10-5 is controlled.
[0028]
As shown in detail in FIG. 2, the disk cache unit 24 includes a cache memory 240, a first-in first-out buffer (FIFO memory) 241, a PCI bus bridge 242 that forms a bus bridge circuit with the PCI bus 25, and a cache memory 240. And a control logic 243 for controlling the FIFO memory 241, an exclusive OR circuit (EX-OR) 245, a bidirectional buffer IC 246, an address buffer IC 247, buffer ICs 248a and 248b, and a control register 249.
[0029]
The cache memory 240 is for temporarily storing write data from the host device, and is composed of, for example, a DRAM group. As shown in FIG. 3, the cache memory 240 is managed by being divided into a plurality of divided areas such as DA, DB, DC, DD. The divided areas DA, DB, DC and DD are used for temporarily storing the chunks Ai, Bi, Ci and Di. It is assumed that data transfer between the cache memory 240 and the PCI bus 25 is performed in units of 32 bytes, for example, according to the procedure of the PCI bus 25 according to a command from the control unit 21.
[0030]
The FIFO memory 241 temporarily stores data from the cache memory 240 or the PCI bus 25, and based on the data from the FIFO memory 241 itself and the data from the cache memory 240 or the PCI bus 25 (exclusive OR circuit). Used to temporarily store the generated parity data. The capacity of the FIFO memory 241 is, for example, 32 bytes that matches the size of one data transfer between the cache memory 240 and the PCI bus 25.
[0031]
The PCI bus bridge 242 exchanges data with the PCI bus 25 and receives commands from the PCI bus 25. Further, the PCI bus bridge 242 transfers the data via the data bus 2401 (considering the direction) between the cache memory 240 and the PCI bus 25 according to the received command, and the FIFO memory 241 (from the cache memory 240 or the PCI bus 25 to the FIFO memory 241 ( Data transfer to the buffer IC 248a) or the exclusive OR circuit 245, transfer from the FIFO memory 241 to the cache memory 240, and transfer from the exclusive OR circuit 245 (corresponding to the buffer IC 248b) to the PCI bus 25. Do as appropriate.
[0032]
The control logic 243 determines whether the access to the cache memory 240 is a normal access mode without parity generation or a parity generation mode with parity generation in accordance with a command received by the PCI bus bridge 242, and according to the determination result For example, read / write timing control to the cache memory 240 is performed. The control logic 243 reads address information for the cache memory 240 from the received command, and outputs an address to the cache memory 240 (and an address buffer IC 247 connected via the address bus 2402).
[0033]
In the present embodiment, the PCI bus bridge 242 and the control logic 243 constitute a control means (disk cache control means) in the disk cache unit 24, for example, a field programmable gate array (programmable logic device). FPGA) 244. The operation circuit of the FPGA 244 is determined by loading (programming) internal logic from the interface 213 of the control unit 21 via the control register 249.
[0034]
The exclusive OR circuit 245 generates parity data by taking the exclusive OR of the data sent via the data bus 2401 and the data read from the FIFO memory 241.
[0035]
Next, basic operations in the present embodiment will be described in order of a disk read operation in response to a disk read request from the host device and a disk write operation in response to a disk write request from the host device.
[0036]
(1) Disk read operation
First, it is assumed that a disk read request is issued from the host device, and the disk read request is transmitted to the control unit 21 via the external input / output unit 22 and the PCI bus 25. When receiving a disk read request from the host device, the control unit 21 determines whether the requested data exists in the cache memory 240 of the disk cache unit 24. This determination method has been well known in the art and is not directly related to the present invention, and therefore the description thereof will be omitted.
[0037]
When the requested data exists in the cache memory 240, the control unit 21 sends a command (cache data read command) for instructing data read from the cache memory 240 to the disk cache unit 24 via the PCI bus 25. The data is sent to the PCI bus bridge 242. For example, 32-bit address information is attached to the cache data read command.
[0038]
In the present embodiment, a range of, for example, 00000000h to 00010000h (the h at the end indicates hexadecimal representation) of the address space indicated by 32-bit address information is allocated for a firmware (F / W) program, The ranges of 10000000h to 1FFFFFFFh and 20000000h to 2FFFFFFFh are all allocated for the cache memory 240. Here, the address of the cache memory 240 is indicated by, for example, the lower 28 bits of 10000000h to 1FFFFFFFh and 20000000h to 2FFFFFFFh. In this embodiment, the first cache memory address of the target data (32 bytes) is indicated by the lower 28 bits of the 32-bit address information attached to the command sent from the control unit 21 to the PCI bus bridge 242. Further, it is a normal access mode in which normal data read / write (herein, data read) for the cache memory 240 is performed according to the value of the upper 4 bits, or data read / write for the cache memory 240 is performed. In addition, it is indicated whether the parity generation mode is to generate parity data using the read / write data. Here, “0001” (1h) indicates the normal access mode, and 0010 ”(2h) indicates the parity generation mode.
[0039]
When the PCI bus bridge 242 receives a cache data read command from the control unit 21 via the PCI bus 25, the PCI bus bridge 242 determines the data flow direction from the command and sends the command to the control logic 243.
[0040]
When the control logic 243 receives the cache data read command from the PCI bus bridge 242, the control logic 243 refers to the upper 4 bits of the address information attached to the command. If “0001”, the control logic 243 is the normal access mode, and “0010”. If the normal access mode is designated, the control logic 243 controls the cache data read in the normal access mode as follows. To do.
[0041]
The control logic 243 controls the bidirectional buffer IC 246 on the data bus 2401 according to the cache data read command received from the PCI bus bridge 242. The control logic 243 controls the address buffer IC 247 on the address bus 2402 to set a cache memory address (first cache memory address) obtained from the address information (the lower 28 bits) attached to the cache data read command. Then, a control signal for data read to the cache memory 240 is generated and output.
[0042]
Then, 32-byte data indicated by the designated cache memory address is read from the cache memory 240 (for example, in units of 4 bytes). The 32-byte data is led to the PCI bus bridge 242 (in units of 4 bytes) via the bidirectional buffer IC 246 and the data bus 2401, and transferred to the external input / output unit 22 via the PCI bus 25 by the PCI bus bridge 242. Is done. The 32-byte data transferred to the external input / output unit 22 is transferred to the host device by the external input / output unit 22.
[0043]
The control unit 21 repeats the output of the cache data read command designating the normal access mode to the PCI bus bridge 242 while switching the address information (lower 28 bits) until all the data requested from the host device is read. .
[0044]
On the other hand, when the data requested by the host device does not exist in the cache memory 240, the control unit 21 controls the disk input / output units 23-0 to 23-3 to transfer the requested data to the disk drive 10-. The data is transferred to the external input / output unit 22 while being read from 0 to 10 −3 to the PCI bus 25 and stored in the cache memory 240 of the disk cache unit 24. The data transferred to the external input / output unit 22 is transferred to the host device by the external input / output unit 22.
[0045]
(2) Disk write operation
Next, it is assumed that a disk write request is issued from the host device and the disk write request is transmitted to the control unit 21 via the external input / output unit 22 and the PCI bus 25. In this case, write data (stream) is transferred from the host device.
[0046]
Upon receiving a disk write request from the host device, the control unit 21 sends a command (cache data write command) for instructing data write to the cache memory 240 via the PCI bus 25 to the PCI bus bridge 242 in the disk cache unit 24. To send. This command has 32-bit address information. The upper 4 bits of this address information are “0001” indicating the normal access mode, and the lower 28 bits indicate the cache memory address.
[0047]
When the upper 4 bits of the address information attached to the cache data write command sent from the control unit 21 to the PCI bus bridge 242 are “0001”, the control logic 243 is used to write the cache data in the normal access mode. Take control. As a result, data transferred from the host device to the PCI bus 25 via the external input / output unit 22 (here, the first 32-byte data of the data stream for writing) is transferred to the data bus 2401 by the PCI bus bridge 242. The data is sent to the cache memory 240 via the direction buffer IC 246 and written into the area in the cache memory 240 indicated by the lower 28 bits of the address information attached to the cache data write command.
[0048]
The control unit 21 caches all the data requested by the host device in units of 32 bytes while switching the address information (the lower 28 bits) while outputting the cache data write command designating the normal access mode to the PCI bus bridge 242. Repeat until written to memory 240.
[0049]
When all the data requested from the host device is written into the cache memory 240, the control unit 21 sequentially reads out the data written in the cache memory 240 using a cache data read command specified in the normal access mode, and inputs / outputs the disk. By performing control to transfer to one of the units 23-0 to 23-3, the data is stored in the corresponding disk drive.
[0050]
The control unit 21 performs control using the above-described normal access mode designation cache data read command while switching the address information (lower 28 bits), and the data written to the cache memory 240 in accordance with the disk write request from the host device. Repeat until all the disk drives 10-0 to 10-3 are stored.
[0051]
When the disk write operation to the disk drives 10-0 to 10-3 is performed, it is necessary to update the corresponding parity data stored in the disk drive 10-4. In this case, the control unit 21 performs control to read out data from the cache memory 240 and generate parity data using a cache data read command designating the parity generation mode. A parity generation operation at the time of reading the cache data will be described with reference to FIGS.
[0052]
(3) Parity generation operation when reading cache data
Now, by the series of disk write operations (2) according to the disk write request from the host device, the requested write data stream is written to the cache memory 240 and the write data written to the cache memory 240 is written to the disk. It is assumed that the drives 10-0 to 10-3 are distributedly arranged. Here, data (chunks) Ai, Bi, Ci, Di of size S (= 4 Kbytes) are written in areas DA, DB, DC, DD of size S (= 4 Kbytes) in the cache memory 240 and the disk drive. It is assumed that 10-0, 10-1, 10-2, and 10-3 are distributed. Chunk Ai is 32-byte data ai1, ai2, ai3... Ain, chunk Bi is 32-byte data bi1, bi2, bi3... Bin, chunk Ci is 32-byte data ci1, ci2, ci3. Byte data di1, di2, di3.
[0053]
First, in order to read the data ai1, bi1, ci1, and di1 and generate the parity data pi1, the control unit 21 generates a parity data pi1 cache data read command, that is, address information whose upper 4 bits are “0010”. The attached cache data read command is sent to the PCI bus bridge 242 via the PCI bus 25. The lower 28 bits of the address information indicate the address of the cache memory 240 in which, for example, the data ai1 of the data ai1, bi1, ci1, di1 is written.
[0054]
When the PCI bus bridge 242 receives a cache data read command from the control unit 21 via the PCI bus 25, the PCI bus bridge 242 determines the data flow direction from the command and sends the command to the control logic 243.
[0055]
When the control logic 243 receives the cache data read command from the PCI bus bridge 242, it refers to the upper 4 bits of the address information attached to the command, and in the case of “0010” as in this example, parity generation is performed. It is determined that the command is a mode-specified cache data read command, and the sequence processing for that is executed as follows.
[0056]
First, the control logic 243 sets the cache memory address (first cache memory address) obtained from the address information (the lower 28 bits) attached to the received command, and sets the control signal for data read to the cache memory 240. By generating and outputting, the target 32-byte data ai1 (first 32 byte data in the chunk Ai) is read from the cache memory 240 to the data bus 2401 via the bidirectional buffer IC 246 (in units of 4 bytes). As shown by reference numeral 41 in FIG. 4, data is written to the FIFO memory 241 via the PCI bus bridge 242 (and the buffer IC 248a).
[0057]
Next, the control logic 243 automatically adds the address to the cache memory 240 by the fixed size S (= 4 Kbytes), and in the four sets of 32-byte data ai1, bi1, ci1, di1 that are the targets of parity generation. The address of the data bi1 is generated. Then, the control logic uses this generated address to send data bi1 (first 32 bytes of data in the chunk Bi) from the cache memory 240 via the bidirectional buffer IC 246 and the data bus 2401, indicated by reference numeral 42 in FIG. Thus, the data is read to the exclusive OR circuit 245 side.
[0058]
At the same time, the control logic 243 reads the data a i1 previously written in the FIFO memory 241 to the exclusive OR circuit 245 side as indicated by reference numeral 43 in FIG.
[0059]
The exclusive OR circuit 245 calculates the exclusive OR of the data ai1 read from the FIFO memory 241 and the data bi1 read from the cache memory 240 in bit units. The exclusive OR operation result (32 bytes) of the exclusive OR circuit 245 is stored in the FIFO memory 241 as indicated by reference numeral 44 in FIG. 4 (via the buffer ICs 248b and 248a) under the control of the control logic 243. Written (in units of 4 bytes).
[0060]
Next, the control logic 243 automatically adds the address to the cache memory 240 by the fixed size S as in the previous time, and generates the address of the data ci1 this time, so that the data ci1 (the head in the chunk Ci) is generated. (32-byte data) is read from the cache memory 240 via the bidirectional buffer IC 246 and the data bus 2401 to the exclusive OR circuit 245 side as indicated by reference numeral 42 in FIG.
[0061]
At the same time, the control logic 243 reads the exclusive OR result of the data ai1 and bi1 previously written in the FIFO memory 241 to the exclusive OR circuit 245 side as indicated by reference numeral 43 in FIG.
[0062]
The exclusive OR circuit 245 performs an exclusive OR operation in units of bits of the data read from the FIFO memory 241 (exclusive OR result of the data ai1 and bi1) and the data ci1 read from the cache memory 240. Take. The exclusive OR result (32 bytes) of the exclusive OR circuit 245, that is, the exclusive OR result of the data ai1 to ci1 is controlled by the control logic 243 as shown by reference numeral 44 in FIG. Written to the FIFO memory 241 (via ICs 248b, 248a).
[0063]
Next, the control logic 243 automatically adds the address for the cache memory 240 by the fixed size S in the same manner as the previous time, and this time generates the address of the fourth data di1, thereby generating the data di1 (chunk Di). The first 32-byte data) is read out from the cache memory 240 via the bidirectional buffer IC 246 and the data bus 2401 to the exclusive OR circuit 245 side as indicated by reference numeral 45 in FIG.
[0064]
At the same time, the control logic 243 reads the exclusive OR result of the exclusive OR results of the data ai1 to ci1 written in the FIFO memory 241 last time to the exclusive OR circuit 245 side as indicated by reference numeral 46 in FIG.
[0065]
The exclusive OR circuit 245 performs an exclusive OR operation in units of bits of the data read from the FIFO memory 241 (exclusive OR result of the data ai1 to ci1) and the data di1 read from the cache memory 240. Take. The exclusive OR result (32 bytes) of the exclusive OR circuit 245 is the parity data pi1 of the data ai1 to di1 (the first 32 byte data ai1 to di1 in the chunks Ai to Di), and the control unit 21 PCI bus bridge (buffer IC 248b and) as indicated by reference numeral 47 in FIG. 4 as if it were read data (from the cache memory 240) specified by the cache data read command (specifying the parity generation mode) from The data is sent to the PCI bus 25 via 242. Parity data pi1, which is an exclusive OR result of the data ai1 to di1 sent to the PCI bus 25, is assigned (assigned to a parity disk by the disk input / output unit 23-4 under the control of the control unit 21. Stored in the disk drive 10-4.
[0066]
Next, the controller 21 sequentially reads the second 32-byte data ai2 to di2 in the chunks Ai to Di from the cache memory 240 and generates a parity data generation mode cache data read command for generating the parity data pi2. The data is sent to the PCI bus bridge 242 via the PCI bus 25. "0010" is set in the upper 4 bits of this address information, and the lower 28 bits indicate the address of the cache memory 240 in which the data ai2 of the data ai2, bi2, ci2, di2 is written.
[0067]
In the disk cache unit 24, in accordance with the second-time parity data generation mode designation cache data read command output from the control unit 21, the same sequence processing as in the first-time parity data generation mode designation cache data read command output The data ai2, bi2, ci2, and di2 are sequentially read from the cache memory 240, exclusive ORed with each other, and parity data pi2 is generated. This is similarly applied to the subsequent data ai2, bi2, ci2, di2 to ain, bin, cin, din in the chunks Ai, Bi, Ci, Di.
[0068]
Parity data generation is performed for all pairs of ai1, bi1, ci1, di1 to ain, bin, cin, and diin the chunks Ai, Bi, Ci, and Di. The chunks Ai, Bi, Ci, and When at least one of Di is updated (disc written), and only a part of the data in the chunks Ai, Bi, Ci, Di is updated, only the corresponding data set Parity data generation by processing is performed.
[0069]
In the above embodiment, the control logic 243 is provided with a sequence processing function, and only one cache data read command designating a parity generation mode is given from the control unit 21. In addition to the data aij designated by the command, In addition, other data bij, cij, dij paired with the data are also automatically updated based on the arrangement interval S between the data aij, bij, cij, dij on the cache memory 240. In the above description, the parity data pij is generated by sequentially reading from the cache memory 240. However, the present invention is not limited to this.
[0070]
For example, the control unit 21 may sequentially issue a cache data read command designating a parity generation mode for reading each data aij, bij, cij, dij to the disk cache unit 24. In this case, every time a cache data read command designating a parity generation mode is given from the control unit 21, data designated by the command is read from the cache memory 240 and stored in the FIFO memory 241 as it is (first time). Cache data read command in the parity generation mode designation), whether the data stored in the FIFO memory 241 at this time is exclusive-ORed and stored in the FIFO memory 241 (second and third times) In the case of a cache data read command designating the parity generation mode), the data stored at that time in the FIFO memory 241 is exclusive-ORed to generate parity data, which is transferred to the disk drive 10-4 (The last parity generation mode for the fourth time In the case of constant of cache data read command).
[0071]
As described above, in the method in which commands are sequentially issued from the control unit 21 to the disk cache unit 24 for each data aij, bij, cij, dij, (cache memory address) in the disk cache unit 24 (internal control logic 243). Since a sequence processing mechanism (including automatic update) is not required, the amount of hardware can be reduced. However, as in the above-described embodiment, the disk cache unit can be obtained only by issuing a cache data read command specifying a parity generation mode once. The operation speed is lower than that in which the parity generation at 24 can be automatically performed.
[0072]
In the embodiment, all the data requested from the host device is written in the cache memory 240, and after the data written in the cache memory 240 is written in the disk drives 10-0 to 10-3, the disk cache unit Although the case where parity generation at 24 is performed (parity generation operation at the time of cache data read), parity data may be generated in parallel using the write data when writing data to the cache memory 240. Is possible.
[0073]
(4) Parity generation operation during cache data write
A parity generation operation at the time of cache data write will be described with reference to FIG.
[0074]
First, in this embodiment, the division size S when the data stream is distributed to the disk drives 10-0 to 10-3 is 32 bytes, which is the size of one data transfer between the cache memory 240 and the PCI bus 25. It is assumed that they match.
[0075]
Now, it is assumed that write data (data stream) accompanying a disk write request from the host device is continuously transferred to the PCI bus 25 via the external input / output unit 22. Here, in order to simplify the description, it is assumed that the size of the write data is 128 bytes and each chunk obtained by dividing the write data in units of 32 bytes is ai, bi, ci, di in order from the top.
[0076]
First, the control unit 21 writes the first data a i into the cache memory 240 and simultaneously writes it into the FIFO memory 241. Therefore, the cache data write command designating the parity generation mode, that is, the address information whose upper 4 bits are “0010” is stored. The attached cache data write command is sent to the PCI bus bridge 242 via the PCI bus 25. The lower 28 bits of this address information indicate the address of the cache memory 240 to which the data ai1 is written.
[0077]
When the PCI bus bridge 242 receives the cache data write command designating the parity generation mode from the control unit 21 through the PCI bus 25, the PCI bus bridge 242 determines the data flow direction from the command and sends the command to the control logic 243.
[0078]
When the control logic 243 receives the first parity mode designation cache data write command from the PCI bus bridge 242, first, the control logic 243 first (first) in the write data (data stream) continuously transferred onto the PCI bus 25. Are written from the PCI bus bridge 242 (via the data bus 2401 and the bidirectional buffer IC 246) to the designated address of the cache memory 240, and as indicated by reference numeral 51 in FIG. Write to the FIFO memory 241 via the buffer IC 248a).
[0079]
Next, the control unit 21 writes a cache data write command designating a parity generation mode via the PCI bus 25 in order to write the second 32-byte data bi into the cache memory 240 and simultaneously write the corresponding data into the FIFO memory 241. The data is sent to the PCI bus bridge 242.
[0080]
When the control logic 243 receives the cache data write command for designating the second parity generation mode sent from the control unit 21 to the PCI bus bridge 242, the control logic 243 receives the second of the write data continuously transferred onto the PCI bus 25. Is written to the designated address of the cache memory 240 from the PCI bus bridge 242 and is transmitted to the exclusive OR circuit 245 side via the PCI bus bridge 242 as indicated by reference numeral 52 in FIG. At the same time, the control logic 243 reads the data a i previously written in the FIFO memory 241 to the exclusive OR circuit 245 side as indicated by reference numeral 53 in FIG.
[0081]
The exclusive OR circuit 245 calculates the exclusive OR of the data ai read from the FIFO memory 241 and the data bi transferred from the PCI bus 25 via the PCI bus bridge 242 in bit units. The exclusive OR result (32 bytes) of the exclusive OR circuit 245 is written into the FIFO memory 241 as shown by reference numeral 54 in FIG. 5 (via the buffer ICs 248b and 248a) under the control of the control logic 243. It is.
[0082]
Next, the control unit 21 writes the cache data write command for designating the parity generation mode via the PCI bus 25 in order to write the third 32-byte data ci to the cache memory 240 and simultaneously write the corresponding data to the FIFO memory 241. The data is sent to the PCI bus bridge 242.
[0083]
Upon receiving the third parity generation mode designation cache data write command sent from the control unit 21 to the PCI bus bridge 242, the control logic 243 receives the third of the write data continuously transferred onto the PCI bus 25. Is written to the designated address of the cache memory 240 from the PCI bus bridge 242 and is transmitted to the exclusive OR circuit 245 side via the PCI bus bridge 242 as indicated by reference numeral 52 in FIG. At the same time, the control logic 243 reads the exclusive OR result of the first data a i and the second data bi written in the FIFO memory 241 last time to the exclusive OR circuit 245 side as indicated by reference numeral 53 in FIG. .
[0084]
The exclusive OR circuit 245 exclusively controls the exclusive OR of the data ai and bi read from the FIFO memory 241 and the data ci transferred from the PCI bus 25 via the PCI bus bridge 242. Take logical OR. The exclusive OR result (32 bytes) of the exclusive OR circuit 245 is written into the FIFO memory 241 as shown by reference numeral 54 in FIG. 5 (via the buffer ICs 248b and 248a) under the control of the control logic 243. It is.
[0085]
Next, the control unit 21 writes a cache data write command designating a parity generation mode via the PCI bus 25 in order to write the fourth 32-byte data di into the cache memory 240 and simultaneously write the corresponding data into the FIFO memory 241. The data is sent to the PCI bus bridge 242.
[0086]
When the control logic 243 receives the fourth parity generation mode designation cache data write command sent from the control unit 21 to the PCI bus bridge 242, the control logic 243 is the fourth in the write data continuously transferred onto the PCI bus 25. Is written to the designated address of the cache memory 240 from the PCI bus bridge 242 and is transmitted to the exclusive OR circuit 245 side via the PCI bus bridge 242 as indicated by reference numeral 52 in FIG. At the same time, the control logic 243 reads the exclusive OR result of the data ai to ci written in the FIFO memory 241 last time to the exclusive OR circuit 245 side as indicated by reference numeral 53 in FIG.
[0087]
The exclusive OR circuit 245 exclusively controls the exclusive OR of the data ai to ci read from the FIFO memory 241 and the data di transferred from the PCI bus 25 via the PCI bus bridge 242. Take logical OR. The exclusive OR result (32 bytes) of the exclusive OR circuit 245, that is, the exclusive OR result of the data a i, b i, c i, d i is written into the FIFO memory 241 as indicated by reference numeral 54 in FIG. . As a result, the parity data pi of the data ai to di is generated in the FIFO memory 241. Parity data pi of the data ai to di generated in the FIFO memory 241 is read out to the PCI bus bridge 242 side as indicated by reference numerals 55 and 55a in FIG. 5 and is sent from the PCI bus bridge 242 to the PCI bus 25. To the disk input / output unit 23-4 and stored in the disk drive 10-4 (allocated for the parity disk).
[0088]
Thereafter, the control unit 21 sequentially reads the disk write data written in the cache memory 240 from the host device using the cache data read command designating the normal access mode, and 1 of the disk input / output units 23-0 to 23-3. It is stored in the corresponding disk drive.
[0089]
In this parity data generation method at the time of cache data write, since the data from the host device can be written to the cache memory 240 and the parity data can be generated at the same time, the operation speed is improved as compared with the method (3). However, the amount of hardware is slightly increased.
[0090]
As described above, when the cache data is read or the cache data is written by the disk cache unit 24 using the write data written to the cache memory 240 or the write data written to the cache memory 240 in response to a disk write request from the host device. However, this parity generation technology is used for the remaining normal disk drives and parity disks when any one of the disk drives 10-0 to 10-3 fails. The present invention can also be applied to data restoration processing in which the data of the failed disk is restored from the data of the disk drive 10-4 and stored in the disk drive 10-5 for backup (hot spare disk).
[0091]
(5) Data restoration in the disk cache unit 24
Therefore, with regard to data restoration in the disk cache unit 24, one of the disk drives 10-0 to 10-3, for example, the disk drive 10-3 has failed. A case will be described as an example in which data is restored using the data of the disk drive 10-4 when the data is written to the cache memory 240. In this data restoration process, since the order of reading data from the disk drive can be managed, unlike the parity generation operation at the time of cache data write in (4), the data stream division size S is set to the cache memory 240. It is not necessary to match the size of one data transfer between the PCI bus 25 and the PCI bus 25.
[0092]
Now, the control unit 21 receives the j th 32-byte data aij to cij of the chunks Ai to Ci stored in the disk drives 10-0 to 10-2 and the chunk Ai stored in the disk drive 10-4. It is assumed that the jth 32-byte data dij of the chunk Di is to be restored from the parity data pij of the jth 32-byte data aij to dij of .about.Di.
[0093]
In this case, the control unit 21 sequentially controls the disk input / output units 23-0 to 23-2 and 23-4 to transfer data from the corresponding disk drives 10-0 to 10-2 and 10-4 to the PCI bus 25. Aij to cij and pij are sequentially read, and a cache data write command designating parity generation using the data aij to cij and pij as write data is sequentially issued to the disk cache unit 24. As a result, the data aij to cij are stored in the FIFO memory 241 (as well as the data aij to cij and pij are written to the cache memory 240) in the same manner as when parity data is generated based on the write data from the host device. , Pij can be generated as an exclusive OR result. Here, the data pij from the disk drive 10-4 is handled as data from the failed disk drive 10-3, and is written in an area in the cache memory 240 that is written when the data dij is read.
[0094]
As is apparent, the exclusive OR result of the data aij to cij, pij described above coincides with the data dij. That is, in the present embodiment, at the time of cache data write from the disk drives 10-0 to 10-2 and 10-4 to the cache memory 240, the data dij can be restored from the write data aij to cij and pij. The data dij restored in the FIFO memory 241 is read to the PCI bus bridge 242 side as indicated by reference numerals 55 and 55a in FIG. 5 and is input / output to the disk via the PCI bus 25 from the PCI bus bridge 242. The data is transferred to the section 23-4 and stored in an area (corresponding to the data aij to cij, pija) in the backup disk drive 10-4. Further, the data dij read from the FIFO memory 241 to the PCI bus bridge 242 side is transferred to the cache memory 240 as indicated by reference numeral 55b in FIG. 5, and the previously written data pij is changed to the data dij. Rewritten.
[0095]
Note that the above-described restoration of the data dij can also be realized by using a cache data read command designated for parity generation. Here, the chunks Ai to Ci stored in the disk drives 10-0 to 10-2 and the parity data Pi of the chunks Ai to Di stored in the disk drive 10-4 are sequentially read (normal access mode). After writing to the cache memory 240 (using the designated cache data write command sequence), the 32-byte data aij to cij, pij (j) of the chunks Ai to Di from the cache memory 240 using the cache data read command sequence designated for parity generation = 0 to n) are read in order to obtain the exclusive OR result of the data aij to cij, pij, that is, the restored data dij.
[0096]
In the configuration of FIGS. 1 and 2, when it is necessary to change the configuration of the disk array due to a system reset (when power is turned on) or a command obtained from the external input / output unit 22, the control unit 21 The (microprocessor 211) selects data mounted in the F / W memory 212, and loads the data from the control unit interface 213 to the FPGA 244 via the control register 249 of the disk cache unit 24. This makes it possible to easily change the target disk array configuration (RAID form). As described above, in the present embodiment, the PCI bus bridge 242 and the control logic 243 of the disk cache unit 24 are realized by using the FPGA 244, thereby reducing the size and speed of the apparatus without using an unnecessarily large device. Therefore, it is possible to prevent the function from being reduced.
[0097]
In this embodiment, the disk cache unit 24 having the cache memory 240 that is accessed according to the procedure of the PCI bus 25 is carded so that it can be directly connected to the PCI bus 25. Thus, by providing the disk cache unit 24 as an independent card configuration and being connectable to the PCI bus 25 (standard bus) of an existing system having a plurality of disk drives, it is only necessary to provide a control program. A highly reliable disk subsystem can be constructed without any special hardware changes.
[0098]
In the series of sequence processing for parity generation at the time of cache data read in the disk cache unit 24 or parity generation at the time of cache data write, a cache data read command designating a parity generation mode from the control unit 21 or The exclusive OR operation is repeatedly performed in accordance with the cache data write command designated by the parity generation mode. The number of data for which this exclusive OR operation is repeated coincides with the data stream division number N. Therefore, in the present embodiment, this division number N (here, 4) is notified from the control unit 21 (inside the microprocessor 211) to the control logic 243 via the control register 249 (accessible by the microprocessor 211). I am doing so. Accordingly, the control unit 21 (internal microprocessor 211) notifies the control logic 243 of the disk cache unit 24 of the division number N via the control register 249, and changes the sequence processing in the control logic 243, Even during system operation, the configuration of the disk array can be freely changed.
[0099]
The above has been described with respect to a case where the present invention is applied to a disk array device having a disk array configuration (represented by RAID 3) in which parity data is stored in a dedicated disk drive (10-4). The parity data can also be applied to a disk array device having a disk array configuration (represented by RAID 5) distributed and arranged in each data disk (disk drives 10-0 to 10-3).
[0100]
【The invention's effect】
As described above in detail, according to the present invention, the disk cache means having a cache memory is provided with a function of generating parity data or restoring data using read / write data when accessing the cache memory. Thus, the configuration can be simplified, the processing speed can be increased, and the control can be facilitated.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a disk array device including a disk array control device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of a disk cache unit 24 in FIG.
FIG. 3 is a view for explaining a procedure for generating parity data from four pieces of data arranged in a predetermined interval S on the disk cache unit 24 in the embodiment;
FIG. 4 is a view for explaining a flow of parity data generation at the time of cache data read in the embodiment;
FIG. 5 is a view for explaining a flow of parity data generation at the time of cache data write in the embodiment;
[Explanation of symbols]
10-0 to 10-5 ... disk drive,
20 ... Disk array control device,
21 ... Control unit (main control means),
22 ... external input / output unit,
23-0 to 235 ... Disc input / output unit,
24 ... disk cache part,
25 ... PCI bus (standard bus),
240 ... cache memory,
241 ... FIFO memory (first-in first-out storage means),
242 ... PCI bus bridge (disk cache control means),
243 ... control logic (disk cache control means),
244 ... FPGA (field programmable gate array, programmable logic device, disk cache control means),
245 ... exclusive OR circuit,
249: Control register.

Claims (6)

Connection between an external input / output unit that controls input / output with an external host device and a disk drive group including N disk drives in which a data stream from the host device is divided and distributed in a fixed size A disk comprising disk drive input / output means, disk cache means having a cache memory for temporarily storing transfer data between the disk drive and the host device, and main control means for controlling each part An array controller,
The disk cache means comprises: an exclusive OR circuit that performs bitwise exclusive OR operation between two data; read / write data for the cache memory; and exclusive OR operation result of the exclusive OR circuit A first-in first-out storage means for temporarily storing any one of the above, and control of the entire disk cache means including access control to the cache memory, access control to the storage means, and control of the exclusive OR circuit A disk cache control means
The disk cache control means is arranged to continuously distribute N arranged in the corresponding areas of the N disk drives when a specific write command for instructing data writing to the cache memory is given from the main control means. The write data is sequentially written to the area of the cache memory designated by the address information attached to the command, and when the first data is written, the data is also written to the storage means. When writing the Nth data, the exclusive OR operation of the data and the data written in the storage means at that time is performed by the exclusive OR circuit, and the exclusive OR operation result is obtained. A sequence process for rewriting to the storage means is performed, and the storage is performed when the Nth data is written. The first through the parity data of the N-th data is written into the stage, and controls so as parity data written in the storage means is written to one disk drive of the disk drive group, the cache Control is performed so that writing of the N write data written in the memory to the N disk drives in the disk drive group is performed after the writing of the parity data.
A disk array control device. The disk cache control means is composed of a programmable logic device that can be rewritten from the main control means, and the configuration of the target disk array can be changed by the logic device when the power is turned on. The disk array control device according to claim 1 . Whether or not to generate the parity data when accessing the cache memory is designated by a predetermined portion of address information passed from the main control means to the disk cache control means for accessing the cache memory. 2. The disk array control apparatus according to claim 1 , wherein the disk array control apparatus is configured as described above. The external input means, the disk drive input / output means, the disk cache means and the main control means are interconnected by a standard bus,
4. The disk array control apparatus according to claim 3, wherein the disk cache control means is configured to access the cache memory according to a procedure of the standard bus. The disk cache means comprises a control register circuit for the logic device, accessible by the main control means,
3. The disk array control apparatus according to claim 2, wherein the main control means notifies the value of N to the logic device via the control register circuit. The disk drives different from the N disk drives in the disk drive group, or the N disk drives store or distribute parity data of data distributed in the N disk drives. Has been placed,
The disk cache control means stores, in the disk drive group, an operation of restoring data of the disk drive in response to an instruction from the main control means when one of the N disk drives fails. Of the N data and the parity data, N data excluding data in the failed disk drive is used in the disk cache means to obtain an exclusive OR operation result of the N data. 2. The disk array control apparatus according to claim 1 , wherein data in the failed disk drive is restored.

Images