JP3780926B2 - Load drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a load driving circuit having an overcurrent protection function.
[0002]
[Prior art]
An example of a load drive circuit having an overcurrent protection function in the power module is shown in FIG. In FIG. 6, a power source 51 and a main transistor 52 are connected in series to a load 50, and the main transistor 52 is driven by the control circuit 57, whereby a large current is passed through the load 50 to drive the load 50. A series circuit of a current detection transistor 53 and resistors 54 and 55 is connected in parallel to the main transistor 52, and both transistors 52 and 53 are driven simultaneously. The main transistor 52 and the current detection transistor 53 are formed in the same chip. The detection resistors 54 and 55 generate a voltage output proportional to the magnitude of the current flowing through the main transistor 52. The control circuit 57 monitors the voltage corresponding to the current value flowing through the main transistor 52 by the detection resistors 54 and 55 through the signal line 56. The control circuit 57 assumes that the system is abnormal when the current value exceeds a predetermined value. The drive of the power transistor 52 is stopped (gate off).
[0003]
In general, the time lag from detection of this abnormality to gate-off is about 5 to 10 μsec. That is, there is a delay τ (= 5 to 10 μsec) from when the current limit value I1 is detected in FIG. 7 to when the current limit operation is actually started.
[0004]
Normally, in order to prevent an excessive current from flowing through the element (main transistor 52) during this time lag and destroying the element, a transistor 58 is provided between the gate and the source of the transistor 52 in FIG. The base terminal is connected to the α point between the resistors 54 and 55, and when the current flowing through the main transistor 52 reaches a predetermined value I2 (see FIG. 7), the gate potential of the main transistor 52 is adjusted to the current flowing through the main transistor 52. There are restrictions. That is, when the voltage at the point α becomes equal to or higher than the operating voltage of the protection transistor 58, the transistor 58 operates to lower the gate voltage of the power transistor 52, thereby limiting the current.
[0005]
At this time, the relationship between the current Im of the main transistor 52, the current ratio A of the transistors 52 and 53, the detection resistance value R, and the operation start voltage Vbe of the protection transistor 58 is as follows:
(Im / A) · R = Vbe
It is represented by In designing the power module, the A value and the R value are determined (selected) so that the Im value does not fall below the maximum operating current of the target load, and the Im value does not exceed the current value that causes element destruction.
[0006]
Normally, the temperature characteristics of the A value and the R value are substantially “0”, whereas the operation start voltage Vbe of the protection transistor 58 has a temperature characteristic of “−2 mV / ° C.” due to physical properties. At room temperature, Vbe (25 ° C.) = 0.6 volts, and at high temperature, Vbe (100 ° C.) = 0.45 volts. Therefore, as shown in FIG. 8, the temperature dependence of the Im value has a large difference between room temperature and high temperature, and the design of the A value and the R value is difficult. In the worst case, the design has not been established, and there has been a problem that causes destruction of the element depending on the temperature.
[0007]
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object of the present invention is to provide a load driving circuit that can easily design an overcurrent protection current value and prevent element destruction due to overcurrent. .
[0008]
[Means for Solving the Problems]
When the control terminal voltage of the overcurrent protection transistor becomes equal to or higher than the operating voltage, the transistor operates and the control terminal voltage of the power transistor is lowered to limit the current. At this time, the relationship between the current Im of the power transistor, the current ratio A of the power transistor to the current detection transistor, the detection resistance value R, and the operation start voltage Vbe of the overcurrent protection transistor is as follows:
Im / A = Vbe / R
It is represented by
[0010]
Here, as described in claim 1 , the overcurrent protection transistor having a negative temperature characteristic has a negative characteristic as the temperature characteristic of the second current detection resistor, and the first current detection resistor If there is no temperature characteristic, the Im value is less affected even when the temperature changes. This facilitates the design of the current value Im for overcurrent protection. That is, the A value and the R value can be easily determined (selected) so that Im does not fall below the maximum operating current of the target load, and Im does not exceed the current value that causes element destruction. It is possible to sufficiently extract the performance of the element without causing destruction.
[0013]
The CrSi film containing a nitrogen component is used as the second current detection resistor as described in claim 2 , and the flow rate ratio of argon gas and nitrogen gas during sputter deposition is adjusted as described in claim 3. Therefore, it is practically preferable to give negative characteristics to the temperature characteristics of the CrSi film containing the nitrogen component.
[0014]
According to a fourth aspect of the present invention , when the second current detection resistor is formed above the portion of the semiconductor substrate where the overcurrent protection transistor is formed in the cross-sectional shape of the semiconductor substrate, the temperature of the overcurrent protection transistor and the second The temperature of the current detection resistor can be made substantially the same.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows an electrical configuration of a load driving circuit in the present embodiment.
[0016]
In FIG. 1, the source terminal of the main power transistor T <b> 1 is connected to the minus terminal of the DC power supply 1. The drain terminal of the main power transistor T1 is connected to the plus terminal of the DC power source 1 via the load 2. In this way, a series circuit of the power source 1, the load 2, and the power transistor T1 is formed.
[0017]
On the other hand, a power source 7 is connected to the control circuit 3. Further, a series circuit of transistors 4 and 5 is connected to the control circuit 3, and a point P1 between the transistors 4 and 5 is connected to a gate terminal of the main power transistor T1 through a resistor 6. Then, when the control circuit 3 turns on the transistors 4 and 5, a voltage is applied to the gate terminal of the main power transistor T1, and the transistor T1 is turned on. As a result, a current can flow through the load 2 through the transistor T1.
[0018]
The transistor T2 and the resistor 8 are connected in series between the source and drain terminals of the main power transistor T1. That is, a series circuit of the first current detection transistor T2 and the first current detection resistor 8 is connected in parallel to the power transistor T1. Transistors T1 and T2 are formed in the same chip. The gate terminal of the transistor T2 is connected to the point P1 through the resistor 6 described above. A point P2 between the transistor T2 and the resistor 8 is connected to the control circuit 3. A voltage output proportional to the magnitude of the current flowing through the main transistor T1 is generated at the detection resistor 8, and the voltage is monitored by the control circuit 3. When the voltage exceeds a predetermined voltage, the current flowing through the main transistor T1 is forced. Will be limited.
[0019]
A transistor T3 and a resistor 9 are connected in series between the source and drain terminals of the main power transistor T1. That is, a series circuit of the second current detection transistor T3 and the second current detection resistor 9 is connected in parallel to the power transistor T1. Transistors T1, T2, and T3 are formed in the same chip. The gate terminal of the transistor T3 is connected to the point P1 through the resistor 6 described above. The transistor T4 is connected between the gate terminals of the transistors T1, T2, and T3 and the source terminal of the main power transistor T1, and the base terminal of the transistor T4 is connected to the point P3 between the transistor T3 and the resistor 9. Has been. A voltage output proportional to the magnitude of the current flowing through the main transistor T1 is generated at the detection resistor 9, and when the voltage exceeds a predetermined value, the transistor T4 is activated to forcibly limit the current flowing through the main transistor T1. Will be added.
[0020]
Regarding the transistor T4 and the resistor 9, FIG. 2 shows a semiconductor substrate on which they are arranged. In FIG. 2, an n ⁻ epitaxial layer 11 is formed on the upper surface of an n ⁺ silicon substrate 10. A p ⁺ region 12 is formed in the surface layer portion of the n ⁻ epitaxial layer 11, and an n ⁺ region 13 is formed in the surface layer portion of the p ⁺ region 12. An n ⁺ region 14 is formed in the surface layer portion of the n ⁻ epitaxial layer 11. A silicon oxide film 15 is formed on n ⁻ epitaxial layer 11, and aluminum wirings 16, 17 and 18 are formed thereon, and aluminum wiring 16 is electrically connected to n ⁺ region 13 through contact hole 19, Similarly, aluminum wiring 17 is electrically connected to p ⁺ region 12 through contact hole 20, and aluminum wiring 18 is electrically connected to n ⁺ region 14 through contact hole 21.
[0021]
On the other hand, a CrSi thin film 22 containing a nitrogen component is formed on the silicon oxide film 15 in FIG. 2 as the resistor 9 in FIG. This film 22 extends in a band shape, and is connected to the above-described aluminum wiring 16 through a barrier metal film 23 at one end thereof. The other end of the belt-like film 22 is connected to the aluminum wiring 25 through the barrier metal film 24. Note that the surface of the substrate is covered with a passivation film 26.
[0022]
Here, the manufacturing method of the CrSi thin film 22 containing a nitrogen component is demonstrated using FIG. This CrSiN film 22 is formed by reactive sputtering. In FIG. 3, a vacuum pump 31 is connected to the chamber 30, and the gas in the chamber 30 can be exhausted by the pump 31. A pair of counter electrodes 32 and 33 are disposed in the chamber 30, and a power source (AC or DC) 34 is connected to both the electrodes 32 and 33. A silicon wafer 35 is disposed on the electrode 32, and a CrSi sintered target 36 is disposed on the electrode 33. The CrSi sintered target 36 has a Cr: Si atomic composition ratio of 1: 1.8. Further, argon gas and nitrogen gas can be supplied into the chamber 30.
[0023]
In the film formation, after the gas in the chamber 30 is discharged, a voltage is applied between the electrodes 32 and 33 while flowing an argon gas. Then, particles (ions) accelerated in the chamber 30 collide with the target 36, and atoms and molecules of the target 36 ejected by the collision are deposited on the silicon wafer 35 to form a CrSi film. At this time, an appropriate amount of nitrogen gas is supplied into the chamber 30 in addition to the argon gas. Then, a CrSi thin film 22 containing a nitrogen component is formed.
[0024]
Next, the operation of the load drive circuit in this embodiment will be described with reference to FIGS.
In FIG. 4, the control circuit 3 in FIG. 1 applies voltage to the gate terminals of the transistors T1, T2, and T3 to turn on the transistors T1, T2, and T3 when the abnormality such as a short circuit does not occur. A current is supplied to the load 2 through the power transistor T1. That is, the control circuit 3 and the transistors 4 and 5 constitute a switching control means, and this switching control means is connected to the power transistor T1 and the control terminals (gate terminals) of the first and second current detection transistors T2 and T3. The transistors T1, T2 and T3 are switching-controlled by adjusting the voltage at the control terminal.
[0025]
The voltage output proportional to the magnitude of the current flowing through the main transistor T1 is generated at the detection resistors 8 and 9 in FIG. At normal time, the detected current does not exceed the current limit value I1 in FIG.
[0026]
On the other hand, when an abnormality such as a short circuit occurs, the value of the current flowing through the main transistor T1 exceeds a predetermined value I1 (timing t1 in FIG. 4). Then, the control circuit 3 starts the driving stop (gate off) operation of the power transistor T1 because the system is abnormal. That is, the control circuit 3 forcibly adjusts the voltage at the gate terminals of the transistors T1, T2, and T3 to the load 2 when the voltage generated between both terminals of the first current detection resistor 8 exceeds a predetermined value. Limit the flowing current. Here, the time lag from when this abnormality is detected to when the gate is turned off is about 5 to 10 μsec.
[0027]
When the current value I2 is larger than the current limit value I1 (timing t2 in FIG. 4), the transistor T4 operates to lower the gate voltage of the power transistor T1 and limit the current flowing through the transistor T1 (FIG. 4). t2 to t3). That is, the overcurrent protection transistor T4 has a base terminal (control terminal) connected between the second current detection transistor T3 and the second current detection resistor 9, and the second current detection resistor 9 When the voltage generated between both terminals exceeds a predetermined value, the voltage at the gate terminals (control terminals) of the transistors T1, T2 and T3 is forcibly adjusted to limit the current flowing through the load 2. Therefore, it is possible to prevent the device from being destroyed due to an excessive current flowing through the device during the time lag.
[0028]
At this time, in this embodiment, the overcurrent protection transistor T4 having a negative temperature characteristic is given a negative characteristic as the temperature characteristic of the current detection resistor 9. Therefore, as shown in FIG. 5, the current values at room temperature and high temperature can be made closer to those in the conventional case of FIG.
[0029]
More specifically, the relationship between the current Im of the main transistor T1, the current ratio A of the transistors T1 and T3, the resistance value R of the detection resistor 9, and the operation start voltage Vbe of the protection transistor T4 is as follows:
(Im / A) · R = Vbe
It is represented by
[0030]
The temperature coefficient of the resistor 9 is set to “−3000 ppm / ° C.”. Therefore, the resistance value R (100 ° C.) of the resistor 9 = R (25 ° C.) × 0.775. Vbe has a temperature characteristic of “−2 mV / ° C.”. Therefore, it is 0.6 volts at room temperature and 0.45 volts at 100 ° C. (0.75 times the room temperature). Therefore, from the above equation, the current Im has a constant value regardless of the temperature.
[0031]
This facilitates the design of the current value (Im) for overcurrent protection of the power module. That is, it is possible to easily determine (select) the A value and the R value so that Im does not fall below the maximum operating current of the target load, and Im does not exceed the current value that causes element destruction. Thus, the performance of the element can be sufficiently extracted without incurring the above. That is, by matching the resistance temperature characteristic with the temperature characteristic of Vbe, the temperature dependence of Im can be reduced, the design of the overcurrent protection current value of the power module can be facilitated, and the element breakdown due to the overcurrent can be prevented. .
[0032]
In the present embodiment, as shown in FIG. 2, a current detection resistor (CrSi thin film resistor) 9 is formed on the portion of the semiconductor substrate where the overcurrent protection transistor T4 is formed. The temperature of 9 is the same, and the fluctuation of Im due to the temperature mismatch between the transistor T4 and the resistor 9 can be prevented.
[0033]
In addition, as shown in FIG. 3, the CrSi thin film resistor is formed by DC magnetron sputtering using a sintered target 36 having a Cr: Si atomic composition ratio of 1: 1.8, and the resistance temperature coefficient is adjusted by sputtering. This can be done by adjusting the flow ratio of Ar and N ₂ during film formation. That is, by using a CrSi film containing a nitrogen component as the second current detection resistor 9 and adjusting the flow rate ratio of the argon gas and the nitrogen gas during the sputtering film formation, the temperature characteristics of the CrSi film containing the nitrogen component are It can have negative characteristics.
[0034]
In FIG. 1, the current detection transistors T2 and T3 are separately formed. This is because the feedback voltage (potential at P2) to the control circuit 3 needs to be generated in proportion to the current flowing through the main transistor T1 regardless of the temperature. A resistance of “0” is used.
[0035]
In FIG. 1, the case where MOS transistors are used for the transistors T1, T2, T3 and a bipolar transistor is used for the transistor T4 has been described. However, these transistors T1, T2, T3, and T4 include MOS transistors, bipolar transistors, and IGBTs. Any of these can be used in any desired combination.
[Brief description of the drawings]
FIG. 1 is a diagram showing an electrical configuration of a load driving circuit in an embodiment.
FIG. 2 is a diagram showing protection transistors and resistors.
FIG. 3 is a view for explaining a method of manufacturing a resistance thin film.
FIG. 4 is a time chart for explaining the operation.
FIG. 5 is a time chart for explaining the operation.
FIG. 6 is an electric circuit diagram for explaining the prior art.
FIG. 7 is a time chart for explaining the prior art.
FIG. 8 is a time chart for explaining the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Power supply, 2 ... Load, 3 ... Control circuit, 4 ... Transistor, 5 ... Transistor, 8 ... Resistance, 9 ... Resistance, T1 ... Main power transistor, T2 ... Current detection transistor, T3 ... Current detection transistor, T4 ... protection transistor.

Claims (4)

A series circuit formed by a power source (1), a load (2), and a power transistor (T1) having a source / drain terminal or an emitter / collector terminal as a connection terminal;
The drain terminal or collector terminal of the first current detection transistor (T2) is connected to the drain terminal or collector terminal of the power transistor (T1), and the source terminal or emitter terminal is connected to one end of the first current detection resistor (8). A series circuit formed by connecting and connecting the other end of the first current detection resistor (8) to the source terminal or emitter terminal of the power transistor (T1);
The drain terminal or collector terminal of the second current detection transistor (T3) is connected to the drain terminal or collector terminal of the power transistor (T1), and the source terminal or emitter terminal is connected to one end of the second current detection resistor (9). A series circuit formed by connecting and connecting the other end of the second current detection resistor (9) to the source terminal or emitter terminal of the power transistor (T1);
The control terminal of the power transistor (T1), the control terminal of the first current detection transistor (T2), and the control terminal of the second current detection transistor (T3) are connected, and the voltage of the control terminal is adjusted. The transistor (T1, T2, T3) is subjected to switching control, and a voltage generated between both terminals of the first current detection resistor (8) causes a first current value (I1) flowing through the power transistor (T1). And control means (3, 4, 5) for forcibly adjusting the voltage at the control terminals of the transistors (T1, T2, T3) to limit the current flowing to the load (2) when a predetermined value corresponding to ,
The control terminals of the transistors (T1, T2, T3) are connected between the source terminals of the transistors (T1, T2, T3) and the source terminals or the emitter terminals of the power transistors (T1) using the source / drain terminals or the emitter / collector terminals as connection terminals. When the current flowing through the power transistor (T1) is larger than the first current value (I1), connected between the second current detection transistor (T3) and the second current detection resistor (9). When the voltage generated between both terminals of the second current detection resistor (9) exceeds a predetermined value corresponding to the second current value (I2) flowing through the power transistor (T1), the transistor (T1, An overcurrent protection transistor (T4) for forcibly adjusting the voltage at the control terminal of T2, T3) to limit the current flowing to the load (2);
A load driving circuit comprising:
The overcurrent protection transistor (T4) having a negative temperature characteristic is given a negative characteristic as the temperature characteristic of the second current detection resistor (9), and the first current detection resistor (8) A load drive circuit characterized by having no temperature characteristics. The load driving circuit according to claim 1 , wherein a CrSi film containing a nitrogen component is used as the second current detection resistor (9). 3. The load drive according to claim 2 , wherein a negative characteristic is imparted to a temperature characteristic of the CrSi film containing a nitrogen component by adjusting a flow rate ratio between the argon gas and the nitrogen gas during the sputtering film formation. circuit. Of claim 1, 2, 3, characterized in that the forming the second current detection resistor above the forming part of the overcurrent protection transistor (T4) (9) in the semiconductor substrate in the cross-sectional shape of the semiconductor substrate The load drive circuit according to any one of the above.

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