JP3781472B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a CMOS transistor.
[0002]
[Prior art]
In the formation of a MOS transistor in a semiconductor integrated circuit, the process of depositing an insulating film and opening a contact hole after forming a transistor region on a substrate will be described with reference to FIG.
[0003]
In recent years, in order to realize high integration of a semiconductor integrated circuit, a distance between an opening of a contact hole 7 of a transistor and an insulating oxide film region (field region) 2 for element isolation has been reduced. As described above, when the distance between the contact and the field region is narrowed, as shown in FIG. 4, when the insulating film 5 is etched away and the insulating film 5 is removed by etching, the contact hole 7 is formed in the substrate 1. There is a problem that the layer region 3 is detached and opens on the field region 2 to generate a junction leakage current.
[0004]
A SAC (se1f-a1ign-contact) technique is generally known as a technique for preventing the occurrence of the leakage current. In this SAC technique, an impurity having the same conductivity type as that of the diffusion layer is injected into the diffusion layer region from the contact opening (plug injection), and a diffusion region is formed at the bottom of the contact hole opening, thereby generating leakage current. Is to prevent.
[0005]
This SAC technique will be described with reference to FIG. FIG. 5 is a cross-sectional view for each process of a transistor portion of one conductivity type in forming a CMOS transistor.
[0006]
First, well formation, formation of an isolation oxide film (field region) 2 and formation of a gate electrode 4 are performed on a silicon (Si) semiconductor substrate 1, and a P ⁺ / N ⁺ type diffusion layer is formed using the gate electrode 4 as a mask. In order to form the region 3, ions of P ⁺ / N ⁺ type are ion-implanted (see FIG. 5A).
[0007]
Subsequently, after the interlayer insulating film 5 is deposited, FA (heat treatment by a furnace annealing apparatus) is performed at a temperature of 850 ° C. for 30 minutes for the purpose of activating the diffusion layer region 3 and reflowing the interlayer insulating film 5 (FIG. 5). (See (b)).
[0008]
Next, through the photolithography process, the interlayer insulating film 5 is etched using the photoresist as a mask to open contact holes 6 and 7 (see FIG. 5C).
[0009]
Thereafter, through the photolithography process, the entire surface of the N ⁺ type diffusion layer region is covered with a photoresist, and using this as a mask, BF ₂ 10 is introduced by ion implantation from the openings of the contact holes 6 and 7 in the P ⁺ type diffusion layer region. Then, the diffusion region 8 is formed at the bottom of the contact hole. Similarly to the P-type diffusion layer region, P ⁺ is introduced into the N ⁺ -type diffusion layer region from the contact holes 6 and 7 6 and 7 by ion implantation to form the diffusion region 8 at the bottom of the contact hole. (See FIG. 5 (d)).
[0010]
Then, for the activation of the diffusion region 8 ion-implanted into the bottom of the contact hole, FA is performed at a temperature of 800 ° C. for 30 minutes.
[0011]
In the above process, two photolithography steps, two ion implantation steps, and one activation step are required to form a diffusion region at the bottom of the contact opening, that is, plug injection.
[0012]
On the other hand, as a technique for implanting inert element ions from the opening of a contact hole, there are JP-A-4-199817 and JP-A-4-246824.
[0013]
Japanese Laid-Open Patent Publication No. 4-199817 relates to a method of manufacturing a semiconductor device in which polycrystalline silicon is selectively deposited in a contact hole to an arbitrary thickness so that no cavities occur and single crystallization does not occur. In other words, an inert element ion is implanted into the bottom surface of the contact hole to make the surface amorphous, and then a polycrystalline silicon film is selectively deposited in the contact hole. That is, in this publication, the surface exposed on the bottom surface of the contact hole is made amorphous, so that polycrystalline silicon is deposited without single crystallization at the time of subsequent selective silicon deposition. However, this publication only discloses a method of depositing polycrystalline silicon embedded in a contact hole without generating a cavity, and is likely to occur when the distance between the contact and the field region is shortened. The problem of leakage current when misalignment occurs is not solved.
[0014]
In Japanese Patent Laid-Open No. 4-246824, in order to reduce contact resistance, silicon (Si) is ion-implanted into the substrate from the opening of the contact hole, and then tungsten (W) is selectively buried in the opening. Is. That is, in this publication, the diffusion rate of impurities in the damaged semiconductor layer is increased by growing tungsten in the opening after causing damage to the diffusion layer by ion implantation of silicon. By utilizing the fact that it becomes faster, tungsten is mixed on the surface of the high concentration diffusion layer to reduce the contact resistance. However, in this publication, after silicon is ion-implanted, tungsten is deposited without performing heat treatment, so that heat treatment for promoting diffusion in the lateral direction of impurities cannot be performed. And after tungsten deposition, heat treatment cannot be applied to promote the lateral diffusion of impurities due to the problem of impurity diffusion between tungsten and the substrate, and this is likely to occur when the distance between the field region and the contact is shortened. It is not possible to prevent leakage current when misalignment occurs. For this reason, in this publication, there is no effect on prevention of leakage current, and the process can be applied only when a sufficient distance between the field region and the contact can be obtained.
[0015]
[Problems to be solved by the invention]
As described above, in the SAC formation according to the conventional technique, it is necessary to implant impurity ions of each conductivity type in each P ⁺ / N ⁺ type diffusion layer region. 2 times and an ion implantation process twice. This leads to an increase in the number of processes, that is, an increase in manufacturing cost, and becomes a problem. Further, there is a problem that an increase in the number of processes causes a decrease in yield.
[0016]
The present invention has been made to solve the above-described conventional problems. Compared to a conventional process that does not perform SAC, the present invention does not increase the photolithography process and performs ion implantation only once. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the same effect, specifically, the generation of a leakage current due to a reduction in the field-contact distance. That is, the purpose is to reduce the manufacturing cost by reducing the photolithography process twice and the ion implantation process once compared with the conventional SAC process.
[0017]
[Means for Solving the Problems]
In the semiconductor device manufacturing method of the present invention, after ion implantation for forming P ⁺ -type and N ⁺ -type diffusion layers is performed on a silicon semiconductor substrate, heat treatment (hereinafter referred to as RTA) by a lamp annealing apparatus is performed. ) alms, subsequently, than the contact hole opening provided respectively on the diffusion layer of the P ⁺ -type and N ⁺ -type, in each of the diffusion layers of the P ⁺ -type and N ⁺ -type below a critical dose of substrate is amorphized After silicon is ion-implanted to form a point defect at the bottom of the contact hole, a heat treatment (hereinafter referred to as FA) is performed by a furnace annealing apparatus.
[0018]
According to the present invention, after the contact hole is formed, the P ⁺ / N ⁺ type diffusion layer region is subjected to heat treatment to cause re-diffusion, and the diffusion region is surrounded by the bottom of the contact hole. This is to obtain a prevention effect. However, with only ordinary heat treatment, the entire diffusion layer region is re-diffused, and also diffuses in the channel direction, shortening the channel length, and the short channel effect becomes significant. In order to prevent this, in the present invention, only the diffusion layer at the bottom of the region where the contact hole is formed is selectively re-diffused. In order to realize this, silicon ions are implanted from the opening of the contact hole to introduce a point defect at the bottom of the contact hole, and the diffusion is selectively performed by causing accelerated diffusion.
[0019]
Specifically, after forming the N ⁺ and P ⁺ type diffusion layer regions, heat treatment of RTA is applied. As a result, the diffusion layer region is activated, and at the same time, the point defects generated at the time of impurity ion implantation for forming the diffusion layer disappear, and the accelerated diffusion hardly occurs. In order to prevent the diffusion layer region from being diffused more than necessary and causing the deterioration of the device special order such as the short channel effect, treatment at a temperature in the range of 950 to 1050 ° C., particularly 1000 ° C. is appropriate. For the same reason, the processing time is 10 seconds or less. However, under this processing condition, there is a concern about the occurrence of junction leakage current due to residual defects. However, in the present invention, since a long time FA is performed later and defects can be eliminated in this process, there is a particular problem. Don't be.
[0020]
A contact hole is formed in this state to the diffusion layer of the P ⁺ -type and N ⁺ -type, ion implantation of Si to the respective diffusion layers of the P ⁺ -type and N ⁺ -type from the opening of the contact hole. As a result, point defects are introduced only in the vicinity of the contact hole region, and the state returns to a state where accelerated diffusion is likely to occur. The ion implantation here is performed in order to introduce a point defect into the substrate, and it is necessary to select an ion species according to the diffusion mechanism of the substrate impurity, but the most suitable ion is Si. Since the purpose is to introduce point defects, it is necessary to carry out implantation at a critical dose amount or less for amorphization, but in the case of Si, it is less than 5 × 10 ¹⁴ cm ⁻² .
[0021]
If FA is performed for a long time at a low temperature after the introduction of the point defect, the impurity diffusion layer is re-diffused only in the point defect introduction region. Even in such a case, the diffusion layer goes under the contact hole and suppresses the generation of leakage current. FA here needs to be performed at a low temperature at which accelerated diffusion occurs but diffusion does not normally occur, and should be set to 800 ° C. or lower, but 750 ° C. is appropriate considering defect recovery and the like. At this temperature, re-diffusion hardly occurs in the point defect unintroduced portion where the accelerated diffusion does not occur, and the problem of the short channel effect does not occur.
[0022]
As the ion species for forming the P ⁺ / N ⁺ type diffusion layer, boron is usually used for forming the P ⁺ type layer, and arsenic is used for forming the N ⁺ type layer. However, in the case of arsenic, accelerated diffusion is less likely to occur compared to boron, so it is effective to use phosphorus, which can be more easily set as the N ⁺ ion species. In the case of formation by phosphorus implantation, it is usually difficult to apply the device because it is very weak against short channel effect due to enhanced diffusion, but in this invention, since RTA treatment is added after implantation, enhanced diffusion is unlikely to occur. It doesn't matter.
[0023]
Further, in the present invention, before performing ion implantation for forming the P ⁺ / N ⁺ type diffusion layer, an inert element such as Si is implanted at an implantation dose greater than the critical dose amount at which the substrate becomes amorphous. It is good to do.
[0024]
Thus, if the substrate is amorphized by implantation of Si or the like before forming the P ⁺ / N ⁺ type diffusion layer region, it is possible to suppress the spread of distribution due to channeling, which becomes a problem during phosphorus ion implantation. In addition, it can be formed into a structure that is strong against the short channel effect.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing one conductivity type transistor portion according to the process when the present invention is applied to the formation of a CMOS transistor.
[0026]
First, well formation, formation of an isolation oxide film (field region) 2 and formation of a gate electrode 4 are performed on a silicon (Si) semiconductor substrate 1, and a P ⁺ / N ⁺ type diffusion layer is formed using the gate electrode 4 as a mask. In order to form the region 3, a P ⁺ / N ⁺ type impurity is ion-implanted and heat treatment (RTA) is performed by a lamp annealing apparatus (see FIG. 1A). This RTA has a treatment temperature in the range of 950 to 1050 ° C. and 10 seconds or less. In this embodiment, the RTA was conducted at a temperature of 1000 ° C. for 10 seconds.
[0027]
Subsequently, after the interlayer insulating film 5 is deposited, the interlayer insulating film 5 is etched through a photolithography process using the photoresist as a mask to open contact holes 6 and 7 (see FIG. 1B).
[0028]
From the openings of the contact holes 6 and 7, an inert element, in this embodiment, Si ions is accelerated at an energy of 80 KeV, and the dose is in the range of 5 × 10 ^{13 to} 5 × 10 ¹⁴ cm ^−2. The injection was performed under the condition of × 10 ¹⁴ cm ⁻² (see FIG. 1C). By this Si ion implantation, a point defect 9 is formed at the bottom of the contact hole.
[0029]
Subsequently, the substrate 1 is subjected to heat treatment (FA) using a furnace annealing apparatus . This FA was performed at a processing temperature of less than 800 ° C. and a processing time of 60 minutes or more, and in this embodiment, at a temperature of 750 ° C. for 2 hours. As described above, when FA is performed at a low temperature for a long time, the impurity diffusion layer re-diffuses only in the point defect introduction region, and the bottom of the contact hole is separated from the diffusion region when the contact hole is formed. Even in such a case, the diffusion layer 8a goes under the contact (see FIG. 1D). The FA here needs to be performed at a low temperature at which accelerated diffusion occurs but normal diffusion hardly occurs, and should be set to 800 ° C. or lower, but 750 ° C. is appropriate considering defect recovery and the like. . At this temperature, re-diffusion hardly occurs in the point defect unintroduced portion where the accelerated diffusion does not occur, and the problem of the short channel effect does not occur.
[0030]
In FIG. 2, the calculation result of the point defect introduction | transduction effect by Si ion by simulation is shown. This figure compares the presence or absence of enhanced diffusion depending on the presence or absence of Si ion implantation, and performs the following process.
[0031]
1) Si ⁺ implantation: acceleration energy 30 KeV, dose amount 5 × 10 ¹⁵ (substrate amorphization)
2) B-ten implantation: acceleration energy 10 KeV, dose amount 3 × 10 ¹⁵
3) RTA: temperature 1000 ° C., time 10 seconds 4) Si ⁺ implantation: acceleration energy 120 KeV, dose 1 × 10 ¹⁴
5) FA: temperature 750 ° C., time 120 minutes
In FIG. 2, A is the state after performing the above process 2), B is the state after performing the above process 3), C is the state after performing 5) without performing 4) of the above process, and D is the above state. The profile of boron (B) in the state carried out through 5) of the process is shown.
[0033]
As is clear from FIG. 2, the profile of C (corresponding to the vicinity of the channel in the diffusion region) where Si is not introduced hardly shows thermal diffusion due to FA, but in D where Si is introduced (diffusion region near the contact). Severe accelerated diffusion is observed. From this, it is shown that the present invention can selectively cause sufficient diffusion only in the contact hole opening.
[0034]
Prepare a semiconductor device fabricated through the above process, a semiconductor device fabricated through a prior art process that does not perform Si implantation, and a semiconductor device that performs Si implantation but heat treatment using the prior art (only high-temperature FA). FIG. 3 shows the result of measuring the leakage current with respect to each field-contact distance.
[0035]
As is apparent from FIG. 3 , according to the present invention, it is understood that the leakage current does not increase even when the field-contact distance is reduced by reducing the design rule.
[0036]
Further, as the ion species for forming the P ⁺ / N ⁺ type diffusion layer, boron is usually used for forming the P ⁺ type diffusion layer, and arsenic is used for forming the N ⁺ type diffusion layer. Although it can be applied as it is, in the case of arsenic, since accelerated diffusion is less likely to occur than boron, it is effective to use phosphorus (P) which can be more easily set as the N ⁺ ion species. In the case of formation by phosphorus implantation, it is usually difficult to apply the device because it is very weak against short channel effect due to enhanced diffusion, but in this invention, since RTA treatment is added after implantation, enhanced diffusion is unlikely to occur. It doesn't matter.
[0037]
In the present invention, before the ion implantation for forming the diffusion layer is performed, the inert element such as Si may be implanted with an implantation amount equal to or higher than the critical dose amount at which the substrate becomes amorphous.
[0038]
Thus, if the substrate is amorphized by implantation of Si or the like before forming the P ⁺ / N ⁺ type diffusion layer region, it is possible to suppress the spread of distribution due to channeling, which becomes a problem during phosphorus ion implantation. In addition, it can be formed into a structure that is strong against the short channel effect.
[0039]
【The invention's effect】
As described above, in the method of manufacturing a semiconductor device according to the present invention, after ion implantation for forming a diffusion layer, RTA is performed, then silicon is ion-implanted from the contact hole opening , and the bottom of the contact hole is formed. after forming the two points defects, by performing F a, without causing a significant increase in the number of steps can be reduced design rules to narrow the inter-field over the contact distance.
[0040]
Further, when the RTA is performed in a processing temperature range of 950 to 1050 ° C. and a processing time of 10 seconds or less, the above-described effect can be realized without causing deterioration of transistor characteristics.
[0041]
Further, by performing FA at a processing temperature of less than 800 ° C. and a processing time of 60 minutes or more, the above-described effects can be realized without causing deterioration of transistor characteristics.
[0042]
Furthermore, before the ion implantation for forming the diffusion layer, the inert element is implanted with an implantation amount greater than the critical dose at which the substrate becomes amorphous. A transistor having a strong effect and good characteristics can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing one conductive type transistor portion by process when the present invention is applied to formation of a CMOS transistor.
FIG. 2 is a simulation diagram comparing the presence or absence of enhanced diffusion depending on the presence or absence of Si ion implantation.
FIG. 3 is a characteristic diagram obtained by measuring a leakage current with respect to a field-contact distance in a semiconductor device manufactured according to the present invention and the prior art.
FIG. 4 is a cross-sectional view showing a problem of a conventional semiconductor device.
FIGS. 5A and 5B are cross-sectional views for each step of a transistor portion of one conductivity type in forming a conventional CMOS transistor. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate 2 Field area 3 Diffusion layer area 4 Gate electrode 5 Interlayer insulating film 6, 7 Contact hole 8a Diffusion layer 9 Point defect

Claims (6)

After ion implantation for forming P ⁺ -type and N ⁺ -type diffusion layers is performed on the silicon semiconductor substrate, heat treatment (hereinafter referred to as RTA) by a lamp annealing apparatus is performed, followed by P ⁺ -type. Then , silicon is ion-implanted into each of the P ⁺ -type and N ⁺ -type diffusion layers from the contact hole opening provided in each of the N ⁺ -type diffusion layers and below the critical dose amount at which the substrate becomes amorphous. A method for manufacturing a semiconductor device, characterized in that after forming point defects, a heat treatment (hereinafter referred to as FA) is performed by a furnace annealing apparatus. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon ion implantation is performed in a dose range of 5 * 10 ^{< 13} > to 5 * 10 ^{< 14} > m ^<-2 >.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the RTA is performed in a processing temperature range of 950 to 1050 [deg.] C. and a processing time of 10 seconds or less.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the FA is performed at a processing temperature of less than 800.degree. C. and a processing time of 60 minutes or more.   2. The semiconductor device according to claim 1, wherein the inert element is implanted at an implantation amount equal to or higher than a critical dose amount at which the substrate becomes amorphous before the ion implantation for forming the diffusion layer is performed. Method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein phosphorus is used as an ion species for ion implantation for forming an N ⁺ type diffusion layer.

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