JP3785237B2 - A / D converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an A / D converter that converts an analog signal (analog input voltage) into a digital signal (digital data) having a predetermined number of bits corresponding thereto.
[0002]
[Prior art]
For example, in a field where high speed and high reliability are required for analog-to-digital conversion, such as digital processing of a video signal, a predetermined number of upper reference voltages generated in accordance with the number of upper bits of the digital signal. A series-parallel comparison that compares each analog signal with an analog signal simultaneously after comparing each analog signal with the analog signal and a predetermined number of lower reference voltages generated according to the number of lower bits of the digital signal. A type of A / D converter is used.
[0003]
Hereinafter, a conventional A / D converter will be described by taking a series-parallel comparison type A / D converter disclosed in Japanese Patent Laid-Open No. 3-165628 as an example.
First, FIG. 2 is a configuration circuit diagram of an example of a conventional series-parallel comparison type A / D converter disclosed in the publication. The A / D converter 42 in the illustrated example has a lower reference resistor string 12, a lower comparator string 14, a lower logic circuit 16, a switch string 18, an upper comparator string 22, and an upper logic circuit 24.
[0004]
In the A / D converter 42, the upper reference voltage string 32 is formed by connecting four lower reference resistor strings 12 in series in the figure, and these four lower reference resistor strings 12 equalize the two reference voltages 26a and 26b. It is created by dividing resistance. The lower reference resistor string 12 is obtained by connecting four resistors Rs in series in the figure. The lower reference voltage string 30 is composed of two upper resistors adjacent to each other in the upper reference voltage string 32 by the four resistors Rs. It is created by equally dividing the reference voltage by resistance.
[0005]
In the A / D converter 42, first, after the analog signal 28 and the upper reference voltage string 32 are simultaneously compared by the upper comparator string 22, the analog signal 28 is converted by the upper logic circuit 24. It is determined which two upper reference voltages adjacent in the upper reference voltage train 32 fall between. That is, the upper bits of the digital signal corresponding to the analog signal 28 converted by the A / D converter 42 are created.
[0006]
Subsequently, the switch row 18 of the lower reference resistor row 12 corresponding to the upper comparison result is turned on, and after the analog signal 28 and the lower reference voltage row 30 are respectively compared by the lower comparator row 14 simultaneously, The lower logic circuit 16 determines between which two adjacent lower reference voltages the analog signal 28 is in the lower reference voltage train 30. That is, the lower bits of the digital signal corresponding to the analog signal 28 are created.
[0007]
Usually, the upper comparator row 22 and the lower comparator row 14 include a capacitive element, and the reference voltages 30 and 32 are compared with the analog signal 28 by charging and discharging the capacitive element. . According to this publication, in the A / D converter 42, when each switch S in the switch array 18 becomes conductive, electric charge is injected from each switch S to the lower reference resistor array 12, and the upper reference voltage is supplied. It is assumed that there is a problem that the AD conversion cannot be performed correctly due to fluctuation of the column 32.
[0008]
Next, FIG. 3 is a configuration circuit diagram of another example of the conventional series-parallel comparison type A / D converter disclosed in the publication. The A / D converter 44 in the illustrated example has been devised to solve the above-described problems. The A / D converter 42 in FIG. The upper reference resistor string 20 is a series connection of four resistors Rm in the figure, and the upper reference voltage string 32 equally divides the two reference voltages 26a and 26b by these four resistors Rm. Created.
[0009]
In this A / D converter 44, by reducing the resistance value of each resistor Rm constituting the higher-order reference resistor array 20 and increasing the flowing current, for example, unless a very large switch S is used, The influence due to the variation can be suppressed, and when each switch S in the switch array 18 becomes conductive, even if charges are injected from each switch S to the lower reference resistor array 12, the upper reference voltage array 32. And the fluctuation | variation of the voltage of the low-order reference voltage row | line 30 can be made small.
[0010]
On the other hand, according to the publication, since the upper reference resistor row 20 is provided, the wirings 34 and 36 in the vertical direction in the figure are required, and the left and right sides in the drawing for connecting the switch row 18 and the lower comparator row 14 Since the wiring 38 in the direction becomes longer by the thickness of the wirings 34 and 36, the load capacity of the wiring 38 increases, and when each switch S in the switch array 18 becomes conductive, the lower comparator array 14 There is a problem that the time until the input to the voltage equal to the lower reference voltage becomes longer and the conversion speed decreases.
[0011]
Next, FIG. 4 is a configuration circuit diagram of an example of the series-parallel comparison type A / D converter disclosed in the publication. The A / D converter 46 in the illustrated example has been proposed to solve the above-described problem. In the A / D converter 44 of FIG. 3, the upper reference resistor string 20 is replaced with two upper reference resistor strings 20a, The upper reference voltage string 32b and the analog signal 28 are compared among the upper reference voltage strings 32a and 32b created by the upper reference resistor strings 20a and 20b.
[0012]
According to this publication, in this A / D converter 46, the upper reference voltage string 32a is reduced by reducing the resistance value of each resistor Rm constituting the upper reference resistor string 20a, 20b and increasing the flowing current. 32b and the lower reference voltage string 30 can be reduced in variation, and the wiring 34 parallel to the lower reference resistor string 12 can be omitted as compared with the A / D converter 44 of FIG. The length of the wiring 38 is shortened by the amount of the wiring 34, and as a result, the time required for AD conversion is shortened.
[0013]
By the way, in the A / D converter 44 of FIG. 3, generally, polysilicon or a diffusion layer having a high resistance value is used as the resistors Rs and Rm, whereas the wirings 34 and 36 have low resistance. Value metal wiring is used. That is, since the resistor Rs and the wirings 34 and 36 have different layers in the manufacturing process, even if the wirings 34 and 36 parallel to the lower-order reference resistor array 12 exist, the wiring 38 has the thickness of the wirings 34 and 36. It does not become longer by the amount of time, and of course the conversion speed does not decrease.
[0014]
However, in the A / D converter 46 of FIG. 4, as described above, the purpose is to omit the wiring 34 that causes the speed reduction of the A / D converter 44 of FIG. The wiring corresponding to the wiring 34 of the D converter 44 is connected only to the upper reference resistor row 20a on the upper side in the figure, and not connected to the upper reference resistor row 20b on the lower side in the figure, The upper reference voltage string 32 b of the device string 20 b is used as the upper reference voltage string of the A / D converter 46.
[0015]
That is, a diagram of the upper reference resistor row 20a in which the upper reference voltage at the center in the drawing of the upper reference resistor row 20b that is not connected to the lower reference resistor row 12 is connected to the lower reference resistor row 12 is shown. As described above, the wiring 34 in the A / D converter 44 in FIG. 3 is omitted by using it as the same as the middle reference upper reference voltage, as described above, although it does not affect the conversion speed. As a result, the conversion speed is reduced.
[0016]
However, even if the resistors Rm are the same on the logical drawing, each resistor Rm actually manufactured has a variation in resistance value. Therefore, the upper reference voltage at the center of the upper reference resistor row 20b that is not connected to the lower reference resistor row 12 is used as being equal to the voltage at the center of the lower reference resistor row 12 in the drawing. However, in reality, the resistance varies depending on the variation of the resistance value of each resistor Rm, and there is a problem that the conversion accuracy may be remarkably lowered.
[0017]
[Problems to be solved by the invention]
An object of the present invention is to provide an A / D converter capable of converting an analog signal into a digital signal at high speed and with high accuracy in view of the problems based on the prior art.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a first and a second circuit, each of which is configured by connecting a predetermined number of resistors in series according to the number of upper bits of a digital signal obtained by converting an analog signal. 2 upper reference resistor arrays, each of which is configured by connecting a predetermined number of resistors corresponding to the number of lower bits of the digital signal in series, thereby forming the first and second upper reference resistor arrays A series-parallel comparison type A / D converter having a predetermined number of low-order reference resistor arrays corresponding to each of the resistors ,
The first and second upper reference resistor strings are each connected between a first reference voltage and a second reference voltage, and each of the resistors of the first upper reference resistor string Both ends and both ends of the corresponding resistors in the second upper reference resistor row are connected to each other,
Each of the predetermined number of the lower reference resistor arrays is nth (n is 1 ≦ n ≦ the first and second) counted from the first reference voltage side of the first upper reference resistor array. (The odd number satisfying the number of resistors constituting the upper reference resistor string) and the first reference voltage side terminal of the second upper reference resistor string and the first reference voltage side of the second upper reference resistor string And the second reference voltage side terminal of the nth resistor, and the mth (m is 2 from the first reference voltage side of the first upper reference resistor row). ≦ m ≦ even number satisfying the number of resistors constituting the first and second higher-order reference resistor rows) and the second higher-order reference resistor row a characterized in that it is inserted between the reference voltage side of the terminal a first of the m-th counted from the reference voltage side resistor first of / It is to provide a converter.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an A / D converter of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
The A / D converter of the present invention has the same components as the conventional A / D converter 46 shown in FIG. 4, for example. Basically, the lower reference resistor string, the lower comparator string, the lower logic A circuit, a switch row, first and second upper reference resistor rows, an upper comparator row, an upper logic circuit, and the like.
[0020]
Here, FIG. 1 shows a partial configuration circuit diagram of an embodiment of the A / D converter of the present invention. The A / D converter 10 in the illustrated example shows an example of the connection relationship between the upper reference resistor string and the lower reference resistor string, which is a characteristic part of the present invention. In the illustrated example, the lower reference resistor string is illustrated. 12, upper reference resistor rows 20a and 20b and upper comparator row 22 are provided. In the illustrated A / D converter 10, the same components as those of the conventional A / D converter 46 shown in FIG.
[0021]
Each of the upper reference resistor rows 20a and 20b is obtained by connecting four resistors Rm in the figure in series, and similarly, the lower reference resistor row 12 is obtained by connecting four resistors Rs in the drawing in series. is there. Further, four lower reference resistor rows 12 in the figure are connected in series corresponding to each resistor Rm constituting the upper reference resistor rows 20a and 20b, and each of the upper reference resistor rows 20a and 20b. Both ends of each resistor Rm and the corresponding ends of each lower reference resistor row 12 are connected to each other by a wiring 40.
[0022]
The upper reference voltage string 32 is created by equally dividing the two reference voltages 26a and 26b by the four resistors Rm constituting the two upper reference resistor strings 20a and 20b. . Similarly, although the lower reference voltage train is not shown, two adjacent upper reference voltages in the upper reference voltage train 32 are evenly distributed by the four resistors Rs constituting each lower reference resistor train 12. It is created by dividing resistance.
[0023]
In the A / D converter 10, first, the higher-order comparator string 22 compares the input analog signal 28 and the higher-order reference voltage string 32 at the same time, and then the higher-order logic circuit (not shown) It is determined which two upper reference voltages adjacent to each other in the upper reference voltage train 32 fall between 28. That is, upper bits of the digital signal corresponding to the analog signal 28 converted by the A / D converter 10 are created.
[0024]
Subsequently, the switch row 18 of the lower reference resistor row 12 corresponding to the upper comparison result is turned on, and the analog signal 28 and the lower reference voltage row are simultaneously compared by the lower comparator row not shown. Thereafter, a lower logic circuit (not shown) determines which of the two adjacent lower reference voltages in the lower reference voltage train the analog signal 28 falls between. That is, the lower bits of the digital signal corresponding to the analog signal 28 are created.
[0025]
In order to suppress the voltage fluctuation amount of the upper reference voltage string 32 and the lower reference voltage string 30 described above to the same level as that of the conventional A / D converter 44 shown in FIG. If each of the resistors Rs to be configured has the same resistance value, the resistance value of each of the upper reference resistor rows 20a and 20b is set to the resistance value of the upper reference resistor row 20 of the A / D converter 44 of FIG. And the amount of current flowing through each of the upper reference resistor arrays 20a and 20b may be halved.
[0026]
That is, in the A / D converter of the present invention, in order to halve the amount of current flowing through the upper reference resistor rows 20a and 20b, for example, each resistor Rm that constitutes the upper reference resistor rows 20a and 20b. Since the width of the upper reference resistor rows 20a and 20b only needs to be halved, for example, the area of the upper reference resistor row 20 of the A / D converter 44 of FIG. The power consumption is substantially the same as the power consumption of the A / D converter 44 of FIG.
[0027]
Further, the A / D converter of the present invention divides the upper reference resistor string into two upper reference resistor strings 20a and 20b. For example, as shown in FIG. Further, both ends of the resistors Rm of the upper reference resistor rows 20a and 20b are connected to both ends of the lower reference resistor rows 12 corresponding thereto, so that, for example, as shown in FIG. Compared with the conventional A / D converter 46, there is an advantage that the balance is very good and the conversion accuracy is extremely high.
[0028]
In the A / D converter of the present invention, for example, high-resistance polysilicon or diffusion layers are used as the resistors Rs and Rm, and low-resistance metal wiring is used as the wiring 40. Therefore, as described above, since the resistor Rs and the wiring 40 are different in the manufacturing process, just because there is the wiring 40 in parallel with the lower reference resistor array 12, the switch array and the lower comparator array Of course, the wiring for connecting the terminals does not have to be long, so that the conversion speed does not decrease.
[0029]
Although the A / D converter of the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and various improvements and modifications may be made without departing from the spirit of the present invention. It is.
For example, in the A / D converter of the present invention, circuit configurations of a lower comparator string, a lower logic circuit, a switch string, an upper comparator string, and an upper logic circuit other than the lower reference resistor string and the upper reference resistor string Is not limited at all.
[0030]
【The invention's effect】
As described above in detail, the A / D converter of the present invention connects a predetermined number of lower reference resistor strings corresponding to each resistor constituting the first and second upper reference resistor strings in series. , Both ends of each of the resistors constituting the first and second upper reference resistor rows and the lower ends of the corresponding lower reference resistor rows are connected to each other. Analog signals can be converted to digital signals with high accuracy.
[Brief description of the drawings]
FIG. 1 is a partial configuration circuit diagram of an embodiment of an A / D converter of the present invention.
FIG. 2 is a configuration circuit diagram of an example of a conventional A / D converter.
FIG. 3 is a configuration circuit diagram of another example of a conventional A / D converter.
FIG. 4 is a configuration circuit diagram of still another example of a conventional A / D converter.
[Explanation of symbols]
10, 42, 44, 46 A / D converter 12 Lower reference resistor string 14 Lower comparator string 16 Lower logic circuit 18 Switch string 20, 20a, 20b Upper reference resistor string 22 Upper comparator string 24 Upper logic circuit 26a, 26b Reference voltage 28 Analog signal 30 Lower reference voltage string 32, 32a, 32b Upper reference voltage string 34, 36, 38, 40 Wiring Rs, Rm Resistor S switch

Claims (1)

First and second upper reference resistor arrays each of which is configured by connecting a predetermined number of resistors in series according to the number of upper bits of a digital signal obtained by converting an analog signal, , said predetermined number of resistors corresponding to the number of low-order bits of the digital signal is constructed by serially connecting, lower predetermined number corresponding to each of the resistors constituting the first and second upper reference resistor string A series-parallel comparison type A / D converter having a reference resistor array,
The first and second upper reference resistor strings are each connected between a first reference voltage and a second reference voltage, and each of the resistors of the first upper reference resistor string Both ends and both ends of the corresponding resistors in the second upper reference resistor row are connected to each other,
Each of the predetermined number of the lower reference resistor arrays is nth (n is 1 ≦ n ≦ the first and second) counted from the first reference voltage side of the first upper reference resistor array. (The odd number satisfying the number of resistors constituting the upper reference resistor string) and the first reference voltage side terminal of the second upper reference resistor string and the first reference voltage side of the second upper reference resistor string. And the second reference voltage side terminal of the nth resistor, and the mth (m is 2 from the first reference voltage side of the first upper reference resistor row). ≦ m ≦ even number satisfying the number of resistors constituting the first and second higher-order reference resistor rows) and the second higher-order reference resistor row a characterized in that it is inserted between the reference voltage side of the terminal a first of the m-th counted from the reference voltage side resistor first of / Converter.

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