JP3786575B2 - Data processing device - Google Patents

Description

本記述は、ＩＥＥＥ１３６４として標準化されているＨＤＬ記述言語に従っている。かかるＨＤＬ記述言語自体については、１９９６年７月ＣＱ出版株式会社発行の『入門Ｖｅｒｉｌｏｇ−ＨＤＬ記述』などに記載されている。
【００９５】
ｃａｓｅｘ及びｃａｓｅは、それに続く（）内の変数（ｏｐｃｏｄｅ、ｔｍｇ）に応じて、後続の値（１６’ｂ０１０１０１００＿０００１？？？？：、４’ｂ０００１：など）に一致した動作を実行する。ｂｅｇｉｎ〜ｅｎｄで１つの動作が記述される。
【００９６】
（１）で、命令デコーダの入力（ｏｐｃｏｄｅ）による条件を指示する。当該条件で、（２）〜（１２）でＲＴＳ／２に相当する命令コードの動作が記述される。更に、各命令コード毎に、ステップに相当する命令デコーダの入力（ｔｍｇ）による条件を指示する。ＲＴＳ／２の第１ステップの動作は、（４）〜（７）に記述される。（５）で、次のステップ（ｎｅｘｔｔｍｇ）が第４ステップであることが指定される。ｎｅｘｔｔｍｇは１ステート後に、ｔｍｇとして命令デコーダに入力される。（６）で、バスコマンドがロングワードリードとされる。ｌｏｎｇ＿ｒｅａｄはパラメータとして、所定のコードが割当てられるようにしておく。この後に、そのほかの制御信号が記述される。同様に、第４ステップの動作は、（８）〜（１１）に記述される。第５〜第８ステップの動作は、これ以降（１２）までに記述される。
【００９７】
同様に、命令デコーダの入力（ｏｐｃｏｄｅ）による条件で、（１３）以降でＲＴＳ／３に相当する命令コードの動作が記述される。第１ステップの動作記述において、（１５）で、次のステップ（ｎｅｘｔｔｍｇ）が第２ステップであることが指定される。また、第２ステップの動作は、（１７）以降に記述される。更に、第４〜第８ステップの動作も記述される。
【００９８】
更に、その後、ＲＴＳ／４に相当する命令コードの動作が記述され、第２の復帰命令（ＲＴＥ／ｎ）、複数レジスタの退避命令（ＳＴＭ）や、その他の命令コードも記述される。
【００９９】
図８に、第１の復帰命令（ＲＴＳ／ｎ）の実行タイミングを示す。
【０１００】
ｎ＝２の場合の例である。
【０１０１】
特に制限はされないものの、内蔵ＲＯＭ、ＲＡＭのリード／ライトを１ステートでリード／ライト可能とし、内蔵ＲＯＭ上にプログラム、内蔵ＲＡＭ上にスタックを配置した場合のタイミングを示す。
【０１０２】
Ｔ０のφ＃（＃は反転論理を示す）で、ＣＰＵのアドレスバッファ（ＭＡＢ）かアドレスがＩＡＢに出力される。また、命令デコーダから、命令フェッチ（ｉｆ）を示す、バスコマンド（ＢＣＭＤ）が出力される。
【０１０３】
Ｔ１のφで、ＩＡＢの内容がＰＡＢに出力され、バスコマンドに基づき、リードサイクルが開始され、ＰＤＢにデータが出力される。φ＃でＰＤＢのリードデータが内部データバスＩＤＢに得られ、これをＴ２のφでＩＲにラッチする。以上の動作は以前の命令の実行の制御によって行われる（プリフェッチ）。ここで、内蔵ＲＯＭ、ＲＡＭは、ＰＡＢ及びＰＤＢに接続されていないが、ＰＡＢ、ＰＤＢ相当の動作をモジュール内で行い、本タイミング図には、このモジュール内の動作を示している。
【０１０４】
直前の命令の実行が終了すると、最も早く命令の実行が開始される場合には、Ｔ２のφで命令コードがＤＥＣに入力されて、命令の内容が解読される。解読結果に従って、制御信号を出力して、各部の制御を行う。命令の一部（レジスタ指定フィード：ｒ）がレジスタセレクトに与えられる。
【０１０５】
前記のステップ１として、Ｔ２のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。
【０１０６】
Ｔ３のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ３のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ４のφで、ＤＢＲに格納される。
【０１０７】
ステップ４として、Ｔ４のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ３のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ４のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ４のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ５のφで、ＤＢＲに格納される。
【０１０８】
ステップ５として、Ｔ５のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ４のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ５のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ５のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ６のφで、ＤＢＲに格納される。
【０１０９】
ステップ６として、Ｔ６のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、ＰＣに書込まれる。
【０１１０】
ステップ７として、Ｔ６のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ７のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。
【０１１１】
ステップ８として、Ｔ７のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ８のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。Ｔ８のφでリードした命令コードが、ＩＲを経由して、ＤＥＣに入力されて、次の命令が実行される。
【０１１２】
図９に、第２の復帰命令（ＲＴＥ／ｎ）の動作フローを示す。
【０１１３】
第１の復帰命令（ＲＴＳ／ｎ）に対して、ステップ６で、ＰＣとともに、ＣＣＲへの書込みが行われるようにされる。そのほかの動作は同様にできる。
【０１１４】
図１０に、第２の復帰命令（ＲＴＥ／ｎ）の実行タイミングを示す。
【０１１５】
ｎ＝４の場合の例である。
【０１１６】
前記同様に、Ｔ２のφで命令コードがＤＥＣに入力されて、命令の内容が解読される。解読結果に従って、制御信号を出力して、各部の制御を行う。命令の一部（レジスタ指定フィード：ｒ）がレジスタセレクトに与えられる。
【０１１７】
前記のステップ１として、Ｔ２のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。
【０１１８】
Ｔ３のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ３のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ４のφで、ＤＢＲに格納される。
【０１１９】
ステップ２として、Ｔ４のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ３のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ４のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ４のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ５のφで、ＤＢＲに格納される。
【０１２０】
ステップ３として、Ｔ５のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ４のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ５のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ５のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ６のφで、ＤＢＲに格納される。
【０１２１】
ステップ４として、Ｔ６のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ５のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ６のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ６のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ７のφで、ＤＢＲに格納される。
【０１２２】
ステップ５として、Ｔ７のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、指定（ｒ）した汎用レジスタに書込まれる。レジスタ指定フィールドがデクリメントされる。前記同様に、Ｔ６のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのリードのバスコマンドが出力される。Ｔ７のφで、ＩＮＣでインクリメント（＋４）された結果が、内部バスＷＢを経由してＳＰにライトされる。Ｔ７のφ＃から、スタックからリードしたデータがＩＤＢに出力され、Ｔ６のφで、ＤＢＲに格納される。
【０１２３】
ステップ６として、Ｔ６のφ及びφ＃で、ＤＢＲの内容が内部バスＧＢ、ＡＬＵ、内部バスＷＢを介して、ＣＣＲとＰＣに書込まれる。ＤＢＲのビット３１〜２４がＣＣＲに、ビット２３〜０がＰＣに書込まれる。
【０１２４】
ステップ７として、Ｔ８のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ９のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。
【０１２５】
ステップ８として、Ｔ９のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ１０のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。Ｔ１０のφでリードした命令コードが、ＩＲを経由して、ＤＥＣに入力されて、次の命令が実行される。
【０１２６】
図１１に、複数汎用レジスタの退避命令（ＳＴＭ）の動作フローを示す。
【０１２７】
ステップ０は、命令コードの第１ワードで制御される。制御信号Ａで、プログラムカウンタ（ＰＣ）の内容のアドレスバス（ＩＡＢ）への出力と、メモリワードリードが指示され、ＰＣの内容のインクリメント（＋２）が指示される。制御信号Ｂで、命令コードの第２ワードの命令デコーダへの入力と、第１ワードで指定される汎用レジスタ本数の情報（ＭＯＤ）が指示される。
【０１２８】
ステップ１で、制御信号Ａで、スタックポインタ（ＳＰ）の内容のデクリメント（−４）が指示される。ステップ２〜５で、制御信号Ａで、スタックポインタ（ＳＰ）の内容のアドレスバス（ＩＡＢ）への出力と、ロングワードのライトが指示される。制御信号Ｂで、汎用レジスタの内容のＤＢＷへの格納が指示される。制御信号Ｃで、ＤＢＷの内容のＩＤＢへの出力が指示される。レジスタセレクタＲＥＳＬに対してレジスタフィールドのインクリメント（−１）が指示される。ステップ２〜４は、ＳＰの内容のデクリメント（−４）が指示される。ステップ２〜５は、指定した汎用レジスタの本数（ｎ）に従って、所定回数が実行される。
【０１２９】
ステップ６で、制御信号Ａで、プログラムカウンタ（ＰＣ）の内容のアドレスバス（ＩＡＢ）への出力と、メモリワードリードが指示され、ＰＣの内容のインクリメント（＋２）が指示される。制御信号Ｂで、前のステップでリードした命令（ＩＲ）の命令デコーダへの入力が指示される。次の命令の実行が開始される。
【０１３０】
ステップ２〜５において、汎用レジスタの内容を、ＤＢＷに転送後、当該汎用レジスタの内容を０にクリアするようにするとよい。汎用レジスタを退避した後、０にクリアし、その内容を確定することで、その後の処理を簡略化することができる。
【０１３１】
例えば、その後、汎用レジスタに０を代入する場合、ＭＯＶ命令を省略できる。また、１などを代入する場合は、
ＭＯＶ．Ｌ ＃１，ＥＲｎ
を使用する代わりに、
ＭＯＶ．Ｂ ＃１，ＲｎＬ
を使用することができる。イミディエイトデータは、そのデータサイズに対応した領域を命令コードに持つから、ＭＯＶ．Ｌの命令コード長（例えば３ワード）よりも、ＭＯＶ．Ｂの命令コード長（例えば１ワード）の方が短い。これによって、プログラム容量の短縮に寄与できる。
【０１３２】
なお、プログラム中に使用する定数値は、０や１などの比較的小さい値が多いことが一般的である。
【０１３３】
図１２に、複数汎用レジスタの退避命令（ＳＴＭ）の実行タイミングを示す。
【０１３４】
ｎ＝２の場合の例である。
【０１３５】
Ｔ２のφで命令コードの第１ワード（ｓｔｍ−１）がＤＥＣに入力されて、命令の内容が解読される。解読結果に従って、制御信号を出力して、各部の制御を行う。命令の一部（レジスタ指定フィード：ｒ）がレジスタセレクトに与えられる。
【０１３６】
ステップ０として、Ｔ２のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ２のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。Ｔ３のφでリードした命令コードが、ＩＲを経由して、ＤＥＣに入力されて、次の命令が実行される。
【０１３７】
Ｔ３のφで命令コードの第２ワード（ｓｔｍ−２）がＤＥＣに入力されて、命令の内容が解読される。解読結果に従って、制御信号を出力して、各部の制御を行う。命令の一部（レジスタ指定フィード：ｒ）がレジスタセレクトに与えられる。
【０１３８】
前記のステップ１として、Ｔ３のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＩＮＣに入力する。Ｔ３のφで、ＩＮＣでデクリメント（−４）された結果が、内部バスＷＢを経由してＳＰにライトされる。
【０１３９】
ステップ２として、Ｔ４のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。ロングワードのライトのバスコマンドが出力される。Ｔ５のφで、ＩＮＣでデクリメント（−４）された結果が、内部バスＷＢを経由してＳＰにライトされる。また、指定（ｒ）した汎用レジスタの内容が内部バスＤＢを介してＤＢＷに書込まれる。レジスタ指定フィールドがインクリメントされる。Ｔ５のφ＃から、ＤＢＷの内容がＩＤＢに出力される。
【０１４０】
ステップ５として、Ｔ５のφ＃で、ＳＰの内容を内部バスＧＢに読み出して、ＡＢを介してアドレスＩＡＢが出力される。ロングワードのライトのバスコマンドが出力される。Ｔ５のφで、指定（ｒ）した汎用レジスタの内容が内部バスＤＢを介してＤＢＷに書込まれる。レジスタ指定フィールドがインクリメントされる。Ｔ５のφ＃から、ＤＢＷの内容がＩＤＢに出力される。
【０１４１】
ステップ６として、Ｔ６のφ＃で、ＰＣの内容を内部バスＧＢに読み出して、ＡＢとＩＮＣに入力する。ＡＢからアドレスＩＡＢが出力される。Ｔ７のφで、ＩＮＣでインクリメント（＋２）された結果が、内部バスＷＢを経由してＰＣにライトされる。プリフェッチした命令コード（ｎｅｘｔ）が、ＩＲを経由して、ＤＥＣに入力されて、次の命令が実行される。
【０１４２】
前記の通り、ステップ２〜５において、Ｔ５、Ｔ６のφ＃で、汎用レジスタの内容を０にクリアする。これは、当該タイミングの内部バスＷＢを０とし、これを汎用レジスタに書込むようにするとよい。
【０１４３】
図１３に、本発明のＣＰＵの開発環境の概略を示す。
【０１４４】
使用者は、各種エディタなどを用いて、Ｃ言語乃至アセンブリ言語でプログラムを作成する。これは通常、複数のモジュールに分割して作成される。
【０１４５】
Ｃコンパイラは、使用者の作成したそれぞれのＣ言語ソースプログラムを入力し、アセンブリ言語ソースプログラム乃至オブジェクトモジュールを出力する。
【０１４６】
例えば、Ｃ言語でプログラムを作成する場合、

と記述された関数ｓｅｑ０は、本発明のＣＰＵに対しては、以下のようにコンパイルされる。
【０１４７】

関数内で使用する汎用レジスタＥＲ３、ＥＲ４をＳＴＭ命令でスタックに退避し、０にクリアされる。復帰命令時にスタックから回復される。
【０１４８】
また、メインプログラムで上記関数ｓｅｑ０を呼び出す場合は、
ｓｅｑ０（）；
と記述され、
ＪＳＲ ＠＿ｓｅｑ０
とサブルーチン分岐命令にコンパイルされる。
【０１４９】
アセンブラは、アセンブリ言語ソースプログラムを入力し、オブジェクトモジュールを出力する。
【０１５０】
リンケージエディタは、上記Ｃコンパイラやアセンブラの生成した、複数のオブジェクトモジュールを入力して、各モジュールの外部参照や相対アドレスなどの解決を行い、１つのプログラムに結合して、ロードモジュールを出力する。
【０１５１】
ロードモジュールは、シミュレータ／デバッガに入力して、パーソナルコンピュータなどのシステム開発装置上で、ＣＰＵの動作をシミュレーションし、実行結果を表示し、プログラムの解析や評価を行うことができる。また、エミュレータに入力して、実際の応用システム上などで動作する、いわゆるインサーキットエミュレーションを行ない、マイクロコンピュータ全体としての、実動作の解析や評価を行うことができる。
【０１５２】
更に、ロードモジュールをＰＲＯＭライタなどのＲＯＭ書込み装置に入力して、マイクロコンピュータの内蔵ＲＯＭがフラッシュメモリなどの場合や、外部のフラッシュメモリなどに、作成したプログラムをロードすることができる。或いはマイクロコンピュータの製造工程で、内蔵ＲＯＭに書込むことも可能である。必要に応じて、オブジェクトコンバータなどによって、所望のフォーマットに変換する。
【０１５３】
このほかに、ライブラリアンとして、汎用的なサブルーチンなどを提供することもできる。
【０１５４】
ＣＰＵ定義情報ファイルは、コンパイル対象のＣＰＵを指定し、本発明の復帰命令を持たない（既存の）ＣＰＵと、本発明のＣＰＵとを共通の開発環境を利用可能にする。
【０１５５】
例えば、ＣＰＵ定義情報ファイルに、
ＳＥＴ ＣＰＵ＝ ＣＰＵ１；
と記述することによって、本発明のＣＰＵを選択するようにする。
【０１５６】
コンパイル時に、かかるＣＰＵ定義情報ファイルを参照し、本発明の復帰命令を持たないＣＰＵが選択されていれば、前記関数は、

となる。ＭＯＶ．Ｌは、当該関数の処理内容に従って、変更になる場合もある。
【０１５７】
Ｃコンパイラ自体には、Ｃ言語によるプログラムを、ＣＰＵの命令に変換する機能のほか、Ｃ＋＋言語によるプログラムのコンパイルや、モジュール間最適化などといった、ＣＰＵの命令セットとは直接関係のない機能の向上が図られているが、ＣＰＵ毎の個別のコンパイラでは、これらの機能向上を全ての個別のコンパイラに適用しなければならない。本発明のように、共通のＣコンパイラとしておけば、前記、ＣＰＵの命令セットとは直接関係のない機能向上を図ることが容易になり、また、開発効率などを向上することができる。
【０１５８】
上記実施例によれば、以下の作用効果を得るものである。
【０１５９】
単一の命令で、複数の汎用レジスタと復帰動作と、サブルーチンまたは例外処理ルーチンからの復帰動作を行うことによって、相対的に、命令コード長を短縮（例えば、２ワード短縮）し、命令のリード回数を低減して、高速化することができる。
【０１６０】
例えば、Ｃ言語などで多用される関数はサブルーチンとされるから、この数に対応する数のサブルーチンからの復帰命令が使用されることになる。関数毎に必要なデータが汎用レジスタに割当てられるから、それ以前の汎用レジスタの内容の退避／復帰を伴う。従って、かかる復帰命令による命令コード長の短縮効果も大きくなる。
【０１６１】
また、関数毎に、退避／復帰する汎用レジスタ本数も異なるから、レジスタの本数の異なる命令を複数命令サポートすることによって、或いは、汎用レジスタの復帰を伴わない復帰命令もサポートして、プログラムの作成を容易にし、使い勝手を向上することができる。
【０１６２】
ＣＰＵの有する汎用レジスタ本数が多い場合にも、復帰する汎用レジスタを指定可能にしているから、汎用レジスタの使用方法の自由度を損なうことが少ない。また、不所望の汎用レジスタの退避／復帰を行ったりするこがない。
【０１６３】
複数の汎用レジスタを指定する固定の組合わせにすることによって、命令コード長を短縮でき、更に、各命令の実行ステート数を固定にすることにより、内部の条件分岐を行うことを少なくし（命令デコーダの入力ｏｐｃｏｄｅに応じて、デコーダを記述すればよい）、内部論理を簡潔にし、論理規模を縮小できる。マイクロプログラムによらず、ワイアードロジックなどでも容易に実現できる。マイクロプログラムによらず、ワイアードロジックなどとすることにより、論理回路の高速化に寄与することができる。レジスタセレクタにインクリメンタを持つことによって、論理的規模の増加を最小限にして、連続した任意の組合せを指定可能にできる。
【０１６４】
同様の指定を可能にした、汎用レジスタの退避命令（ＳＴＭ）を持ち、これをサブルーチン乃至例外処理ルーチンの先頭で実行し、最後に、本発明の復帰命令を実行することによって、より一層の使い勝手を向上できる。汎用レジスタの退避命令実行時に、退避後に汎用レジスタをクリアすることにより、更に、命令コード長を短縮し、実行ステート数を短縮できる。
【０１６５】
また、データのリード／ライトを連続して行うことによって、メモリに対するバースト動作などやバス幅を拡張する場合にも、これらを有効に利用しやすい。
【０１６６】
ソースプログラムレベルまたはオブジェクトプログラムレベルで、既存のＣＰＵの命令セットを包含した上で、上記命令を追加することによって、ソフトウェア資産を有効に利用することができ、使用者のソフトウェア開発効率を向上することができる。ソースプログラムレベルまたはオブジェクトプログラムレベルで互換性を保つことによる利点と前記転送命令を追加することの利点の双方を享受することができる。
【０１６７】
以上本発明者等によってなされた発明を実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能である。
【０１６８】
命令コードは一例であり、種々変更が可能である。既存の命令セットに追加するほか、新規の命令セットを開発する場合に適用することが可能であることは言うまでもない。
【０１６９】
例外処理におけるスタックの構造は、ＣＣＲとＰＣを組合せて３２ビットとしたが、これらは、１６ビットと３２ビットに分割したり、そのほかのコントロールレジスタを追加したりすることもできる。ＰＣも３２ビットとしてもよい。
【０１７０】
汎用レジスタの構成や本数など、或いは復帰命令で復帰する汎用レジスタの本数などは任意に変更できる。復帰する汎用レジスタの本数は１本でもよい。スタックに格納される順序なども任意に変更できる。汎用レジスタを復帰する場合、ＰＣ（及びＣＣＲ）と連続してリードする方が都合がよい。
【０１７１】
インクリメンタ（ＲＩＮＣ）も、インクリメント／デクリメントを行うほか、命令デコーダの出力との加算／減算を行うようにしてもよい。本発明の復帰命令の場合、命令コードのレジスタ指定フィールドに対して、１／２／３を順次減算するようにしてもよい。命令コード中に含まれるレジスタ指定フィールドも、最初に指定する汎用レジスタに対応している必要は必ずしもない。前記加算／減算と組合せて、所望の汎用レジスタを指定できればよい。
【０１７２】
復帰する汎用レジスタとして、スタックポインタであるＥＲ７が指定された場合は、ＥＲ７への書込みを禁止するとよい。スタックポインタの退避／復帰は意味がなく、所定のポイント動作を行えばよいからである。
【０１７３】
汎用レジスタの退避命令実行時に、退避後に汎用レジスタをクリアする命令と、保持する命令の両方を持ってもよい。当該命令コードの第１ワードの所定のビットでこれを指定して、制御信号（ＭＯＤ）を発生して、第２ワードの動作を変更するようにすればよい。
【０１７４】
汎用レジスタのクリアの内容は０に限定されず、他の値にしてもよい。クリアする内容を指定する手段を別に設けてもよい。
【０１７５】
命令の基本単位も１６ビットに限定されない。８ビット単位、３２ビット単位でも、本発明の復帰命令は適用可能である。
【０１７６】
簡単のために、バス幅を３２ビットとし、命令リードを１６ビット単位としたが、命令リードを３２ビット単位にして高速化することができる。このような例は、特願平１１−１６７８１２に記載されている。また、バス幅を１６ビットとして、ロングワードのリード／ライトを、ワード単位の２回のリード／ライトで実行するようにしてもよい。このような例は、特願平１１−３２０５１８に記載されている。
【０１７７】
マイクロコンピュータのその他の機能ブロックについても何等制約されない。
【０１７８】
以上の説明では主として本発明者によってなされた発明をその背景となった利用分野であるマイクロコンピュータに適用した場合について説明したが、それに限定されるものではなく、その他のデータ処理装置にも適用可能であり、本発明は少なくとも、複数のレジスタ手段を有するデータ処理装置に適用することができる。
【０１７９】
【発明の効果】
本題において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記の通りである。
【０１８０】
サブルーチンから、または例外処理からの復帰命令において、当該命令コードに複数の汎用レジスタを指定する情報を含み、当該命令コードの実行時に、プログラムカウンタの復帰に加えて、前記指定した汎用レジスタの復帰を行うようにすることにより、使い勝手を向上し、プログラム容量と実行ステート数を短縮できる。
【０１８１】
更に、指定する汎用レジスタの組合せを連続したものにすることにより、命令コード長を短縮でき、更に、各命令の実行ステート数を固定にすることにより、内部の条件分岐を行うことを少なくし、内部論理を簡潔にし、論理規模を縮小できる。１６ビット単位の可変長の命令コード体系を採る場合にも、命令プリフェッチや命令デコードを簡易にしつつ、命令コードを有効に利用して、全体的なプログラム効率を向上できる。
【０１８２】
同様の指定を可能にした、汎用レジスタの退避命令を持ち、これをサブルーチン乃至例外処理ルーチンの先頭で実行し、最後に、本発明の復帰命令を実行することによって、より一層の使い勝手を向上できる。
【０１８３】
汎用レジスタの復帰と、プログラムカウンタなどの復帰を連続的に行うことによって、内部の動作を容易にし、高速化できる。
【０１８４】
レジスタの本数の異なる復帰命令を複数サポートすることによって、また、連続した汎用レジスタの指定を可能にして、更に、プログラムの作成を容易にし、使い勝手を向上することができる。
【図面の簡単な説明】
【図１】本発明の適用されたマイクロコンピュータのブロック図。
【図２】ＣＰＵに内蔵されている汎用レジスタ及び制御レジスタの構成例の図。
【図３】ＣＰＵの構成例の図。
【図４】レジスタセレクタＲＥＳＬの一部の詳細ブロック図。
【図５】複数汎用レジスタの復帰を含む第１の復帰命令（ＲＴＳ／ｎ）、第２の復帰命令（ＲＴＥ／ｎ）の命令フォーマット図。
【図６】複数汎用レジスタの復帰を含む第１の復帰命令（ＲＴＳ／ｎ）、第２の復帰命令（ＲＴＥ／ｎ）のスタックの構成例の図。
【図７】第１の復帰命令（ＲＴＳ／ｎ）の動作フローの図。
【図８】第１の復帰命令（ＲＴＳ／ｎ）の実行タイミングの図。
【図９】第２の復帰命令（ＲＴＥ／ｎ）の動作フローの図。
【図１０】第２の復帰命令（ＲＴＥ／ｎ）の実行タイミングの図。
【図１１】複数汎用レジスタの退避命令（ＳＴＭ）の動作フローの図。
【図１２】複数汎用レジスタの退避命令（ＳＴＭ）の実行タイミングの図。
【図１３】本発明のＣＰＵの開発環境の概略図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus, and more particularly to a microcomputer constituted by a semiconductor integrated circuit device. It is related to effective technology.
[0002]
[Prior art]
With the advancement of manufacturing technology of semiconductor integrated circuit devices, a central processing unit (hereinafter simply referred to as CPU), a ROM (Read Only Memory) for storing a program on a single chip made of a semiconductor single crystal, Microcomputers manufactured by integrating components including RAM (Random Access Memory) that stores various data in a rewritable manner have been widely used, and have been used as data processing apparatuses for various purposes. . The performance of this microcomputer varies depending on the amount of information that can be processed simultaneously by the CPU, and is classified as, for example, a microcomputer of 4 bits, 8 bits, 16 bits, 32 bits, or the like.
[0003]
Such microcomputers have been expanded in address space, instruction set, and speed. In addition, since the performance of the CPU is defined by software, even in a microcomputer that has expanded the address space, expanded the instruction set, and increased the speed as described above, the software assets of the existing microcomputer are reduced. It is desirable that it can be used effectively.
[0004]
For this reason, as an example of realizing address space expansion, instruction set expansion, high speed, etc. while maintaining compatibility at the object level, there is, for example, JP-A-6-51981 previously proposed by the present inventor. . This is a variable-length instruction in 16-bit units, and it is shown that a so-called general-purpose register type or load / store type architecture is adopted.
[0005]
In the case of a single-chip type having a built-in ROM as a program memory, the capacity of the built-in ROM is small compared to connecting an external memory, so it is desirable to reduce the program capacity. .
[0006]
When a variable length instruction in 16-bit units is adopted, there is a return (RTS / RTE) instruction that has only an operation code, does not specify an effective address, and is meaningful. When such a return instruction is assigned to a 16-bit instruction, all the bits of the 16-bit instruction code are often not used.
[0007]
For example, if the instruction code H′5470 is a return instruction from a subroutine and H′5471, H′5472 and H′5473 are undefined (not defined as other instructions), the bit 0 and bit 1 are not used.
[0008]
On the other hand, the CPU described in Japanese Patent Application Laid-Open No. 8-263290 previously proposed by the present inventors fixes a combination of a plurality of general-purpose registers that can be designated as control means for controlling execution means for executing instructions. The general-purpose register stack has a save / return instruction, and a plurality of general-purpose registers are sequentially saved / restored. By fixing the combination of general-purpose registers, the number of bits required to specify the general-purpose registers can be saved.
[0009]
Such a save / return instruction is used for the purpose of saving the state of the previous process at the break of processing such as a subroutine or exception processing, and the addressing mode is pre-decrement / retraction of the stack pointer ) Can be used.
[0010]
That is, such a general register return instruction is often placed before a return instruction (RTS / RTE) from the subroutine or exception processing.
[0011]
In a CPU of a so-called accumulator type architecture, there is a case where the accumulator is saved / restored in addition to the PC when branching to the subroutine / returning from the subroutine. This is because data processing is performed on a small number of accumulators, and when the processing changes like a subroutine, it is necessary to free up the accumulator. In other words, it is not wasted even if the accumulator is automatically retracted / returned.
[0012]
In contrast, general-purpose register architecture CPUs have a high degree of freedom in which data is placed in general-purpose registers, and arguments for branching / returning from subroutines are assigned to general-purpose registers. Sometimes. For this reason, automatically saving / restoring predetermined (all or a part) of general-purpose registers tends to be useless. This is because the number of execution states and the usage amount of the stack increase due to undesired saving / restoring of general-purpose registers.
[0013]
Microcomputer programs are often written in C language. Functions often used in the C language are realized as subroutines.
[0014]
[Problems to be solved by the invention]
The problems to be solved by the present invention are as follows:
It is an object of the present invention to provide a data processing apparatus such as a microcomputer and a means for improving usability, reducing the program capacity, and reducing the number of execution states while minimizing an increase in the logical scale.
[0015]
In particular, in a program using C language or the like, it is intended to reduce the program capacity and the number of execution states when many functions are used.
[0016]
In addition, the existing software assets can be used effectively to improve the development efficiency of users, the development equipment can be used in common, the development efficiency of the development equipment can be improved, and the development environment can be provided quickly. It is to be.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.
[0018]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0019]
The data processing apparatus of the present invention includes information specifying a plurality of general-purpose registers in the instruction code in a return instruction from a subroutine or exception processing, and in addition to the return of the program counter when the instruction code is executed, The designated general-purpose register is restored.
[0020]
Furthermore, the combination of general-purpose registers to be specified is made continuous.
[0021]
Enables a general-purpose register save instruction that allows the same specification.
[0022]
According to the above means,
By making the return instruction from the subroutine or exception processing and the return instruction of the general-purpose register the same instruction (for example, 16 bits), usability can be improved and the program capacity can be reduced.
[0023]
Even in the case of adopting a 16-bit variable instruction code system, it is possible to improve the overall program efficiency by effectively using instruction codes while simplifying instruction prefetching and instruction decoding.
[0024]
It has a general register save instruction that enables the same specification, and this is executed at the beginning of a subroutine or exception processing routine. Finally, the return instruction of the present invention is executed, so that the usability can be further improved. .
[0025]
By fixing the combination of general-purpose registers to be specified, information specifying the general-purpose registers can be shortened, and even a limited instruction code (for example, 16 bits) can be specified.
[0026]
By continuously returning the general-purpose register and the program counter, the internal operation can be facilitated and speeded up.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram of a microcomputer to which the present invention is applied.
[0028]
The microcomputer is a single chip type, a CPU that controls the whole, an interrupt controller (INT), a ROM that is a memory for storing a processing program of the CPU, a work area of the CPU, a temporary storage of data and a stack RAM, timer, serial communication interface (SCI), A / D converter, first to ninth input / output ports (IOP1 to IOP9), clock oscillator (CPG) functional blocks or modules And is formed on a single semiconductor substrate by a known semiconductor manufacturing technique.
[0029]
Such a microcomputer has, as power supply terminals, a ground level (Vss), a power supply voltage level (Vcc), an analog ground level (AVss), an analog power supply voltage level (AVcc), an analog reference voltage (Vref), and other dedicated control terminals. , Reset (RES), standby (STBY), mode control (MD0, MD1), and clock input (EXTAL, XTAL) terminals.
[0030]
The microcomputer operates in synchronization with a crystal oscillator connected to the terminals EXTAL and CTAL of the CPG or a reference clock (system clock) generated based on an external clock input to the EXTAL terminal. One cycle of this reference clock is called a state.
[0031]
The functional blocks of the microcomputer are connected to each other by an internal bus. A bus controller (not shown) that controls the bus is incorporated. In addition to the address bus and data bus, the internal bus includes a read signal, a write signal, and a bus size signal, which are coded as a bus command.
[0032]
Such functional blocks and modules are read / written by the CPU via the internal bus. The data bus width of the internal bus is 32 bits. The built-in ROM and RAM can be read / written in one state.
[0033]
Control registers included in the timer, the SCI, the A / D converter, the IOP1 to the IOP9, the SYSC, the INT, and the CPG are collectively referred to as an internal I / O register.
[0034]
Each input / output port is also used as an input / output terminal of an address bus, data bus, bus control signal or timer, SCI, and A / D converter. That is, the timer, the SCI, and the A / D converter each have an input / output signal and are input / output from / to the outside through a terminal also used as an input / output port. For example, IOPs 5 and 6 are also used as timer input / output terminals, and IOP7 is also used as an SCI input / output terminal. Analog data input / output (AIN0 to AIN7) terminals are also used as IOP8.
[0035]
The external interrupt input is shared with IOP9.
[0036]
When a reset signal RES is given to such a microcomputer, the microcomputer including the CPU is reset. When this reset is released, the operation mode specified by the mode control (single chip, external bus expansion, internal ROM enabled, etc.) is set, and the CPU reads the start address from a predetermined address (vector address). Performs reset exception handling that starts reading an instruction from the start address. Thereafter, the CPU sequentially reads and decodes the instruction from the ROM or the like, and based on the decoded content, processing of data including determination and operation of flags and bits, or RAM, timer, SCI, A / D conversion Data transfer to and from input / output ports. That is, the CPU refers to data input from a timer, SCI, A / D converter, input / output port, etc., or an instruction stored in a ROM or the like while referring to device status or instructions (switch, volume, etc.). Processing is performed based on the result, and a signal is output to the outside using an input / output port, a timer, and the like to control the device.
[0037]
The interrupt controller (INT) inputs the timer, SCI, A / D converter, and external input interrupt signals, and outputs an interrupt request signal to the CPU.
[0038]
When an interrupt request signal is given to the CPU, the CPU interrupts the processing being executed, branches to the predetermined processing routine through the interrupt exception processing state, performs the desired processing, and clears the interrupt factor. To do. At the end of the predetermined processing routine, a normal return instruction is given, and the interrupted process is resumed by executing this instruction.
[0039]
When executing an interrupt exception process, a program counter (PC) and a condition code register (CCR), which will be described later, are saved in a RAM or the like, and when executing a return instruction, the program counter (PC) and the condition code register (CCR) are restored. The
[0040]
Further, in the interrupt processing routine, it is necessary to use a general-purpose register in order to perform necessary processing. In order to save the state immediately before the occurrence of the interrupt, the required general-purpose register is saved on the stack at the beginning of the interrupt processing routine. This is, for example,
STM ER0-ER3, @ -SP
Is described. At the end of the interrupt processing routine, the saved general-purpose register is restored, and then the return instruction (RTE) is executed to continue the program immediately before the occurrence of the interrupt. In the prior art, for example,
LDM @ SP +, ER0-ER3
RTE
Is described.
[0041]
According to the present invention, the LDM and RTE instructions are executed in one instruction,
RTE / 4 ER0-ER3
To be described.
[0042]
Similarly, in the subroutine, a general-purpose register is used to perform necessary processing. For example, at the beginning of a subroutine,
STM ER0-ER1, @-SP
And finally,
LDM @ SP +, ER0-ER1
RTS
Is described.
[0043]
According to the present invention, the LDM and RTE instructions are executed in one instruction,
RTS / 2 ER0-ER1
To be described.
[0044]
FIG. 2 shows a configuration example (programming model) of general-purpose registers and control registers built in the CPU.
[0045]
The CPU has eight general-purpose registers having a 32-bit length. All general purpose registers have the same function and can be used as both address registers and data registers.
[0046]
The data register can be used as a 32-bit, 16-bit, and 8-bit register. The address register and 32-bit register are used as general registers ER (ER0 to ER7) at once. As 16-bit registers, general-purpose registers ER are divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have equivalent functions, and up to 16 16-bit registers can be used. Note that the general-purpose registers E (E0 to E7) may be particularly referred to as extension registers. As an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R7H) and general-purpose registers RL (R0L to R7L). These have equivalent functions, and up to 16 8-bit registers can be used. The usage method can be selected independently for each register.
[0047]
The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and is used implicitly in exception handling, subroutine branching, and the like. Exception handling includes the interrupt handling.
[0048]
PC is a 24-bit counter indicating the address of the next instruction to be executed by the CPU. Although not particularly limited, since all CPU instructions are in units of 2 bytes (words), the least significant bit is invalid, and the least significant bit is regarded as 0 when the instruction is read.
[0049]
The CCR is an 8-bit register and includes an interrupt mask bit (I) and half carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The half carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags check the data and reflect the state when executing a transfer instruction or an arithmetic instruction. Half carry (H) is used only for decimal correction.
[0050]
FIG. 3 shows a configuration example of the CPU.
[0051]
The CPU includes a control unit and an execution unit including the general-purpose registers ER0 to ER31, a program counter PC, and a condition code register CCR.
[0052]
The control unit is an instruction register IR , Instruction decoder DEC, register selector RESL , Including an interrupt acceptance circuit INT. The instruction decoder DEC is configured by, for example, a micro ROM, PLA (Programmable Logic Array), or a wiring logic. Part of the output of the instruction decoder DEC is fed back to the instruction decoder DEC. This includes a stage code (TMG) used for transition in each instruction code and a control signal (MOD) used between instruction codes. That is, the first word of the STM instruction generates a control signal that specifies the number of general-purpose registers, outputs an interrupt mask signal, and inhibits acceptance of interrupts.
[0053]
The interrupt control unit INT receives an interrupt request signal output from an interrupt controller shown in FIG. Further, referring to the interrupt mask signal output from the instruction decoder, if the interrupt is not masked, the instruction change unit CHG is instructed to execute an interrupt exception processing instruction code.
[0054]
The execution unit further includes a temporary register TR, an arithmetic logic unit ALU, an incrementer INC, a read data buffer DBR, a write data buffer DBW, and an address buffer AB. These blocks are connected to each other by a GB bus, a DB bus, and a WB bus.
[0055]
The arithmetic logic unit ALU uses various operations specified by instructions and calculation of effective addresses.
[0056]
The incrementer INC is mainly used for PC addition and address calculation.
[0057]
The DBR temporarily stores instruction codes and data read from the ROM, RAM, internal I / O register, or external memory (not shown). The DBW temporarily stores write data to the ROM, RAM, internal I / O register, or external memory. The timings of the CPU internal operation and the read / write operation outside the CPU are adjusted by DBR and DBW.
[0058]
The address buffer AB temporarily stores an address read / written by the CPU.
[0059]
Figure 4 shows the register selector RESL FIG. 2 shows a detailed block diagram of a part of
[0060]
register Selector RESL Holds the register field IR The register field information output from the control signal output from the instruction decoder DEC and the control signal output of the instruction decoder DEC are input to generate a register selection signal corresponding to each general purpose register.
[0061]
There are two register designation fields (r1, r2).
[0062]
The second register designation field (r2) is IR Bits 3 to 0 and the control signal output (inc, dec) of the instruction decoder.
[0063]
The output of the incrementer (RINC) to which the above is input is latched at the inversion φ # of the system clock and becomes the second register designation field (r2).
[0064]
For example,
STM ER0-ER3, @ -SP
In this case, 0 is given as the initial value of r2. Thereafter, r2 is changed from 0 → 1 → 2 → 3 by an increment signal (inc) at a predetermined timing described later.
[0065]
Also,
LDM @ SP +, ER0-ER1
Or
RTS / 2 ER0-ER1
In this case, 1 is given as the initial value of r2. Thereafter, r2 is changed from 1 to 0 by an increment signal (dec = rd−) at a predetermined timing described later.
[0066]
As a result, sharing the register selection circuit itself with other instructions can suppress an increase in logical scale.
[0067]
Since bit 3 of r2 is not used in these instructions, the incrementer (RINC) may be 3 bits. By having an incrementer (RINC), it is possible to designate any combination of general-purpose registers in succession without significantly increasing the logical scale.
[0068]
In addition, other RESL The details of are omitted.
[0069]
FIG. 5 shows the instruction formats of the first return instruction (RTS / n) and the second return instruction (RTE / n) including return of a plurality of general purpose registers.
[0070]
The first return instruction (RTS / n) is a return instruction from the subroutine, Second The return instruction (RTE / n) is a return instruction from the exception handling routine.
[0071]
Bits 15 to 7 are an operation field for designating a return instruction.
[0072]
When bit 6 is 0, the number of general-purpose registers is specified by bits 5 and 4. In the case of 01, 2 lines are used. The general-purpose register can be selected from 2, 3, 4 in succession. For example, in the case of four, ER0-3, ER1-4, ER2-5, ER3-6 can be specified. ER7 is also used as a stack pointer and is not targeted.
[0073]
When bit 6 is 1, the general-purpose register is not restored. That is, it is the same as the return instruction of the prior art, and a common instruction code (H′5470) is used.
[0074]
Bits 3 to 0 specify the general register to be used first. Bit 3 is reserved and is 0.
[0075]
For example, in the case of RTS / 4 ER0-3, since it is restored from ER3, the instruction code is H'5433.
[0076]
The second return instruction (RTE / n) is the same as that described above except that the operation field is different.
[0077]
The instruction format of the STM instruction is a two-word instruction, and a general-purpose register to be used first is designated by bits 3 to 0 of the second word. This is shared with the return instruction.
[0078]
The instruction format of the LDM instruction is the same.
[0079]
FIG. 6 shows an example of a stack configuration of a first return instruction (RTS / n) including a return of a plurality of general purpose registers and a second return instruction (RTE / n).
[0080]
The last address of the stack is indicated by the stack pointer (SP: ER7).
[0081]
A program counter is saved to the stack by a subroutine branch instruction (for example, a BSR instruction). Thereafter, a required general-purpose register is saved at the beginning of the subroutine (for example, STM ER0-ER1, @ -SP).
[0082]
Correspondingly, the first return instruction (for example, RTS / 2 ER0-ER1) first reads from the stack as the return of the specified general-purpose register, and then reads the specified general-purpose register (ER1, ER0). Store sequentially. Subsequently, as the return of the program counter, the stack is read and stored in the program counter, and the instruction is read according to the contents.
[0083]
Similarly, the program counter and the condition code register are saved in the stack by exception processing. The program counter has 24 bits and is saved in the stack in combination with the condition code register. Thereafter, a required general-purpose register is saved at the beginning of the subroutine (for example, STM ER0-ER3, @ -SP).
[0084]
Correspondingly, the second return instruction (for example, RTE / 4 ER0-ER3) first reads from the stack as the return of the specified general register, and specifies the specified general registers (ER3, ER2, ER1). , ER0). Subsequently, as a return of the program counter and the condition code register, reading from the stack is performed, predetermined contents are stored in the program counter and the condition code register, and an instruction is read.
[0085]
FIG. 7 shows an operation flow of the first return instruction (RTS / n).
[0086]
In step 1, the content of the stack pointer (SP) is output to the address bus (IAB) by the control signal A, and a long word read is instructed. In addition, an increment (+4) of the contents of SP is instructed. The control signal C instructs storage of the read data in the DBR.
[0087]
In steps 2 to 5, the control signal B instructs to write the contents read in the previous step to the general-purpose register. Specifically, the data is once output to the internal bus GB, output to the internal bus WB via the ALU, and written to the designated general-purpose register. register Selector RESL Is decremented (-1) in the register field. Similarly to the above, the control signal A instructs the output of the contents of the stack pointer (SP) to the address bus (IAB), the reading of the long word, and the increment (+4) of the contents of the SP. The control signal C instructs storage of the read data in the DBR. Steps 2 to 4 are executed a predetermined number of times according to the designated number (n) of general-purpose registers.
[0088]
In step 6, the control signal B instructs to write the contents read in the previous step to the program counter (PC).
[0089]
In step 7, the contents of the program counter (PC) are output to the address bus (IAB) as an instruction read by the control signal A, and a memory word read is instructed. In addition, an increment (+2) of the contents of the PC is instructed. The read instruction is stored in the IR by the control signal C.
[0090]
Similarly, in step 8, the control signal A instructs the output of the contents of the program counter (PC) to the address bus (IAB), the memory word read, and the increment (+2) of the contents of the PC. Control signal B instructs the input of the instruction (IR) read in the previous step to the instruction decoder. Execution of the next instruction is started.
[0091]
The contents read from the stack are temporarily stored in the PC when the PC is restored. However, this may not be performed, but may be read from the DBR instead of the PC in step 7.
[0092]
In the case of a return instruction that does not return the general-purpose register, steps 2 to 5 may be skipped. In other words, steps 2 to 5 may be added to the return instruction of the prior art.
[0093]
According to such an operation flow, a hardware description language (HDL) can be described and an instruction decoder DEC can be generated. The part relating to the first return instruction (RTS / n) is as follows.
[0094]

This description follows the HDL description language standardized as IEEE 1364. The HDL description language itself is described in “Introductory Verilog-HDL Description” issued by CQ Publishing Co., Ltd. in July 1996.
[0095]
Cases and cases execute operations corresponding to subsequent values (16′b01010100_0001 ???, 4′b0001 :, etc.) according to variables (opcode, tmg) in parentheses () that follow. One operation is described from begin to end.
[0096]
In (1), the condition by the instruction decoder input (opcode) is designated. Under this condition, the operation of the instruction code corresponding to RTS / 2 is described in (2) to (12). Further, for each instruction code, a condition by an instruction decoder input (tmg) corresponding to a step is instructed. The operation of the first step of RTS / 2 is described in (4) to (7). (5) specifies that the next step (nextmg) is the fourth step. Nexttmg is input to the instruction decoder as tmg after one state. In (6), the bus command is a long word read. As long_read, a predetermined code is assigned as a parameter. After this, other control signals are described. Similarly, the operation of the fourth step is described in (8) to (11). The operations of the fifth to eighth steps will be described up to (12).
[0097]
Similarly, the operation of the instruction code corresponding to RTS / 3 is described from (13) onward under the condition of the instruction decoder input (opcode). In the behavior description of the first step, (15) specifies that the next step (nextmg) is the second step. The operation of the second step is described after (17). Furthermore, the operations of the fourth to eighth steps are also described.
[0098]
Thereafter, the operation of an instruction code corresponding to RTS / 4 is described, and a second return instruction (RTE / n), a multiple register save instruction (STM), and other instruction codes are also described.
[0099]
FIG. 8 shows the execution timing of the first return instruction (RTS / n).
[0100]
This is an example in the case of n = 2.
[0101]
Although not particularly limited, the timing when the read / write of the built-in ROM and RAM can be read / written in one state and the program is placed on the built-in ROM and the stack is placed on the built-in RAM is shown.
[0102]
At φ # of T0 (# indicates inverted logic), the CPU address buffer (MAB) or address is output to the IAB. Also, a bus command (BCMD) indicating instruction fetch (if) is output from the instruction decoder.
[0103]
At φ of T1, the contents of IAB are output to PAB, a read cycle is started based on the bus command, and data is output to PDB. The read data of the PDB is obtained on the internal data bus IDB at φ #, and this is latched at IR by φ at T2. The above operation is performed by controlling the execution of the previous instruction (prefetch). Here, the built-in ROM and RAM are not connected to the PAB and PDB, but operations corresponding to the PAB and PDB are performed in the module, and this timing diagram shows the operation in the module.
[0104]
When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, the instruction code is input to the DEC at φ of T2, and the content of the instruction is decoded. According to the result of decoding, a control signal is output to control each part. Part of the instruction (register specified feed: r) is given to the register select.
[0105]
As step 1, the content of SP is read to the internal bus GB at φ # of T2 and input to AB and INC. The address IAB is output from AB. A long word read bus command is output.
[0106]
The result incremented (+4) by INC at φ of T3 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T3, and stored in the DBR with φ of T4.
[0107]
As step 4, at φ4 and φ # of T4, the contents of the DBR are written to the designated general-purpose register (r) via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T3, the contents of SP are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T4 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T4, and stored in the DBR at φ of T5.
[0108]
As step 5, at φ5 and φ # of T5, the contents of the DBR are written to the designated general-purpose register (r) via the internal buses GB, ALU, and the internal bus WB. The register specification field is decremented. Similarly to the above, at φ4 of T4, the contents of SP are read out to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T5 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T5, and stored in the DBR at φ of T6.
[0109]
In step 6, the contents of DBR are written to the PC through internal buses GB, ALU, and internal bus WB at φ and φ # of T6.
[0110]
In step 7, at φ6 of T6, the contents of the PC are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T7 is written to the PC via the internal bus WB.
[0111]
In step 8, the contents of the PC are read to the internal bus GB at φ # of T7 and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T8 is written to the PC via the internal bus WB. The instruction code read by φ at T8 is input to the DEC via the IR, and the next instruction is executed.
[0112]
FIG. 9 shows an operation flow of the second return instruction (RTE / n).
[0113]
In response to the first return instruction (RTS / n), in step 6, writing to the CCR is performed together with the PC. Other operations can be performed similarly.
[0114]
FIG. 10 shows the execution timing of the second return instruction (RTE / n).
[0115]
This is an example in the case of n = 4.
[0116]
In the same manner as described above, the instruction code is input to DEC at φ of T2, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Part of the instruction (register specified feed: r) is given to the register select.
[0117]
As step 1, the content of SP is read to the internal bus GB at φ # of T2 and input to AB and INC. The address IAB is output from AB. A long word read bus command is output.
[0118]
The result incremented (+4) by INC at φ of T3 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T3, and stored in the DBR with φ of T4.
[0119]
As step 2, at φ4 and φ # of T4, the contents of the DBR are written to the designated general-purpose register (r) via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T3, the contents of SP are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T4 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T4, and stored in the DBR at φ of T5.
[0120]
In step 3, the contents of DBR are written to the designated general-purpose register (r) via internal buses GB, ALU, and internal bus WB at φ and φ # of T5. The register specification field is decremented. Similarly to the above, at φ4 of T4, the contents of SP are read out to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T5 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T5, and stored in the DBR at φ of T6.
[0121]
As step 4, at φ6 and φ # of T6, the contents of DBR are written to the designated general-purpose register (r) via internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ5 of T5, the contents of SP are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T6 is written to the SP via the internal bus WB. The data read from the stack is output to the IDB from φ # of T6, and stored in the DBR at φ of T7.
[0122]
In step 5, the contents of DBR are written to the designated general-purpose register (r) via internal buses GB, ALU, and internal bus WB at φ and φ # of T7. The register specification field is decremented. Similarly to the above, at φ # of T6, the contents of SP are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. A long word read bus command is output. The result incremented (+4) by INC at φ of T7 is written to the SP via the internal bus WB. Data read from the stack is output to the IDB from φ # of T7, and stored in the DBR at φ of T6.
[0123]
In step 6, the contents of DBR are written to CCR and PC via internal buses GB, ALU, and internal bus WB at φ and φ # of T6. Bits 31-24 of the DBR are written to the CCR and bits 23-0 are written to the PC.
[0124]
In step 7, the contents of the PC are read to the internal bus GB at φ8 of T8 and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T9 is written to the PC via the internal bus WB.
[0125]
In step 8, the content of the PC is read to the internal bus GB at φ # of T9 and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T10 is written to the PC via the internal bus WB. The instruction code read by φ at T10 is input to the DEC via the IR, and the next instruction is executed.
[0126]
FIG. 11 shows an operation flow of a save instruction (STM) for a plurality of general-purpose registers.
[0127]
Step 0 is controlled by the first word of the instruction code. The control signal A instructs the output of the program counter (PC) contents to the address bus (IAB), the memory word read, and the PC contents increment (+2). The control signal B instructs the input of the second word of the instruction code to the instruction decoder and the information (MOD) on the number of general-purpose registers specified by the first word.
[0128]
In step 1, the control signal A indicates the decrement (-4) of the contents of the stack pointer (SP). In steps 2 to 5, the control signal A instructs to output the contents of the stack pointer (SP) to the address bus (IAB) and to write a long word. Control signal B instructs the contents of the general-purpose register to be stored in DBW. Control signal C instructs the output of the contents of DBW to IDB. register Selector RESL Is instructed to increment the register field (-1). In steps 2 to 4, the SP content is decremented (-4). Steps 2 to 5 are executed a predetermined number of times according to the designated number (n) of general-purpose registers.
[0129]
In step 6, the control signal A instructs the output of the program counter (PC) contents to the address bus (IAB), the memory word read, and the PC contents increment (+2). Control signal B instructs the input of the instruction (IR) read in the previous step to the instruction decoder. Execution of the next instruction is started.
[0130]
In steps 2 to 5, after the contents of the general-purpose register are transferred to the DBW, the contents of the general-purpose register may be cleared to zero. After saving the general-purpose register, clearing it to 0 and confirming its contents can simplify the subsequent processing.
[0131]
For example, the MOV instruction can be omitted when 0 is assigned to the general-purpose register. When substituting 1 etc.,
MOV. L # 1, ERn
Instead of using
MOV. B # 1, RnL
Can be used. Immediate data has an area corresponding to the data size in the instruction code. Than the instruction code length of L (for example, 3 words). The instruction code length of B (for example, 1 word) is shorter. This can contribute to shortening the program capacity.
[0132]
In general, constant values used in a program often have relatively small values such as 0 and 1.
[0133]
FIG. 12 shows the execution timing of a save instruction (STM) for a plurality of general purpose registers.
[0134]
This is an example in the case of n = 2.
[0135]
The first word (stm-1) of the instruction code is input to DEC at φ of T2, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Part of the instruction (register specified feed: r) is given to the register select.
[0136]
As step 0, the contents of the PC are read to the internal bus GB at φ # of T2 and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T2 is written to the PC via the internal bus WB. The instruction code read by φ at T3 is input to DEC via IR, and the next instruction is executed.
[0137]
The second word (stm-2) of the instruction code is input to the DEC at φ of T3, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Part of the instruction (register specified feed: r) is given to the register select.
[0138]
As step 1, the content of SP is read to the internal bus GB at φ # of T3 and input to INC. The result of decrementing (−4) by INC at φ of T3 is written to the SP via the internal bus WB.
[0139]
As Step 2, at φ4 of T4, the contents of SP are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. A longword write bus command is output. The result of decrement (−4) by INC at φ of T5 is written to the SP via the internal bus WB. In addition, the contents of the designated general-purpose register (r) are written to the DBW via the internal bus DB. The register specification field is incremented. The contents of DBW are output to IDB from φ # of T5.
[0140]
In step 5, the content of SP is read to the internal bus GB at φ # of T5, and the address IAB is output via AB. A longword write bus command is output. The contents of the general-purpose register designated (r) are written to DBW via the internal bus DB at φ of T5. The register specification field is incremented. The contents of DBW are output to IDB from φ # of T5.
[0141]
As step 6, at φ6 of T6, the contents of the PC are read to the internal bus GB and input to AB and INC. The address IAB is output from AB. The result incremented (+2) by INC at φ of T7 is written to the PC via the internal bus WB. The prefetched instruction code (next) is input to the DEC via the IR, and the next instruction is executed.
[0142]
As described above, in Steps 2 to 5, the contents of the general-purpose register are cleared to 0 with φ # of T5 and T6. This is preferably done by setting the internal bus WB at that timing to 0 and writing it to the general-purpose register.
[0143]
FIG. 13 shows an outline of the development environment of the CPU of the present invention.
[0144]
The user creates a program in C language or assembly language using various editors. This is usually created by dividing it into a plurality of modules.
[0145]
The C compiler inputs each C language source program created by the user and outputs an assembly language source program or object module.
[0146]
For example, when creating a program in C language,

The function seq0 described as follows is compiled as follows for the CPU of the present invention.
[0147]

The general purpose registers ER3 and ER4 used in the function are saved to the stack by the STM instruction and cleared to 0. Restored from stack on return instruction.
[0148]
When calling the function seq0 in the main program,
seq0 ();
And
JSR @ _seq0
And compiled into a subroutine branch instruction.
[0149]
The assembler inputs an assembly language source program and outputs an object module.
[0150]
The linkage editor inputs a plurality of object modules generated by the C compiler and assembler, resolves external references and relative addresses of each module, combines them into one program, and outputs a load module.
[0151]
The load module can be input to a simulator / debugger, simulate a CPU operation on a system development apparatus such as a personal computer, display an execution result, and analyze and evaluate a program. In addition, by inputting into an emulator and performing on-circuit emulation that operates on an actual application system or the like, it is possible to analyze and evaluate the actual operation of the entire microcomputer.
[0152]
Furthermore, the load module can be input to a ROM writing device such as a PROM writer, and the created program can be loaded into the external flash memory or the like when the built-in ROM of the microcomputer is a flash memory or the like. Alternatively, it can be written in the built-in ROM in the manufacturing process of the microcomputer. If necessary, it is converted into a desired format by an object converter or the like.
[0153]
In addition, a general subroutine can be provided as a librarian.
[0154]
The CPU definition information file designates a CPU to be compiled, and makes it possible to use a common development environment for the (existing) CPU having no return instruction of the present invention and the CPU of the present invention.
[0155]
For example, in the CPU definition information file,
SET CPU = CPU1;
To select the CPU of the present invention.
[0156]
If a CPU that does not have a return instruction of the present invention is selected with reference to the CPU definition information file at the time of compilation, the function is

It becomes. MOV. L may be changed according to the processing content of the function.
[0157]
In addition to the function to convert C language programs into CPU instructions, the C compiler itself has improved functions not directly related to the CPU instruction set, such as C ++ language program compilation and inter-module optimization. However, in an individual compiler for each CPU, these functional improvements must be applied to all the individual compilers. If a common C compiler is used as in the present invention, it is easy to improve the functions not directly related to the CPU instruction set, and to improve development efficiency.
[0158]
According to the said Example, the following effects are obtained.
[0159]
A single instruction performs multiple general register and return operations, and a return operation from a subroutine or exception handling routine, thereby relatively shortening the instruction code length (for example, shortening by 2 words) and reading the instruction The number of times can be reduced and the speed can be increased.
[0160]
For example, since a function frequently used in the C language or the like is a subroutine, the number of return instructions from the subroutine corresponding to this number is used. Since necessary data for each function is allocated to the general-purpose register, the contents of the previous general-purpose register are saved / restored. Therefore, the effect of shortening the instruction code length by such a return instruction is also increased.
[0161]
In addition, since the number of general-purpose registers to be saved / restored is different for each function, a program can be created by supporting multiple instructions with different numbers of registers or by supporting return instructions that do not involve general-purpose register restoration. Can be improved and the usability can be improved.
[0162]
Even when the CPU has a large number of general-purpose registers, it is possible to specify the general-purpose registers to be restored, so that the degree of freedom in using the general-purpose registers is hardly lost. Further, undesired general purpose registers are not saved / restored.
[0163]
The instruction code length can be shortened by using a fixed combination that designates multiple general-purpose registers, and the number of execution states of each instruction is fixed to reduce internal conditional branching (instruction The decoder can be described according to the input opcode of the decoder), and the internal logic can be simplified and the logic scale can be reduced. It can be easily realized with a wired logic or the like without using a microprogram. Regardless of the microprogram, a wired logic or the like can contribute to speeding up the logic circuit. register selector By having an incrementer at the same time, it is possible to specify an arbitrary continuous combination while minimizing an increase in logical scale.
[0164]
A general-purpose register save instruction (STM) that enables the same designation is executed at the beginning of a subroutine or exception handling routine, and finally, the return instruction of the present invention is executed. Can be improved. When the general-purpose register save instruction is executed, the general-purpose register is cleared after the save, thereby further reducing the instruction code length and the number of execution states.
[0165]
Further, by continuously reading / writing data, it is easy to use these effectively when burst operation for the memory or the bus width is expanded.
[0166]
By including the instruction set of the existing CPU at the source program level or the object program level and adding the above instructions, the software assets can be used effectively and the software development efficiency of the user is improved. Can do. Both of the advantages of maintaining compatibility at the source program level or the object program level and the advantages of adding the transfer instruction can be enjoyed.
[0167]
The invention made by the inventors as described above is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention.
[0168]
The instruction code is an example and can be variously changed. Needless to say, the present invention can be applied when developing a new instruction set in addition to adding to an existing instruction set.
[0169]
The stack structure in exception handling is 32 bits by combining CCR and PC, but these can be divided into 16 bits and 32 bits, or other control registers can be added. The PC may be 32 bits.
[0170]
The configuration and number of general-purpose registers or the number of general-purpose registers that are restored by a return instruction can be arbitrarily changed. The number of general-purpose registers to be restored may be one. The order stored in the stack can be arbitrarily changed. When restoring the general-purpose register, it is more convenient to read continuously with PC (and CCR).
[0171]
The incrementer (RINC) may also perform addition / subtraction with the output of the instruction decoder in addition to increment / decrement. In the case of the return instruction of the present invention, 1/2/3 may be sequentially subtracted from the register designation field of the instruction code. The register specification field included in the instruction code does not necessarily correspond to the general-purpose register specified first. A desired general-purpose register may be specified in combination with the addition / subtraction.
[0172]
When ER7, which is a stack pointer, is designated as a general-purpose register to be restored, writing to ER7 may be prohibited. This is because saving / returning the stack pointer is meaningless and a predetermined point operation may be performed.
[0173]
When executing a general register save instruction, it may have both an instruction to clear the general register after saving and an instruction to hold it. This may be specified by a predetermined bit of the first word of the instruction code, and a control signal (MOD) may be generated to change the operation of the second word.
[0174]
The contents of clearing the general-purpose register are not limited to 0, but may be other values. A means for designating the contents to be cleared may be provided separately.
[0175]
The basic unit of instruction is not limited to 16 bits. The return instruction of the present invention can also be applied in 8-bit units and 32-bit units.
[0176]
For simplicity, the bus width is set to 32 bits and the instruction read is set to 16 bits. However, the instruction read can be set to 32 bits and the speed can be increased. Such an example is described in Japanese Patent Application No. 11-167812. Alternatively, the bus width may be 16 bits, and long word read / write may be executed in two read / write operations in units of words. Such an example is described in Japanese Patent Application No. 11-320518.
[0177]
There are no restrictions on other functional blocks of the microcomputer.
[0178]
In the above description, the case where the invention made by the present inventor is applied to the microcomputer, which is the field of use behind the present invention, has been described. Therefore, the present invention can be applied to at least a data processing apparatus having a plurality of register means.
[0179]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in this subject will be briefly described as follows.
[0180]
In a return instruction from a subroutine or exception processing, the instruction code includes information specifying a plurality of general-purpose registers. When the instruction code is executed, the specified general-purpose register is returned in addition to the return of the program counter. By doing so, usability can be improved, and the program capacity and the number of execution states can be shortened.
[0181]
Furthermore, the instruction code length can be shortened by making the combination of general-purpose registers to be specified continuous.Furthermore, by fixing the number of execution states of each instruction, it is possible to reduce internal conditional branching, The internal logic can be simplified and the logical scale can be reduced. Even in the case of adopting a 16-bit variable instruction code system, it is possible to improve the overall program efficiency by effectively using instruction codes while simplifying instruction prefetching and instruction decoding.
[0182]
It has a general register save instruction that enables the same specification, and this is executed at the beginning of a subroutine or exception processing routine. Finally, the return instruction of the present invention is executed, so that the usability can be further improved. .
[0183]
By continuously returning the general-purpose register and the program counter, the internal operation can be facilitated and speeded up.
[0184]
By supporting a plurality of return instructions with different numbers of registers, it is possible to specify consecutive general-purpose registers, further facilitate the creation of a program, and improve usability.
[Brief description of the drawings]
FIG. 1 is a block diagram of a microcomputer to which the present invention is applied.
FIG. 2 is a diagram illustrating a configuration example of a general-purpose register and a control register built in the CPU.
FIG. 3 is a diagram illustrating a configuration example of a CPU.
FIG. 4 is a register selector. RESL The detailed block diagram of a part of.
FIG. 5 is an instruction format diagram of a first return instruction (RTS / n) including a return of a plurality of general purpose registers and a second return instruction (RTE / n).
FIG. 6 is a diagram illustrating a configuration example of a stack of a first return instruction (RTS / n) including a return of a plurality of general-purpose registers and a second return instruction (RTE / n).
FIG. 7 is a flowchart of the operation of a first return instruction (RTS / n).
FIG. 8 is a diagram showing the execution timing of a first return instruction (RTS / n).
FIG. 9 is a diagram showing an operation flow of a second return instruction (RTE / n).
FIG. 10 is a diagram of execution timing of a second return instruction (RTE / n).
FIG. 11 is a diagram showing an operation flow of a save instruction (STM) for a plurality of general-purpose registers.
FIG. 12 is a diagram showing the execution timing of a save instruction (STM) for a plurality of general-purpose registers.
FIG. 13 is a schematic diagram of a CPU development environment according to the present invention.

Claims (4)

A data processing apparatus for sequentially executing predetermined instructions,
It has a program counter, stack and multiple registers that can be specified by register number
The stack is a data storage means that can write and read data, and can sequentially read from the content stored last.
The data processing device executes an instruction stored at an address specified by the program counter, and updates the value of the program counter.
The data processing device reads from the stack a first instruction to write the contents of the program counter to the stack, a second instruction to write the contents of a specified register of the plurality of registers to the stack, and And a third instruction that can specify the number and register number of the registers among the plurality of registers that should be written back from the stack, and read from the stack. And a fourth instruction capable of specifying the number of registers and the register number of the plurality of registers whose contents are to be written back from the stack.
The data processing apparatus according to claim 3, wherein the third instruction and the fourth instruction have different possible values for the number of registers that can be specified. The data processing apparatus according to claim 1, wherein
Arithmetic operation means for register selection,
In the third instruction, a plurality of contents sequentially read from the stack are calculated by the arithmetic operation means using the value specified in the instruction code of the third instruction in the register and this value. A data processing apparatus capable of writing to a plurality of registers designated based on the value . The data processing apparatus according to claim 1 or 2 ,
The data processing device is further capable of executing a fifth instruction;
The data processing apparatus according to claim 5, wherein the fifth instruction can designate a register number whose contents are to be restored from the stack among the plurality of registers. The data processing apparatus according to any one of claims 1 to 3 ,
The data processing device can further execute a return instruction,
The data processing apparatus according to claim 1, wherein the return instruction can write back the contents read from the stack to the program counter.

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