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JP3786580B2 - Chemical vapor deposition apparatus and semiconductor film manufacturing method using the same - Google Patents
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JP3786580B2 - Chemical vapor deposition apparatus and semiconductor film manufacturing method using the same - Google Patents

Chemical vapor deposition apparatus and semiconductor film manufacturing method using the same Download PDF

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JP3786580B2
JP3786580B2 JP2001028240A JP2001028240A JP3786580B2 JP 3786580 B2 JP3786580 B2 JP 3786580B2 JP 2001028240 A JP2001028240 A JP 2001028240A JP 2001028240 A JP2001028240 A JP 2001028240A JP 3786580 B2 JP3786580 B2 JP 3786580B2
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reaction chamber
film
pressure
temperature
deposition
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JP2001257171A (en
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光敏 宮坂
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Seiko Epson Corp
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Seiko Epson Corp
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Description

【0001】
【発明の属する技術分野】
本発明は薄膜半導体装置や集積回路、太陽電池、電荷結合装置等に適応されるシリコン膜等の半導膜の形成方法及び、半導体膜形成に用いる減圧化学気相堆積装置とアクティブマトリックス液晶ディスプレイ等に適応される半導体膜を用いた薄膜半導体装置に関する。
【0002】
【従来の技術】
近年、液晶ディスプレイの大画面化、高解像度化に伴い、その駆動方式は単純マトリックス方式からアクティブマトリックス方式へ移行し、大容量の情報を表示出来るように成りつつ有る。アクティブマトリックス方式は数十万を越える画素を有する液晶ディスプレイが可能で有り、各画素毎にスイッチングトランジスタを形成するもので有る。各種液晶ディスプレイの基板としては、透過型ディスプレイを可能ならしめる溶融石英板や硝子などの透明絶縁基板が使用されている。
【0003】
しかしながら、表示画面の拡大化や低価格化を進める場合には絶縁基板として安価な通常ガラスを使用するのが必要不可欠で有る。従って、この経済性を維持して尚、アクティブマトリックス方式の液晶ディスプレイを動作させる薄膜トランジスタを安価なガラス基板上に安定した性能で形成する事が可能な技術が望まれていた。
【0004】
薄膜トランジスタの能動層としては、通常アモルファスシリコンや多結晶シリコンなどの半導体膜が用いられるが、駆動回路まで一体化して薄膜トランジスタで形成しようとする場合には動作速度の速い多結晶シリコンが有利である。
【0005】
この様に通常のガラス基板上に多結晶シリコン膜等の半導体膜を能動層とする薄膜半導体装置を作成する技術が求められているが、通常のガラス基板を用いる際には最高プロセス湿度が約600℃程度とのガラス歪点温度以下とする大きな制約が有る。即ち低温プロセスで液晶ディスプレイを動作し得る薄膜トランジスタと、駆動回路を高速作動し得る薄膜トランジスタの能動層を形成する技術が望まれている。
【0006】
従来LPCVD法で該半導体膜を堆積するには、第一に到達最低背景圧力が10-3〜10-4torrのLPCVD装置を用いて堆積圧力を40mtorr程度以上として、ガラス歪点温度と同等、もしくはそれよりも若干高い温度(610℃〜640℃)迄堆積温度を上げてシリコン膜等の半導体膜を堆積していた。或いは、反応室に於ける実効排気速度が1SCCM/mtorrから3SCCM/mtorr程度以下で有るLPCVD装置を用いて、堆積温度をガラス基板を使用し得る最高温度(600℃〜620℃)程度に迄高め、原料ガスであるモノシラン(SiH4)を10SCCM程度流し、モノシラン分圧を数mtorrとしてシリコン膜等の半導体膜を体積していた(Solid State Devices and Materials 1991,Extended Abstracts,P.614)。
【0007】
その他の方法で能動層半導体膜を形成するには、第二の方法として例えば絶縁基板上に570℃以下の温度で減圧CVD法により能動層となるシリコン膜等の半導体膜を堆積し、しかる後640℃以下の温度で24時間程度の熱処理を施して結晶化した半導体膜を形成し、薄膜トランジスタの特性を高めている(特開昭63−307776)。第三の方法はRFマグネトロン・スパッタリングやプラズマCVD法で300℃程度以下の温度にてアモルファス・シリコン膜を堆積した後、各種レーザー照射を行う事でシリコン膜を形成し、薄膜トランジスタの能動層とするものである(Jpn.J.Appl.phys.28.P1871(1989)や電子情報通信学会技術研究報告EID−88−58など)。
【0008】
【発明が解決しようとする課題】
しかしながら、前述の従来技術にはそれそれ種々の問題が内在している。第二のシリコン膜を堆積した後、熱処理を施す方法では熱処理温度がガラス基板を使用するには高過ぎ、又この処理温度を600℃程度以下とした場合、処理時間に数十時間以上費やし、やはりガラス基板を使用し得ない。加えて第一のLPCVD法による製造方法に比較して、製造工程が冗長と化し、生産性の低下及び製品価格の上昇を招くと言った問題点が有る。第三のシリコン膜を堆積した後レーザー照射を行う方法では、半導体特性のばらつきが大きく、大面積に均一に沢山の薄膜半導体装置を作成し得ぬとの問題点が有る。加えて第一のLPCVD法に比較すると、第二の方法同様に製造工程が著しく煩雑冗長と化し、生産性の低下や高価な加工装置の購入、製品価格の上昇を招くと言った問題点が有る。
【0009】
一方、従来のLPCVD法でシリコン膜等の半導体膜を形成する方法では、堆積装置と堆積技術が未熟で有る為、能動層としてこれらの半導体膜を用いた場合、半導体特性が不十分で有り高精細高画質液晶ディスプレイのスイッチング素子や駆動回路用としては未だ不適切であるとの問題点が有った。
【0010】
そこで本発明はこの様な諸問題点の解決を目指し、その目的は良質な半導体膜の形成をLPCVD法のみで行うという簡略な方法を提供する事及びそうした半導体膜を利用した良好な薄膜半導体装置の製造方法及びそれを実現し得る減圧化学気相堆積装置を提供する事にある。
【0011】
【課題を解決するための手段】
本発明の化学気相堆積装置(CVD装置)は、少なくとも反応室とターボ分子ポンプと該ターボ分子ポンプの排気口側に接続された第二の真空ポンプを具備する化学気相堆積装置(CVD装置)に於いて、該ターボ分子ポンプの排気口へ不活性ガスを該ガス流量をガス流量調整器にて調整して流し込むことでターボ分子ポンプ排気口の圧力を調整する事に依り、該反応室の圧力を調整する圧力調整装置を備える事を特徴とする。
【0012】
本発明の化学気相堆積装置(CVD装置)は、少なくとも反応室とターボ分子ポンプとゲート・バルブと該ターボ分子ポンプの排気口側に接続された第二の真空ポンプを具備する化学気相堆積装置(CVD装置)に於いて、該ターボ分子ポンプが該反応室に直接設置されて居り、且つ該ゲート・バルブが該ターボ分子ポンプと該第二の真空ポンプの間に設置されて居る事を特徴とする。
【0013】
本発明の化学気相堆積装置は、反応室内の圧力を調整する為の圧力調整装置がゲート・バルブと第二の真空ポンプの間に設置されて居る事を特徴とする。
【0014】
本発明の半導体膜の製造方法は、上記のいずれかに記載の化学気相堆積装置(CVD装置)を用いて半導体膜を形成することを特徴とする。
【0015】
【発明の実施の形態】
(実施例1)
以下本発明の実施例を説明するが、本発明が以下の実施例に限定される物では無い。
【0016】
図1は本発明に依る減圧化学気相堆積装置(LPCVD装置)の概念図で有る。LPCVD装置は縦型炉で石英反応室101の中央部付近に300mm□のガラス基板102を水平に設置し、シラン(SiH4)ジシラン(Si2H6)或いはゲルマン(GeH4)等の原料ガスの熱分解を利用してシリコン膜等の半導体膜を堆積する。反応室101の口径は直径600mmでその容積は184.51で有る。真空排気装置は本実施例1ではターボ分子ポンプ106とロータリーポンプ107より構成されている。
【0017】
真空排気装置はこの他にもメカニカル・ブースター・ポンプやドライポンプなどを組み合わせても良い。原料ガス及びヘリウム・窒素・アルゴン・水素等の希釈ガスは必要に応じてガス導入管103を通じて反応室101に導入され、マニホールド104にゲート・バルブ及びコンダクタンス・バルブ105を介して直接取り付けられたターボ分子ポンプ106よりロータリー・ポンプ107を経して排気される。マニホールードと反応炉内に特別な区切りはなく、両者は一体化してその区別はない。反応室101の外側には3ゾーンに分かれたヒーター108が設置されて居り、それらを独立に調整する事で反応室中央部付近に所望の温度で均熱帯を形成する。この均熱帯は約350mmの高さで広がり、その範囲内での温度のずれは、例えば600℃に、設定した時0.2℃以内で有る。従って挿入基板の間隔を10mmとすれば1バッチで35枚の基板の処理が可能で有る。本実施例1では20mm間隔で17枚の基板をターン・テーブル109上に広がる均熱帯内に設置した。
【0018】
排気はターボ分子ポンプ106とロータリーポンプ107を直結して行った。本発明で用いたターボ分子ポンプ106は化学対応タイプでシリコン膜等半導体膜堆積中も運転可能である。又、このターボ分子ポンプは窒素に対して22001/secの排気速度を有している。反応室101入り口に於ける実効排気速度を最大限大きくする為、ターボ分子ポンプ106とゲート・バルブ及びコンダクタンスバルプ105はマニホールド104に直付けされている。この結果炉内温度600℃に於いて両ポンプを運転した状態で窒素を100SCCMガス導入管103より流した時の反応室101内平衡圧力は1.2×10-3torrとなり、実効排気速度は83.3SCCM/mtorrとなった。又同じ条件下で窒素を3.97SCCM、15・83SCCM、39.68SCCM、300SCCM流した時のそれぞれの反応室内平衡圧力は9.5×10-5torr、2.5×10-4torr、5.5×10-4torr、3.0×10-3torrで有り、対応する実効排気速度はそれそれ41.8SCCM/mtorr、63.3SCCM/mtorr、72.1SCCM/mtorr、100SCCM/mtorrとなった。
【0019】
これらの圧力は窒素で校正された電離真空計を用いて測定された。又反応中など窒素以外のガスが流される場合は、測定値がガス種に依存しない融膜式圧力計を用いて圧力を測定した。融膜式圧力計の最小分解能は1×10-6torrで有った。
【0020】
本実施例1で用いたターボ分子ポンプは、ターボ分子ポンプの吸気穴に於ける圧力が3mtorr程度で有る時、窒素に対するポンプ吸気穴排気速度SpはSp=22001/secで有る。一方、反応室に於ける同圧力の実効排気速度Seは上述の如くSe=100SCCM/mtorr=12671/secで有る。又ゲート・バルブ及びコンダクタンス・バルブのコンダクタンスCvはCv=31501/secで有る。従って、マニホールドやマニホールドと反応室との間のコンダクタンス等、残りのすべてのコンダクタンスの合計Cxは、
1/se=1/Sp+1/Cv+1/Cx
に依り、Cx=579371/secで有る。これは本発明がマニホールド自身の有するコンダクタンス、並びにマニホールドと反応室との間のコンダクタンスを充分大きく取った為、残りの総コンダクタンスCxをポンプ吸気穴排気速度Spに比べてはるかに大きくし得、結果として反応室に於ける実効排気速度Seを大きくし得た事を物語っている。
【0021】
本発明に依るLPCVD装置のマニホールド部を縦(上下)方向から見た概念図を図9に示す。マニホールド104全体の内部は空洞と化しており、この広い空洞を通じて反応室からの排気が取られる。内部には所々補強の梁901が設けられて居るが、マニホールド空洞部の幅600mmに比べて充分細い為、マニホールド部のコンダクタンス低下の要因とはなり得ない。マニホールド内部の厚みは125mmで有り、ガスが通過する断面積は最も狭い部位でも700cm2以上と広く、マニホールド内部のコンダクタンスをポンプの排気速度Spやゲート・バルブ及びコンダクタンス・バルブのコンダクタンスCvより充分大きくし得ている。前述の如くマニホールド下部にはゲート・バルブ及びコンダクタンス・バルブを介してターボ分子ポンプが直付けされている。この真空排気装置の吸気穴902の直径は260mmで、従ってその断面積は531cm2で有るマニホールド下面及び上面には反応室への基板挿入口903が有る。本発明のLPCVD装置では300mm角の正方形型基板を反応室内に水平に設置可能としている為、この基板挿入口903の直径は460mmで有る。先の真空排気装置吸気穴902と基板挿入口903はマニホールドの強度が許される限り、出来るだけ接近している事が望ましい。
【0022】
マニホールドの上面には図1に示した様に反応室101が設置されて居り、真空排気装置吸気穴902の中心と基板挿入口903の中心を結ぶ直線上で基板挿入口の中心に対して真空排気装置吸気穴と反対方向のマニホールド上にガス導入管103が立てられている。従って、反応室でのガスは上から下へ、図9に於いては右から左へと流れる。ガス導入管と、マニホールドの吸気穴を対称に配置する事に依り、反応室内での乱流発生を最小限に止め得、半導体膜を均質・均一に堆積できる。マニホールドの反応室からの吸気はマニホールド吸気部904より取られる。マニホールド吸気部904は図1に示す様にマニホールド基板挿入口に面する側面で取られる。マニホールドの基板挿入口に面する側面の内、真空排気装置方向の半円部全体が開口されて居り、これがマニホールド吸気部904となっている。基板挿入口の半径が230mmでマニホールドの厚みが125mmで有る為、マニホールド吸気部904の開口面積は903cm2と広く、事実上マニホールドと反応室とを一体化している。これが故、マニホールドと反応室との間のコンダクタンスはポンプの排気速度等に比べてはるかに大きい。又、マニホールドの反応室側の側面全体の開口は反応室とマニホールドとの区別を無意味と化し、その違いは単に温度や材質程度で有り、気体流としては両者を区別し得ない。この様にマニホールドの最も狭い部位の断面積でも真空排気装置の吸気断面積よりも広くし、更にマニホールド吸気部を可能な限り広く取った事に依り、反応室に於ける実効排気速度を前述の如く大きくし得た。
【0023】
ターボ分子ポンプ106は運転開始後約10分間で定常回転に達する。この間ゲート・バルブ及びコンタクタンス・バルブ105を全開にしておくと、反応室を600℃に保った状態で反応室内背景圧力は1.0×10-6torrから1.5×10-6torrとなる。又ターボ分子ポンプが定常回転に達してから10分後の反応室内背景圧力は600℃で4.0×10-7torrから9.0×10-7torrの間となる。ゲート・バルブが閉じられて居り、反応室内圧力が1torr程度に維持され、ターボ分子ポンプが定常運転している状態で、ゲート・バルブを開門すると開門後10分後の反応室内背景圧力は600℃で、やはり4.0×10-7torrから9.0×10-7torrの間となる。これはターボ分子ポンプをマニホールドに直付けして、コンダクタンスを最大とした結果、反応室に於ける実効排気速度を40SCCM/mtorr以上と非常に大きくできた為、ターボ分子ポンプ定常回転到達後又はゲート・バルブ開門後僅か10分間で10-7torr代の高真空を実現し得たので有る。
【0024】
本発明のLPCVD装置に235mm□のガラス基板を17枚挿入し、真空中で堆積温度に相当する500℃から600℃程度に加熱した際の脱ガス等の漏洩速度はおよそ2×10-5torr/minから7×10-5torr/minで有る。従って真空中10分間に於ける脱ガス等による不純物気体のもたらす圧力上昇は2×10-4torrから7×10-4torr程度で有る。
【0025】
これに対して本発明のLPCVD装置では、ターボ分子ポンプ等の真空排気装置が定常運転している状態では、前述の如く1torrの真空度を10分以内に1×10-6torr以下へと圧力を下げる排気能力を有している。
【0026】
従って本発明のLPCVD装置は基板やボート治具等からの不必要で必然的に生ずる脱ガスを十分排気する事が可能となっている。基板やボート治具等から発生する脱ガスには水(H20)、酸素(02)等が含まれて居り、これらの不純物ガスは良質なシリコン膜の成長を阻害する。即ち、基板やボート治具から発生した不純物ガスはシリコン膜などの半導体膜堆積に際し、堆積の初期過程では堆積膜の核となり得る。これが故、脱ガスが十分排気されない場合、沢山の不純物ガスが基板表面に吸着し、多くの核が発生する。従って堆積された半導体膜を構成する粒径が小さくなり、半導体膜の特性を劣下させる原因となる。又、非晶質半導体膜を堆積し、後に熱処理やレーザー照射等で結晶化させる場合で有っても、これらの脱ガスに起因する多量の核の存在は結晶成長後の平均粒径サイズを小さくし、やはり半導体特性を低下させる。又堆積進行中にもこれらの脱ガス不純物は成長表面に於ける原料ガスの表面マイグレーションを抑制する。これに依り、シラン・ジシラン・ゲルマン・フォスフィン(PH3)・ジボラン(B2H6)など原料ガスが結晶エネルギー的に最も安定な位置を探し出す能力が低下し、多粒界の半導体膜や非晶質成分を多く含んだ半導佐膜を形成させるに至り、低品質な半導体膜と化してしまう。又これらの脱ガス不純物が成長半導体膜内に取り込まれると、更に半導体特性は劣下する。
【0027】
この事から良質な半導体膜を堆積するには、基板などから不可避的に発生する脱ガス不純物を十分速く排気するLPCVD装置が適当で有る。一般に真空中での脱ガス速度は10分間で10-4torr程度の圧力上昇をもたらす為、この脱ガス速度よりも大きい排気能力、即ち1torr程度の真空を10分間で10-5torr以下とする様な真空排気系を具備するLPCVD装置では脱ガス不純物を十分速く反応室外に廃棄でき、その結果良質な半導体膜が形成される。又、こうした真空排気系は真空排気装置と反応室間の不要な配管を除去し、真空排気装置がゲート・バルブやコンダクタンスバルブ等必要最小限のバルブを介して、反応室に直接設置される事に依り容易に構成されるので有る。
【0028】
図2(a)〜(e)はMIS型電界効果トランジスタを形成する薄膜半導体装置の製造工程を断面で示した図で有る。本実施例1ではノン・セルフ・アライン型スタガード構造の薄膜半導体装置を例として作成したが、これ以外にも本発明は逆スタガード構造の薄膜半導体装置やセルフ・アライン型薄膜半導体装置に関しても有効で有る。
【0029】
又、本実施例1では基板201として235mm□の石英ガラスを用いたが、半導体膜堆積温度に耐え得る基板で有るならば、基板の種類や大きさは無論問われない。更に本実施例1では半導体膜として真性シリコン膜を用いたが、これ以外にもリンやポロンなどのドナーやアクセプターなどの不純物、或いはゲルマニウムが含まれるシリコン膜や、真性ゲルマニウム膜、又はドナーやアクセブターを含むゲルマニウム膜等も可能で有る。
【0030】
まず基板201上に常圧化学気相堆積法(APCVD法)やスパッター法などで下地保護膜となる二酸化珪素膜(SiO2膜)202を形成し、次いでドナー又はアクセプターとなる不純物を含んだシリコン膜をLPCVD法にて堆積した後パターニングを行い、ソース・ドレイン領域203を形成する。(図2−a)本実施例1では不純物としてリンを選び、ホスフィン(PH3)とSiH4を混合して堆積温度600℃でLPCVD法で不純物を含んだシリコン膜を1500オングストローム堆積した。
【0031】
次に図1に示し、前述したLPCVD装置を用いてトランジスタの能動層となるチャンネル部シリコン膜204を堆積した。(図2−b)本実施例1では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度600℃でシリコン膜204を推積した。基板は表側を下向きとして、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SLMの純窒素が流れ出て居り、基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。
【0032】
基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査を2分間施した。この時の脱ガス等の漏洩速度は4.3×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の600℃迄一時間費やして昇温した。昇温の最初の10分間は反応室にガスを全く導入せず、真空中で昇温した。昇温開始後10分後の反応室到達最低背景圧力は6.8×10-7torrで有った。又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。堆積温度到達後、原料ガスであるSiH4を250SCCM流し、6分51秒間Si膜を堆積した。この時コンダクタンス・バルブの開閉を調整し反応室内圧を28.5mtorrに保った。反応中の圧力はガス種に測定値が依存しない隔膜式圧力計を用いて測定した。こうして得られたシリコン膜の膜厚は294オングストロームで有った。次にこのシリコン膜をパターニングし、トランジスタの能動層となるチャンネル部シリコン膜205を作成した。(図2−C)
その後電子サイクロトロン共鳴プラズマ化学気相堆積法(ECR−PECVD法)やAPCVD法などでゲート絶縁膜206を形成する。本実施例1ではゲート絶縁膜としてSi02膜を用い、ECR−PECVD法で1500オングストロームの膜厚に堆積した。(図2−d)引き続いてゲート電極207となる薄膜をスパッター法蒸着法或いはCVD法などで堆積する。本実施例1ではゲート電極材料としてクロム(Cr)を選択し、スパッター法で1500オングストローム堆積した。ゲート電極となる薄膜を堆積後パターニングを行い、更に層間絶縁膜208を5000オングストローム堆積した後、コンタクトホールを開け、ソース・ドレイン取り出し電極209をスパッター法などで形成し、薄膜半導体装置が完成する。(図2−e)
この様にして試作した薄膜半導体装置のトランジスタ特性の一例Vgs−Ids曲線を図3、3−aに示した。ここでIdsはソース・ドレイン電流、Vgsはゲート電圧を示し、ソース・ドレイン電圧Vdsは4Vで温度25℃の元で測定した。トランジスタチャンネル部の長さL=10μm、幅W=10μmで有った。Vds=4V,Vgs=10Vでトランジスタをオンさせたときオン電流は3.34×10-7Aで有った。又Vgs=0Vでトランジスタをオフさせたときのオフ電流は2.24×10-13Aとなり、ゲート電圧の10Vの変調に対してIdsが6桁以上変動する良好な薄膜半導体装置が得られた。この薄膜半導体装置の飽和電流領域から求めた有効電子移動度は6.1cm2/v・secで有った。
【0033】
一方図3、3−bに従来のLPCVD法で能動層チャンネル部シリコン膜を堆積し、それ以外の工程は総て本発明と同様にして薄膜半導体装置を製作した際のVgs−Ids曲線を比較のために掲げる。
【0034】
図7に示したように、従来のLPCVD装置は図1に示した本発明のLPCVD装置と比べると、反応室の大きさや形状・又基板種類・枚数・挿入位置や加熱系などは同一で有るのに対し、排気系は大きく異なっている。即ち、従来のLPCVD装置ではロータリー・ポンプ107とメカニカル・ブースター・ポンプ706に依り排気される。反応室101からの排気はマニホールド104上に立てられた排気管703を通じて取られ、更にマニホールドからは真空排気装置への排気管705に依り排気される。図10に従来技術のLPCVD装置のマニホールド部を縦(上下)方向から見た概念図を示す。従来のマニホールドはドーナツ状で有り外径が600mmでマニホールドの幅が70mm厚さが125mmで断面積は87.5cm2程度で有り、コンダクタンスは非常に小さい。又、マニホールドと反応室との間には直径40mm長さ685mmの円柱管が4本排気管703として立てられている。排気管のコンダクタンスは各々11.641/secでその結果、マニホールドと反応室の間のコンダクタンスは471/sec程度で有る。その為、反応室内温度600℃でヘリウムを74SCCM流した時、反応室内平衡圧が25.2mtorrとなる実効排気速度を有して居り、又反応室の到達最低背景圧力は10-4torr代で有った。
【0035】
こうした従来のLPCVD装置にて、堆積温度600℃、SiH4流量70SCCMで反応炉内圧力28.4mtorrで8分30秒間能動層チャンネル部となるSi膜を堆積した。堆積Si膜の膜厚は299オングストロームで有った。この様にして従来技術で作成された薄膜半導体装置のオン電流は1.1×10-7A、オフ電流は8.76×10-13飽和電流領域から求めた有効電子移動度は2.48cm2/v.secで有った。
【0036】
これらの結果を比較すると本発明の多大な優位性を窺い知らされる。即ち本発明は従来技術に対して例えば電子移動度を2倍以上大きくし、オン電流を3倍以上に増大させ、しかもオフ電流も3分の1以下に低減し、トランジスタ特性を大きく改良なし得た。この他、製造上でも本発明の堆積速度は42.9オングストローム/minと同じ温度の同じ圧力の従来接術に於ける堆積速度35.2オングストローム/minより改善されて居り、製造時間の短縮、スループット向上に役立つもので有る。更に本発明では通常ホット・ウォール型では不可能とされていた高真空で高排気能力を有するLPCVD装置を前述した特珠真空排気系に依り実現し得た。これに依り、一バッチで多数の基板加工が可能になり、同時に窮めて優れた均一性をも確保し得た。実際、本実施例1では235mmの基板17枚を同時処理したが、各基板内での膜厚のバラツキは基板の四角のコーナーから1cm以内を除いてその他の全面に渡って1%未満で有る。即ち235mm□の基板が有する552.25cm2の面積の内、各四角以外の549.11cm2の領域内での膜厚変動は2オングストローム以下で有った。又、基板間の膜厚変動も最下層に設置された一枚30オングストローム程度薄かった事を除くと残りの16枚総て非常に均一で、これら16枚の基板で最も膜厚が薄かった物で289オングストローム、最も厚かつた基板でも298オングストロームで有った。この様に高真空・高排気能力を有する本発明のLPCVD装置に依り、高品質半導体膜を窮めて均一に、しかも多量に処理する事が可能となった。
【0037】
一般にシリコン薄膜半導体装置ではチャンネル部を構成するシリコン膜を堆積する際の温度と圧力が重要なパラメーターとして知られて居り、これらが同じで有るならば同じ膜質のシリコン膜が堆積され、延ては同等のトランジスタ特性を有する薄膜半導体装置が作成されると考えられている。しかしながら本発明は温度と圧力が同じであっても排気系を改良する事に依り、堆積時間を短縮してスループットを上げ更に良質な半導体膜を堆積する事に依りトランジスタ特性を大幅に改良する事に成功した。
【0038】
(実施例2)
図2(a)〜(b)はMIS型電界効果トランジスタを形成する薄膜半導体装置の製造工程を断面で示した図で有る。本実施例2ではノン・セルフ・アライン型スタガード溝造の薄膜半導体装置を例として作成したが、これ以外にも本発明は逆スタガード構造の薄膜半導体装置やセルフ・アライン型薄膜半導体装置に関しても有効で有る。
【0039】
本実施例2では基板201として235mm□の石英ガラスを用いたが、シリコン膜堆積温度に耐え得る基板で有るならば、基板の種類や大きさは無論問われない。又、本実施例2でも半導体膜としてシリコン膜を用いたが、本実施例1と同様、ゲルマニウム(Ge)やシリコン・ゲルマニウム(SiχGel−χ:0<χ<1)やドナー・アクセブターなどを含んだ半導体膜であっても構わない。
【0040】
まず基板201上に常圧化学気相堆積法(A P C V D法)やスパッター法などで下地保護膜となる二酸化珪素膜(Sio2膜)202を形成し、次いでドナー又はアクセプターとなる不純物を含んだシリコン膜をL P C V D法にて堆積した後パターニングを行い、ソース・ドレイン額域203を形成する。(図2‐a)本実施例2では不純物としてリンを選び、ホスフイン(PH3)とSiH4を混合して堆積温度600℃でLPCVDで不純物を含んだシリコン膜を1500オングストローム堆積した。
【0041】
次に図1に示し、実施例1で詳述したLPCVD装置を用いてトランジスタの能動層となるチャンネル部シリコン膜204を堆積した。(図2‐b)本実施例2では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度600℃でシリコン膜204を堆積した。基板は表側を下向きとして、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SMLの純窒素が流れ出て居り、基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査を2分間施した。この時の脱ガス等の漏洩速度は4.0×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の600℃迄一時間費やして昇温した。昇温の最初の10分間は反応室にガスを全く導入せず、真空中で昇湿した。昇温開始後10分後の反応室到達最低背景圧力は6.5×10-7torrで有った。又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。堆積温度到達後、原料ガスであるSiH4を250SCCM流し、12分46秒間Si膜を堆積した。この間コンダクタンス・パルプは全開とし、反応炉内圧はガス種に潮定値が依存しない隔膜式圧力計を用いて測定した。原料SiH4を反応室に導入後最初の3分16秒間は反応室内平衡圧力は2.55mtorrで有った。この圧力測定値は反応室の温度を25℃としてSiH4を250SCCM流した時に得られる反応室内平衡圧力と同値である。又この条件で堆積時間t(min)と堆積膜厚T(オングストローム)の関係は
T(オングストローム)=-87.9(オングストローム)+30.4(オングストローム/min)×t(min)
の関係にある事から、原料ガスを反応室に導入後最初の三分間程度は原料ガスの熱分解は生じていないと推定される。その後反応室内圧力は徐々に上昇し、原料ガス導入後11分16秒後には2.94mtorrとなり、以後堆積が終了する原料ガス導入後12分46秒迄この圧力値を維持した。反応室内の圧力上昇は原料シランの反応率が変わり、生成水素量が増大した結果で有る。従ってこの圧力変化を考慮すると、堆積終了直前の原料シランの反応率は16.7%で、これに基づいてシラン分圧は2.10mtorrと推定される。
【0042】
一方、本実施例2では235m□の基板を反応室に17枚挿入した為、反応室内総面積は44040cm2となる。反応室内全域で同一の堆積速度を仮定し、堆積速度と反応室内総面積より原料シランの反応率及びシラン分圧を見積もるとそれぞれ10.0%及び2.52mtorrとなった。こうして得られたシリコン膜の膜厚は301オングストロームで有った。次にこのシリコン膜をパターニングし、トランジスタの能動層となるチャンネル部シリコン膜205を作成した。(図2‐C)
その後ECR-PECVD法やAPCVD法などでゲート絶縁膜206を形成する。本実施例2ではゲート絶縁膜としてSiO2膜を用い、ECR-PECVD法で1500オングストロームの膜厚に堆積した。(図2-d)引き続いてゲート電極207となる薄膜をスパッター法蒸着法或いはC V D法などで堆積する。本実施例2ではゲート電極材料としてクロム(Cr)を選択し、スパッター法で1500オングストローム堆積した。ゲート電極となる薄膜を堆積後パターニングを行い、更に層間絶縁膜208を5000オングストローム堆積した後、コンタクトホールを開け、ソース・ドレイン取り出し電極209をスパッター法などで形成し、薄膜半導体装置が完成する。(図2‐e)
この様にして試作した薄膜半導体装置のトランジスタ特性の一例Vgs‐Ids曲線を図4、4−aに示した。ここでIdsはソース・ドレイン電流、Vgsはゲート電圧を示し、ソース・ドレイン電圧Vdsは4Vで温度25℃の元で測定した。トランジスタチャンネル部の長さL=10μm、幅W=10μmで有った。Vds=4V,Vgs=10Vでトランジスタをオンさせたときオン電流は95%の信頼係数でION=(2.40+0.08、-0.07)×10-6Aで有った。又、Vgs=0Vでトランジスタをオフさせた時のオフ電流はIOFF=(1.82+0.64、-0.47)×10-13Aとなり、ゲート電圧の10Vの変調に対してIdsが7桁以上変動する良好な薄膜半導体装置が得られた。この薄膜半導体装置の飽和電流領域から求めた有効電子移動度は10.84±0.29cm2/V・secで有った。この様に本発明に依り良好な薄膜半導体装置が得られた。
【0043】
一方図4、4−bにコンダクタンスバルブを全閉として反応室に於ける実効排気速度を落として能動層チャンネル部シリコン膜を堆積し、それ以外の工程は総て本発明と同様にして薄膜半導体装置を製作した際のVgs−Ids曲線を比較のために掲げる。このコンダクタンスパルプを全閉にした際、反応室に窒素を100SCCM、200SCCM、300SCCM流した時の反応室内平衡圧力は炉内温度600℃に於いて、それぞれ1.2×10-2torr、2.6×10-2torr、4.0×10-2torrとなり、対応する実効排気速度は各々、8.33SCCM/mtorr、7.69SCCM/mtorr、7.50SCCM/mtorrとなった。この実効排気速度は従来のLPCVD装置の実効排気速度より約2倍程度大きく、従来接術を代表していないが、他の製造条件を総て本発明と同様にして比較するために実効排気速度の小さい例として薄膜半導体装置を作製した。
【0044】
こうしたコンダクタンス・バルブ全開とした本発明のLPCVD装置を用いてトランジスタの能動層となるチャンネル部シリコン膜を堆積した。この比較例では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度600℃でシリコン膜204を堆積した。基板は表側を下向きとして、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SLMの純窒素が流れ出て居り基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査2分間施した。この時の脱ガス等の漏洩速度は4.3×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の600℃まで1時間費やして昇温した。昇温の最初10分間は反応室にガスを全く導入せず、真空中で昇湿した。昇温開始後10分後の反応室到達最低背景圧力は6.8×10-7torrで有った。又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。堆積温度到達後、原料ガスであるSiH4を250SCCM流し、6分51秒間Si膜を堆積した。このときコンダクタンス・バルプは全閉とし、反応炉内圧は28.5mtorrとなった。反応中の圧力はガス種に判定値が依存しない隔膜式圧力計を用いて測定した。こうして得られたシリコン膜の膜厚は294オングストロームで有った。これ以外は実施例2の本発明と全く同一の製造工程で薄膜半導体装置を試作した。
【0045】
この様にして作成された比較例の薄膜半導体装置のオン電流はION=(3.34+0.11、-0.12)×10-7A、オフ電流はI OFF=(2.24+0.79、-0.58)×10-13Aで飽和電流領域から求めた有効電子移動度は、6.12±0.29cm2/v・secで有った。この比較例から分かる様に、実効排気速度を10SCCM/mtorr以上としLPCVD装置にてチャンネル部シリコン膜を形成するという本発明により、従来の実効排気速度が10SCCM/mtorr以下で有ったL P C V D装置で薄膜半導体装置のチャンネル部シリコン膜を形成する技術に比較して、オン電流を7倍以上増大させ、且つオフ電流も低く押さえる事が出来、その結果オン・オフ比を従来に比して10倍以上増大させる事に成功した。
【0046】
一般にシリコン薄膜半導体装置ではチャンネル部を構成するシリコン膜を堆積する際の温度と圧力が重要なパラメーターとして知られている。例えば堆積温度600℃でシリコン膜を堆積する場合、従来のLPCVD装置ではシラン分庄が3mtorr以下では実効排気速度が小さい為、堆積速度は8オングストローム/min程度と遅く、加えて半導体特性も劣悪で有った。しかるに本発明に依ると、実効排気速度を大きくする事に依り、堆積速度を増大させ、それに依り堆積時間を短縮してなお、低圧堆積に依りトランジスタ特性を大幅に改良する事に成功した。
【0047】
(実施例3)
図2(a)〜(e)はMIS型電界効果トランジスタを形成する薄膜半導体装置の製造工程を断面で示した図で有る。本実施例3ではノン・セルフ・アライン型スタガード構造の薄膜半導体装置を例として作成したが、これ以外にも本発明は逆スタガード構造の薄膜半導体装置やセルフ・アライン型薄膜半導体装置に関しても有効で有る。
【0048】
本実施例3では基板201として235m□の石英ガラスを用いたが、半導体膜堆積温度に耐え得る基板で有るならば、基板の種類や大きさは無論問われない。更に本実施例3では半導体膜として真性シリコン膜を用いたが、半導体膜としてドナーやアクセプターを含むシリコン膜や、ゲルマニウムを含むSiχGel-χ(0<χ<1)或いはSiGex膜で有っても構わない。まず基板201上に常圧化学気相堆積法(APCVD法)やスパッター法などで下地保護膜となる二酸化珪素膜(SiO2膜)202を形成し、次いでドナー又はアクセプターとなる不純物を含んだシリコン膜をLPCVD法にて堆積した後パターニングを行い、ソース・ドレイン領域203を形成する。(図2−a)本実施例3では不純物としてリンを選び、ホスフィン(PH3)とSiH4を混合して堆積温度600℃でLPCVD法で不純物を含んだシリコン膜を1500オングストローム堆積した。
【0049】
次に図1に示し、実施例1で詳述した本発明のLPCVD装置を用いてトランジスタの能動層となるチャンネル部シリコン膜204を堆積した。(図2−b)本実施例3では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度600℃でシリコン膜204を堆積した。基板は表側を下向きとして、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SLMの純窒素が流れ出て居り、基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査を2分間施した。この時の脱ガス等の漏洩速度は3.0×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の600℃迄一時間費やして昇温した。
【0050】
昇温の最初の10分間は反応室にガスを全く導入せず、真空中で昇温した。昇温開始後10分後の反応室到達最低背景圧力は5.2×107torrで有った又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。堆積温度到達後原料ガスであるSiH4を50SCCM流し、26分04秒間Si膜を堆積した。
【0051】
この間コンダクタンス・バルブは全開とし、反応室内圧力はガス種に測定値が依存しない隔膜式圧力計を用いて測定した。原料SiH4を反応室に導入後最初の13分30秒間は反応室内平衡圧力は0.69mtorrで有った。この圧力測定値は反応室の温度を25℃としてSiH4を50SCCM流した時に得られる反応室内平衡圧力の0.67mtorrとほぼ同値である。又この条件で堆積時間t(min)と堆積膜厚T(オングストローム)の関係はT(オングストローム)=-227(オングストローム)+20.6(オングストローム/min)×t(min)の関係にある事から、原料ガスを反応室に導入後最初の12分間程度は原料ガスの熱分解は生じていないと推定される。その後反応室内圧力は徐々に上昇し、堆積が終了する直前の原料ガス導入後26分00秒後には0.86mtorrとなった。
反応室内の圧力上昇は原料シランの反応率が変わり、生成水素量が増大した結果で有る。
【0052】
従ってこの圧力変化を考慮すると、堆積終了直前の原料シランの反応率は31.5%で、これに基づいてシラン分圧は0.45mtorr推定される。一方、本実施例3では235mm□の基板を反応室に17枚挿入した為、反応室内総面積は44040cm2となる。反応室内全域で同一の堆積速度を仮定し、堆積速度と反応室内総面積より原料シランの反応率及びシラン分圧を見積もるとそれぞれ34.0%及び0.43mtorrとなった。こうして得られたシリコン膜の膜厚は326オングストロームで有った。次にこのシリコン膜をパターニングし、トランジスタの能動層となるチャンネル部シリコン膜205を作成した。(図2−C)
その後ECR‐PECVD法やAPCVD法などでゲート絶縁膜206を形成する。本実施例3ではゲート絶縁膜としてSi02膜を用い、ECR−PECVD法で1500オングストロームの膜厚に堆積した。(図2−d)引き続いてゲート電極207となる薄膜をスパッター法蒸着法或いはCVD法などで堆積する。本実施例3ではゲート電極材料としてクロム(Cr)を選択し、スパッター法で1500オングストローム堆積した。ゲート電極となる薄膜を堆積後パターニングを行い、更に層間絶縁膜208を5000オングストローム堆積した後、コンタクトホールを開け、ソース・ドレイン取り出し電極209をスパッター法などで形成し、薄膜半導体装置が完成する。(図2−e)
この様にして試作した薄膜半導体装置のトランジスタ特性を測定したところ、ソース・ドレイン電圧Vds=4V,ゲート電圧Vgs=10Vでトランジスタをオンさせた時のソース・ドレイン電流Idsをオン電流IONと定義して、95%の信頼係数でION=(3.63+0.12、−0.11)×10-6Aで有った。ここで測定は温度25℃の元で、チャンネル部の長さL=10μm、幅W=10μmのトランジスタに対してなされた。又、飽和電流領域から求めた有効電子移動度(J.Levisonetal.j,Appl,Phys.53,1193’82)は、μ=12.91±0.29cm2/v.secで有った。この様に本発明に依り良好な薄膜体装置が得られた。
【0053】
(実施例4)
チャンネル部シリコン膜を堆積する工程を除いてその他の工程は全て実施例3と同じ工程で薄膜半導体装置を作成した。本実施例4ではチャンネル部シリコン膜を堆積するのに、実施例1で詳述したLPCVD装置を用い、堆積温度600℃で、希釈ガスは用いず、シラン流量100SCCMから250SCCMまで、50SCCMおきに設定し、チャンネル部シリコン膜の膜厚が300オングストローム程度になるように堆積して薄膜半導体装置を作成した。この際、LPCVD装置のコンダクタンス・バルブは全開とした為、シラン流量の変化に応じて、反応室内圧力及び堆積速度、シラン反応率、シラン分圧は変化する。各試料に於けるこれらの数値を表1に揚げる。こうして得られた薄導体装置のトランジスタ特性の一例として実施例3で定義したオン電流と有効移動度を表1及び図5、図6に示す。これらの表及び図でエラー・バーは95%の信頼係数に於ける区間推定値を示している。これらの表及び図からシラン分圧が1mtorr以下となるか、または反応室内圧力が2mtorr以下としたチャンネル部シリコン膜を堆積すると、半導体膜の膜質が大きく向上する為対応するトランジスタ特性が明らかに著しく向上する事が分かる。
【0054】
所で高生産性という観点からすると、1バッチで出来る限り多数の基板を処理する必要が生ずる。これを満たすには、原料ガスで有るシランの反応率を低く押さえ、基板間でのシラン分圧の差をなるべく小さくして、基板間の膜質を均一化せねばならない。即ち高品質膜と高生産性を両立させるには、少なくとも原料シランガスを100SCCM程度以上流して、基板間の均一性を保つ一方で、なお且つ高品質膜を堆積する為に反応炉内圧力が2mtorr以下となるのが必然と化す。実施例1で詳述した如く、本発明の真空排気装置は窒素に対して22001/secの排気速度を有して居るが故、シラン流量が100SCCMの時、反応室内最高圧力は1.49mtorrとなり、この両条件を矛盾無く満たしている。一般にはこれら二つの要請を満足させるには、少なくとも真空排気装置の排気速度は16501/sec以上でなければならない。
【0055】
【表1】

Figure 0003786580
【0056】
(実施例5)
直径3インチの溶融石英ガラス基板上にSio2膜を堆積した後、シリコン膜を形成してその物性を調べた。まず、石英基板を沸騰している濃度60%の硝酸中に5分間浸して基板表面の汚れを取り、更に1.67%弗化水素酸水溶液に20秒間浸して基板表面の不定形酸化膜を除去した後、直ちにAPCVDで下地保護膜となるSi02を2000オングストロームの膜厚に堆積した。
【0057】
次に図1に示し、実施例1で詳述した本発明のLPCVD装置を用いてシリコン膜を堆積した。本実施例5では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度555℃でシリコン膜を堆積した。直径3インチの石英基板はダミー基板として設置されている17枚の235mm□基板の内で中央に位置する下から九度目の基板上に表側を上向きとして置かれ、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SLMの純窒素が流れ出て居り、基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査を2分間施した。この時の脱ガス等の漏洩速度は4.45×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の555℃迄一時間費やして昇湿した。昇温の最初の10分間は反応室にガスを全く導入せず、真空中で昇湿した。昇温開始後10分後の反応室到達最低背景圧力は6.0×10-7torrで有った。又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。
【0058】
この時の反応室内平衡圧力は3.0×10-3torrで有った。堆積温度到達後、原料ガスであるSiH4を100SCCM流し、15時間44分00秒間Si膜を堆積した。この間コンダクタンス・バルブは全開とし、反応室内圧力はガス種に測定値が依存しない隔膜式圧力計を用いて測定した。原料SiH4を反応室に導入後最初の17分30秒間は反応室内平衡圧力は1.21mtorrで有った。この圧力測定値は反応室の温度を25℃としてSiH4を100SCCM流した時に得られる反応室内平衡圧力と同値である。又この条件で堆積時間t(min)と堆積膜厚T(オングストローム)の関係は堆積膜厚が1000オングストローム未満の膜に対して
T(オングストローム)=−102(オングストローム)+5.63(オングストローム/min)×t(min)
の関係にある事から、原料ガスを反応室に導入後最初の18分間程度は原料ガスの熱分解は生じていないと推定される。その後反応室内圧力は徐々に上昇し、堆積が終了する直前の原料ガス導入後15時間40分後には1.26mtorrとなった。
【0059】
反応室内の圧力上昇は原料シランの反応率が変わり、生成水素量が増大した結果で有る。
【0060】
従ってこの圧力変化を考慮すると、堆積終了直前の原料シランの反応率は3.4%で、これに基づいてシラン分圧は1.17mtorrと推定される。一方、本実施例5では235mm□のダミー基板を反応室に17枚挿入した為、反応室内総面積は44040cm2となる。反応室内全域で同一の堆積速度を仮定し、堆積速度と反応室内総面積より原料シランの反応率及びシラン分圧を見積もるとそれぞれ4.6%及び1.15mtorrとなった。こうして得られたシリコン膜の膜厚は5363オングストロームで有った。
【0061】
次にこうして得られたシリコン膜の結晶性をX線回折法とラマン分光法に依って調べた。X線画折法では回折角2θ(θはブラック角)が28.47度、47.44度、56.18度、69.21度に強いピークが観測された。これらのピークは単結晶シリコン粉末の(111)、(220)、(311)、(400)回折に相当し、本実施例5で得られたシリコン膜が多結晶品質で有る事を明示している。又各ピーク強度は其々順に任意スケールで5118、16760、2787、498で、本実施例5で得られたシリコン膜は(110)面方向に優先配向した多結晶シリコンと認められる。ラマン分光法は顕微サンプル室に於いて後方散乱配置で測定を行った。
【0062】
励起レーザー光に依るアニール及び試料表面の温度上昇によるピークシフト及び半値幅の広がりを避ける為、レーザー出力を10mWと小さくし、同時にビーム径を顕微測定に於ける最大の10μmとした。測定は25℃の元で行われ波数走査領域は600cm-1から100cm-1で有った。
【0063】
本実施例5で得られたシリコン膜は、こうしたラマン分光測定の結果、波数519.50cm-1に半値幅4.27cm-1の鋭いピークを持つ事が認められ、明らかに結晶性シリコン膜で有ると証明された。又、結晶シリコンに対応する光学モード振動数520cm-1付近のラマン散乱積分確度と、アモルファス・シリコンに対応する振動数130cm-1付近の音響横波モード、290cm-1付近の音響縦波モード405cm-1付近の光学縦波モードと480cm-1付近に現れる光学横波モードのアモルファス・シリコンの散乱積分強度の和との相対比から結晶化度を求めた所、(Appl,Phys,Lett,40(6),534(1982))本実施例5に依り得られたシリコン膜は96.6%との高い結晶化度を有すると測定された。
但しここで散乱積分強度補正係数Kの値としては0.88を採用した。
【0064】
こうした物性測定の結果、従来堆積温度580℃以上でなければ決して堆積する事の出来なかった結晶質シリコン膜を、本発明に依るLPCVD装置を用いる事で55℃程度以下という窮めて低温で形成する事が初めて可能となった。
【0065】
次に本実施例5で得られた真性シリコン膜に燐を添加して電気伝導体を作成した。本実施例5ではバケットタイプの質量非分離型のイオン注入装置を用いて不純物イオンの添加を施した。原料ガスとして水素中に希釈された濃度5%のホスフィンを用い、加速電圧110kVで1.6×10161/cm2の濃度に打ち込んだ。次にこの基板を窒素雰囲気下で400℃に保たれている炉に挿入して熱処理を施した。熱処理時間は3時間で有った。こうして得られたシリコン膜のシート抵抗値は185Ω/□という窮めて低い値が得られた。従来のLPCVD法で堆積温度580℃以下で作成したシリコン膜では、燐などの不純物イオンを添加しても600℃以上の温度で数十時間の熱処理を施さぬ限り、抵抗値は無限大で、事実上全く電気は流れなかった。しかるに本発明に依るLPCVD装置で形成した本発明のシリコン膜に本発明に依るイオン注入法を用いた場合では斯様に555℃という低温堆積で尚且つ400℃という低温熱処理で充分低い電気抵抗値を示し得た。従って本発明のシリコン膜は薄膜半導体装置や集積回路(LSI)、又は電荷結合装置(CCD)のゲート電極や配線など、あらゆる電子装置などに用いるシリコン膜を555℃程度以下の低温で形成出来、又こうした低温でも電気伝導体を作成し得る。これに依り素子を高温熱工程による劣化から保護する事が可能となったり、他素子、配線などを耐熱性の低い物質で形成する事が可能になり、これら電子装置の高性能化や低価格化をもたらし得る。
【0066】
(実施例6)
図2(a)〜(e)はMIS型電界効果トランジスタを形成する薄膜半導体装置の製造工程を断面で示した図で有る。本実施例6ではノン・セルフ・アライン型スタガード溝造の薄膜半導体装置を例として作成したが、これ以外にも本発明は逆スタガード構造の薄膜半導体装着やセルフ・アライン型薄膜半導体装置に関しても有効で有る。
【0067】
本案施例6では基板201として235mm□の石英ガラスを用いたが、シリコン膜堆積温度に耐え得る基板で有るならば、基板の種類や大きさは無論問われない。まず基板201上に常圧化学気相堆積法(APCVD法)やスパッター法などで下地保護膜となる二酸化珪素膜(Si02膜)202を形成し、次いでドナー又はアクセブターとなる不純物を含んだシリコン膜を形成後バターニングを行い、ソース・ドレイン領域203を作成する。(図2−a)
本実施例6では、図1に示し実施例1で詳述した本発明のLPCVD装置を用いて、堆積温度555℃で真性シリコン膜を1500オングストローム程度堆積した後、不純物元素として燐を選び、イオン注入法で燐を打ち込み、不純物を含んだシリコン膜を形成した。後にソース及びドレイン領域と化す真性シリコン膜は本発明のLPCVD装置にて、原料ガスで有るSiH4を100SCCM流し堆積温度555℃で4時間53分04秒間堆積した。反応室内の圧力変化や堆積膜厚T(オングストローム)と堆積時間t(min)の関係は実施例5で示された関係と同一で有った。即ち、原料ガスのSiH4を555℃の反応室に導入した直後の反応室内圧力は1.21mtorrで有り、堆積が終了する直前の原料ガス導入後4時間52分後には1.27mtorrとなった。こうして得られた真性シリコン膜の膜厚は、1571オングストロームで有った。引き続いてこの真性シリコン膜にバケット型質量非分離型のイオン注入装置を用いて燐元素を添加した。原料ガスとしては水素中に希釈された濃度5%のホスフィンを用い、高周波出力38W、加速電圧110kVで3×10151/cm2の濃度に打ち込んだ。その後室素雰囲気下400℃で1時間30分熱処理を施した所、こうして得られた不純物を含んだシリコン膜のシート抵抗値は936Ω/□で有った。
【0068】
次に図1に示し、実施例1で詳述した本発明のLPCVD装置を用いてトランジスタの能動層となるチャンネル部シリコン膜204を堆積した。(図2−b)本実施例6では原料ガスとしてSiH4を用い、希釈ガスを全く用いず、堆積温度555℃でシリコン膜204を堆積した。基板は表側を下向きとして、400℃に保たれた反応室101に挿入された。この際ガス導入管103からは30SLMの純窒素が流れ出て居り、基板挿入時に空気が反応室内に流れ込む事を最小限に止めている。基板挿入後、ターボ分子ポンプの運転を開始し、定常回転に達した後、漏洩検査を2分間施した。この時の脱ガス等の漏洩速度は4.85×10-5torr/minで有った。その後挿入温度の400℃から堆積温度の555℃迄一時間費やして昇温した。昇温の最初の10分間は反応室にガスを全く導入せず、真空中で昇温した。昇温開始後10分後の反応室到達最低背景圧力は6.4×10-7torrで有った。又残り50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。
【0069】
堆積温度到達後、原料ガスであるSiH4を100 SCCM流し、58分23秒間Si膜を堆積した。この間コンダクタンス・バルブは全開とし、反応室内圧力はガス種に測定値が依存しない隔膜式圧力計を用いて滑走した。原料SiH4を反応室に導入後最初の17分30秒間は反応室内平衡圧力は1.21mtorrで有った。堆積時間t(min)と堆積膜厚T(オングストローム)の関係は実施例5と同じで有る。堆積が終了する直前の原料ガス導入後58分00秒後には反応室内平衡圧力は1.27mtorrで有った。実施例5で示した様に反応室内全域で同一の堆積速度を仮定し、堆積速度と反応室内総面積より原料シランの反応率及びシラン分圧を見積もるとそれぞれ4.6%及び1.15mtorrとなる。こうして得られたシリコン膜の膜厚は199オングストロームで有った。次にこのシリコン膜をバターニングし、トランジスタの能動層となるチャンネル部シリコン膜205を作成した。(図2−C)
その後ECR−PECVD法やAPCVD法などでゲート絶縁膜206を形成する。本実施例6ではゲート絶縁膜としてSiO2膜を用い、ECR−PECVD法で1500オングストロームの膜厚に堆積した。(図2−d)引き続いてゲート電極207となる薄膜をスパッター法蒸着法或いはCVD法などで堆積する。本実施例6ではゲート電極材料としてクロム(Cr)を選択し、スパッター法で1500オングストローム堆積した。ゲート電極となる薄膜を堆積後パターニングを行い、更に層間絶縁膜208を500オングストローム堆積した後、コンタクトホールを開け、ソース・ドレイン取り出し電極209をスパッター法などで形成し、薄膜半導体装置が完成する。(図2‐e)
この様にして試作した薄膜半導体装置のトランジスタ特性を測定したところ、ソース・ドレイン電圧Vds=4V,ゲート電圧Vgs=10Vでトランジスタをオンさせた時のソース・ドレイン電流Idsをオン電流IONと定義して、95%の信頼係数でION=(1.45+0.08、−0.07)×10-6Aで有った。又、Vds=4V、Vgs=0Vでトランジスタをオフさせた時のオフ電流はIOFF=(0.079+0.030、−0.022)×10-12Aで有った。ここで測定は温度25℃の元で、チャンネル部の長さL=10μm、幅W=10μmのトランジスタに対してなされた。飽和電流額域から求めた有効電子移動度(J.Levinsonetal.J,APPl,Phys.53,1193’82)は、μ=9.30±0.39cm2/v.secで有った。
【0070】
この様に本発明に依り、高移動度を有し、ゲート電圧の10Vの変調に対してIdsが7桁以上も変動する窮めて優良な薄膜半導体装置を工程最高温度を555℃以下で、しかも工程最高温度に維持されている期間を数時間以内とする低温工程で初めて現実化した。これは本発明が単に半導体膜と薄膜半導体装置を高性能化するのみならず、同時にかくたる高品質半導体膜や高性能薄膜半導体装置を従来全く製造不可能と考えられていた低温工程で多量にしかも安定的に生産する手法をも初めて提供した事を意味して居る。
【0071】
(実施例7)
図8(a)〜(d)はMIS型電界効果トランジスタを形成する薄膜半導体装置の製造工程を断面で示した図で有る。
【0072】
本実施例7では基板801として235mm□の石英ガラスを用いたが、555℃3時間程度の熱環境に耐え得る基板であるならば、その種類や大きさは問われない。
【0073】
まず基板801上に常圧化学気相堆積法(APCVD法)やスパッター法などで下地保護膜となる二酸化珪素膜(SiO2膜)802を形成する。本実施例7ではAPCVD法で基板温度300℃、堆積速度3.9オングストローム/secで2000オングストロームの膜厚にSiO2膜を堆積して下地保護膜802を形成した。
【0074】
次に図1に示し、実施例1で詳述した本発明のLPCVD装置を用いて半導体膜803を形成する。本実施例7では半導体膜として真性シリコン膜を用いたが、シリコン・ゲルマニウム膜やガリウム・ヒ素膜等他の半導体膜も可能で有る。
【0075】
又、半導体膜はP型又はn型などとなる不純物を1×10191/cm3程度以下の微量を含んでいても構わない。本実施例7では堆積温度555℃でシラン流量が100SCCMで2時間5分26秒シリコン膜を推積した。堆積に際し、基板挿入温度の400℃から堆積温度の555℃まで1時間かけて昇温したが、最初の10分間は反応室にガスを全く導入せず、真空中で昇温した。昇温開始後10分後の反応室到達最低背景圧力は6.1×10-7torrで有った。又、残りの50分間の昇温期間には純度99.9999%以上の窒素ガスを300SCCM流し続けた。この時の反応室内平衡圧力は3.0×10-3torrで有った。又、堆積終了直前の原料ガス導入後2時間5分に於ける反応室内平衡圧力は1.26mtorrで有った。こうして得られた半導体膜の膜厚は588オングストロームで有った。次にこの半導体膜をパターニングして後にトランジスタとなる半導体膜803を形成した(図8 a)。
【0076】
その後ECR−PECVD法やAPCVD法などでゲート絶縁膜804を形成する。本実施例7ではゲート絶縁膜としてSiO2膜を用い、ECR−PECVD法で基板温度を100℃として1500オングストロームの膜厚に堆積した。
【0077】
次に後にゲート電極と化する導伝膜を形成し、更にキャップ層となる膜を形成する。キャップ層は後にゲート電極をマスクとしてドナー又はアクセプターとなる不純物を半導体膜に打ち込む際に、これら不純物元素がチャンネル部に達せぬ様に設けた。従ってゲート電極の膜厚が厚い等、ゲート電極に不純物添加に対する阻止能力が有ればこのキャップ層は必要とされない。本実施例7ではゲート電極805に2000オングストロームの膜厚のインジウム・錫酸化物(ITO)を選び、又キャップ層806には3500オングストロームのSiO2膜を用いた。ゲート電極805はスパッター法で基板温度150℃で形成し、キャップ層806はAPCVD法でSiO2膜を基板温度300℃にて堆積した後、それぞれこの膜をパターニングして、ゲート電極805及びキャップ層806を形成した(図8b)。
ゲート電極材料にはこの他、クロムやタングステン・モリブデン等の金属材料やモリブデン・シリサイドやタングステンシリサイドなどのシリサイド膜も可能で有る。
【0078】
又、これらの膜が3500オングストローム程度以上の膜厚を有する時は前述したキャップ層は必要とされない。又、純アルミニウムを8000オングストローム程度スパッター法等でゲート電極として形成するのも効果的で有る。この場合もやはりキャップ層は必要とされない。キャップ層としては本実施例7で示したSiO2膜の他に、窒化シリコンやSiON膜、酸化金属膜等も可能で有る。
【0079】
次にパケットタイプの質量非分離型のイオン注入装置を用いて、ドナー又はアクセプターとなる不純物元素をゲート電極805をマスクとして半導体膜803に打ち込む。この手法により半導体膜はソース・ドレイン領域808及びチャンネル領域807がゲート電極805に対して自己整合的に出来上がる(図8c)。
【0080】
本実施例7ではN型MOSの作成を試みた為、原料ガスとして水素中に希釈された濃度5%のホスフィン(PH3)を用いたが、不純物元素の水素化物を水素で希釈した物で有るならば、これに限られない。例えばP型MOSの作成には水素中に希釈されたジボラン(B2H6)等も可能で有る。本実施例7では13.56MHzで出力50Wの高周波にて原将ガスをプラズマ化し、加速電圧110kvにて、PH3 +、PH2 +、PH+、H2 +、H+、等のすべてのイオン種を総イオン数で2×10161/cm2半導体膜に打ち込んだ。その後350℃2時間の窒素アニールを施し、ソース・ドレイン領域808が完成する。窒素アニール後のソース・ドレイン領域のシート抵抗値は17.01kΩ/□で有った。
【0081】
その後、層間絶縁膜809をAPCVD法で300℃にて5000オングストローム程度堆積した後、コンタクト・ホールを開穴し、ソース・ドレイン取り出し電極810を形成して薄膜半導体装置が完成する。本実施例7ではアルミニウムを基板温度180℃にてスパッター法で8000オングストローム堆積した後パターニングを行う事によりソース・ドレイン取り出し電極810を形成した。
【0082】
この様にして試作した薄膜半導体装置のトランジスタ特性を測定したところ、ソース・ドレイン電圧Vds=4v、ゲート電圧Vgs=10vでトランジスタをオンさせた時のソース・ドレイン電流I d sをオン電流と定義して、チャンネル長及び幅が共に10μmのトランジスタに対して室温でI ON=5.62×10 7Aが得られた。又このトランジスタの飽和電流領域から求めた有効電子移動度は95%の信頼係数でμ=6.87±0.35cm2/v・secで有った。更にVds=4V、Vgs=0Vでトランジスタをオフさせた時のオフ電流は同トランジスタで8.48×10 13オングストロームで有った。この様に本発明により工程最高温度が555℃で、その温度に維持されている期間が2時間程度で有るという短時間低温工程で大面積に均一に且つ多くの優れた自己整合型薄膜半導体装置を作成する事に成功した。これは本発明に依り、555℃で良質な半導体膜803を形成後の工程最高温度を不純物活性化の350℃に依る窒素アニールに押さえ、バラツキや工程変動、スループット低下の一因となる水素化処理やレーザー照射といった工程を経る事なく薄膜半導体装置を完成させた事に依る。又本発明では555℃数時間が最も厳しい熱環境で有る為、比較的安価なガラスを基板として用いても、基板の伸縮、ゆがみ等が問題とならず、高精細、高密度の薄膜半導体装置を安価で大面積に作成する事も可能となった。
【0083】
(実施例8)
実施例1から実施例7に渡って詳述して来た様に、反応室に於ける実効排気速度が大きい程、良質な半導体膜をより低温で堆積し得る。斯くして安価な大面積基板上に均一で優れた薄膜半導体装置を安定的に製造できるに至る。
【0084】
図11はこの様な優れた機能を有する本発明に依る縦型減圧化学気相堆積装置(縦型LPCVD装置)の概念図で有る。LPCVD装置は反応室101の中央部付近に基板102を水平に設置し、シランやジシラン、ゲルマン等の原料ガスの熱分解を利用してシリコン膜等の半導体膜を堆積する。これらのガス及び窒素・水素・アルゴン等の希釈ガスは反応室下部に設置されたガス導入口1103より反応室に導入される。基板102は円板を数枚組み合わせたターン・テーブル109上に設置され、半導体膜堆積中はこのターン・テーブルと基板は一分間に数回転して居る。反応室に入った原料ガスはターン・テーブルと反応室の内壁の間等を流れた後、基板に達し、更に反応室上部に設置されたマニホールド104或いは真空ポンプ等に依り排気される。本実施例8ではマニホールドや真空ポンプは実施例1に詳述した本発明のLPCVD装置と同じマニホールドや真空ポンプを用いたが、例えば後述する様にマニホールドは省略されても構わぬし、ポンプの組み合わせもこれ以外にも可能で有る。反応室の外側には数ゾーンに分かれたヒーター108が設置されて居り、これらの各ゾーンの温度を独立に調整する事に依り、反応室内に所望の温度領域を形成し得る。例えばヒーター108を5ゾーンに分け一番下のヒーターから順次ヒーター温度を高くして、下側の基板から上側へと温度が一定の割合で高くなる様に反応室内に温度勾配をつける事も可能で有る。又、むろん基板間の温度が一定で有る均熱帯の設定も可能で有る。
【0085】
本実施例8で示した縦型LPCVD装置ではガスは下方から上方へと流れる。その為、厳密に云うと反応室内に於ける圧力は上方がより低くなっている。前述の如く良質な半導体膜を得るには出来る限り高排気速度で且つ低い圧力で堆積する事が好ましい。図11に示すLPCVD装置では上方より排気を取るが故、ターン・テーブルと反応室璧とのコンダクタンスが問題にならず、マニホールドの反応室吸気穴からの排気速度が、そのまま基板の被る排気速度となり、更に高真空に依る半導体膜の形成が可能となる。又本発明では反応室の上面全体で排気を取る為、反応室内の対流の発生を大幅に低減し、基板間で更に均質な膜の形成が可能となる。加えて、半導体膜の堆積にはシラン(SiH4)、ジクロール、シラン(SiH2Cl2)等、一般に反応ガスの分子量の方が水素(H2)や塩化水素(HCl)等の生成ガスの分子量よりも大きいのが普通で有る。従って、図7に示す従来のLPCVDD装置の様に排気管を立てる方法では反応室上部に生成ガスが滞留し、堆積時間の経過と共に反応室内の反応ガスと生成ガスの比が変化する。これに対して本発明の図11に示すLPCVDでは生成ガスの滞留をなくし、堆積の初期から最後まで堆積状態を意のままに調整出来る。更に水素等の分子量の小さいガスは一般にポンプの排気速度が劣り、これらのガスが反応室内に滞留すると、結果として基板の被る排気速度も落ちるが、本発明のLPCVD装置では上方より排気を取る為、これらの軽いガスを効果的に排気し得、それが故基板自身が実際に被る排気速度を最大限大きく出来る。この様に本発明のLPCVD装置に依り、より高品質の半導体膜を555℃程度以下の低温で堆積出来、しかも堆積速度を増す事も可能となった。
【0086】
(実施例9)
図12は本発明に依る縦型減圧化学気相堆積装置(縦型LPCVD装置)の概念図である。
【0087】
実施例8で詳述した如く、高品質半導体膜をより効果的に形成するには高排気能力を有する縦型LPCVD装置にて、原料ガスを反応室下部より導入し、排気は反応室上面で広く取る事が望ましい。図12に示す本発明のLPCVD装置はマニホールドを有さず、反応室上面に取り付けられたゲート・バルブ及び、コンダクタンス・バルブ105を介して磁気軸受型ターボ分子ポンプ1206(例えば株式会社大阪真空機器製作所製、磁気軸受型複合分子ポンプTG2203MVなど)が直接反応室に設置されている。磁気軸受型ターボ分子ポンプを用いる事に依りターボ分子ポンプを倒立させて使用する事が出来、これに依り、均一な堆積を容易にする下方から上方へのガス流と、軽分子の高速排気を可能にし、しかもマニホールドやターン・テーブルと反応室壁との間に生ずる流体抵抗の基板への影響をゼロにして基板位置に於いて最大限の排気速度が得られる。前述した磁気軸受型ターボ分子ポンプを例として用いた場合、ポンプ吸気穴排気速度SpはSp=22001/secで有り、ゲート・バルブ及びコンダクタンスCvがCv=31501/secで有るから、反応室に於ける実効排気速度Seは、1/se=1/Sp+1/Cvに依り、Se=12351/secと実施例1に記述した本発明のLPCVD装置(図1)と比較しても更に高い排気速度が得られる。又、本実施例9で示した本発明のLPCVD装置(図12)ではポンプ吸気穴に於ける圧力と基板に於ける圧力との差も従来のLPCVD装置や図1に示したLPCVD装置の圧力差よりもはるかに小さく、実質的により低圧での堆積が可能となる。これに依り高品質の半導体膜及び優れた薄膜半導体装置が窮めて容易に安定的に製造出来る様になった。
【0088】
(実施例10)
図13及び図14は本発明に依る化学気相堆積装置(CVD装置)の一例を示す概念図で有る。本実施例10では発明の例としてLPCVD装置を用いたが、ここに記する本発明はプラズマCVD装置(PECVD装置)や光CVD装置等、他のCVD装置に対しても有効で有る。
【0089】
例として述べるLPCVD装置は縦型炉で反応室101の中央付近に基板102は設置される。図13、図14では基板はターン・テーブル109上に水平に設置されて居るが、これに限らず垂直或いは傾斜状態で設置する事も可能で有る。反応室の外側にはヒーター108が設けられている。原料ガスはガス導入口1103より反応室に導入されゲート・バルブ1304を介してターボ分子ポンプ106に依り排気される。ターボ分子ポンプの排気は第二の真空ポンプ1307に依り行われる。本実施例10ではこの第二の真空ポンプとしてロータリーポンプを用いたが、ドライ・ポンプ等、他のポンプで有っても無論構わない。反応室内の圧力は圧力計1310に依って判定される。従来のLPCVD装置では反応室の圧力を調整するコンダクタンス・バルブが反応室とターボ分子ポンプとの間に設置されていたが、本発明では反応室の圧力を調整する為の圧力調整装置はターボ分子ポンプの排気口に設けられている。ターボ分子ポンプの吸気穴に於ける排気速度はターボ分子ポンプ排気口圧力と負の相関に有る為、例えば排気口の圧力を高くするとターボ分子ポンプ吸気穴に於ける排気速度は小さくなり、その結果反応室に於ける圧力は高くなる。反対に排気口の圧力を低くすると、排気速度は大きくなり、反応室の圧力は低くなる。従って反応室の圧力はターボ分子ポンプ排気口の圧力を調整する事で容易に調整し得る。図13ではターボ分子ポンプ排気口にガス流量調整器1305が設けられて居り、ヘリウム、窒素、アルゴン等の高純度不活性ガスを適当量ターボ分子ポンプ106の排気口に流し込む。このガスの流量は所望の反応室内圧力と圧力計1310で測定された実圧力との差に応じてガス流量調整器に依り調整される。従ってガス流量調整器1305でガスがターボ分子ポンプの排気口に全く供給されない時にターボ分子ポンプ吸気穴の排気速度は最大となる。一方、図14ではターボ分子ポンプ排気口にコンダクタンス・バルブ1405が設置されている。先と同様、コンダクタンス・バルブ1405の開閉度は所望の反応室内圧力と圧力計1310で測定された実圧力との差に応じて定められる。コンダクタンス・バルブ1405が全開の時にターボ分子ポンプ吸気穴の排気速度は最大となる。圧力調整装置としては上述のガス導入による方法やコンダクタンス・バルブを利用する方法単独の他、両者の組み合わせも可能で有り、これに依り高い堆積圧力が可能となる。
【0090】
通常CVD装置では様々な種類の膜を色々な堆積条件下、一台の装置で堆積する事が求められている。この場合、使用出来る堆積条件はなるたけ広い方が望ましい。例えば堆積圧力ならば低圧から比較的高い圧力まで広い圧力範囲を一台の装置でまかなえる事が望ましい。本発明のCVD装置ではこの様に広い圧力範囲で膜を堆積する事が可能と化すにのみならず、排気速度と低圧力が求められるCVD装置に対して窮めて効果的である。
【0091】
ターボ分子ポンプ106として実施例9で述べた磁気軸受型ターボ分子ポンプを用いた場合、ターボ分子ポンプと反応室の間にはゲート・バルブ1304のみが存在する。このゲート・バルブ1304のコンダクタンスCGはCG=105001/secで有るから、最大排気速度を得ようとした場合反応室に於ける実効排気速度SeはSe=18191/secと大きくなる。こうして、反応室に窒素を100SCCM程度流した時の反応室内平衡圧力は8.4×10 4torrとなり、超低圧堆積が可能となる。実施例9迄に述べて来た様に、100SCCM程度の比較的多量の原料ガスを反応室に導入し、且つこの様な超低圧堆積に依り良質な半導体膜をより低温で形成する事が可能になる。例えば真性シリコン膜堆積の場合、原料ガスにモノシランを用い100SCCM程流し堆積温度を555℃とした場合、堆積中のシラン分圧は0.8mtorr程度と化し、実施例5で述べた同温度での多結晶シリコン膜よりも圧力が低下した分だけ更に高結晶化率で大粒径を有する高品質多結晶シリコン膜が堆積される。又、これに限り優良な特性を有する薄膜半導体装置が低温プロセスで容易に作成される。
【0092】
一方、例えば図13に示した本発明のLPCVD装置に於いて、ガス流量調整器1305に依り純度99.9995%程度以上の窒素を1.4SLMターボ分子ポンプ排気口に流し、ガス導入口1103より原料ガスのモノシランを100SCCM反応室に導入した場合、ターボ分子ポンプ排気口での圧力は1.12torrと高くなり、相応して反応室内圧力は0.45torrとなる。先と同様の堆積温度が555℃の場合、堆積に依り得られる膜は非晶質シリコン膜で有る。又ガス流量調整器1305より同上の窒素を2.9SLMターボ分子ポンプ排気口に流し、ガス導入口1103より原料ガスを100SCCM反応室に導入した場合、ターボ分子ポンプ排気口での圧力は2.01torrで、反応室内圧力は1.6torrとなる。この様に本発明のCVD装置ではガス導入口1103から反応室へ導入する原料ガスの流量を例えば100SCCMと固定した場合、反応室内圧力を8.4×10 4torrの超低圧から1.6torrの比較的高い圧力まで一台の装で自由に設定し得、最低圧力と最大圧力の比は実に2000倍にも達する。これに応じて本発明の一台のCVD装置で高結晶性の多結晶半導体膜から非晶質半導体膜まで、様々な種類の半導体膜を自由に形成できる。更に比較的圧力が高い状態の堆積に於いても、堆積前の昇温期間を高排気速度の超低圧で行う事に依り400℃以上の温度で背景圧力を10 7torr代程度以下と高真空に保つ事が可能となる。これに依り、基板や反応室内壁からの脱ガスや、極微量のリークを充分速く排気出来、高純度半導体膜堆積が容易に行われる。
【0093】
これに対して、図7に示す従来技術のLPCVD装置では、反応室に原料ガスを100SCCM流した時の堆積最低圧力は33mtorr、コンダクタンス・バルブを全閉にして得られる最高圧力は0.9torrで最低圧力と最大圧力の比は高々27倍程度でしかない。この従来のLPCVD装置で堆積温度を555℃とし、原料ガスにモノシランを用いた場合、非晶質シリコン膜以外堆積し得ない。
【0094】
又図1に示す高排気速度を有するLPCVD装置で有っても、コンダクタンス・バルブが反応室(マニホールド)とターボ分子ポンプの間に有る場合、原料ガスを100SCCMガス導入103より反応室に導入した時のコンダクタンス・バルブ開閉調整に依る最低圧力と最高圧力はそれぞれ1.2mtorrと12mtorrで有る。この様に反応室内圧力調整装置をターボ分子ポンプの排気口に設ける事に依り使用し得る圧力範囲が大きく広がり、様々な種類の半導体膜を一台のCVD装置で形成する事が可能になったり、同時に超低圧堆積に依る半導体膜の高品質化も可能となった。
【0095】
(実施例11)
図15は本発明に依る化学気相堆積装置(CVD装置)の一例を示す概念図で有る。本実施例11では発明の例としてLPCVD装置を用いたが、ここに記する本発明はプラズマCVD装置(PECVD装置)や光CVD装置等、他のCVD装置に対しても有効で有る。
【0096】
例として述べるLPCVD装置は縦型炉で反応室101の中央付近に基板102は設置される。図15では基板はターン・テーブル109上に水平に設置されて居るが、これに限らず垂直或いは傾斜状態で設置する事も可能で有る。反応室の外側にはヒーター101が設けられている。原料ガスはガス導入口1103より反応室に導入され反応室に直接設置されたターボ分子ポンプ106に依り排気される。ターボ分子ポンプの排気は第二の真空ポンプ1307に依り行われる。本実施例11ではこの第二の真空ポンプとしてロータリーポンプを用いたが、ドライ・ポンプ等、他のポンプで有っても無論構わない。
反応室内の圧力は圧力計1310に依って判定される。
【0097】
従来のLPCVD装置では反応室とターボ分子ポンプとの間にゲート・バルブが設置されていたが、本発明ではゲート・バルブ1304はターボ分子ポンプの排気口に設けられている。又反応室内の圧力を調整する圧力調整装置1505はゲート・バルブ1304と第二の真空ポンプ1307の間に設けられている。圧力調整装置には高純度不活性ガスを所定量添加する方法や、コンダクタンス・バルブを用いる方法などが有る。圧力調整装置は圧力計1310に依り測定された反応室実圧力と所望圧力の差に応じて働く。
【0098】
以下本発明のCVD装置の操作手順の一例を説明する。
まず基板挿入後、ゲート・バルブ1304を開門する。
【0099】
この時第二の真空ポンプ1307は定常運転して居り反応室内をターボ分子ポンプ106を通じて粗引きをする。
【0100】
反応室内圧力はゲート・バルブ開門時に大気圧で有っても1torr程度の真空で有っても構わない。ゲート・バルブ開門と同時にターボ分子ポンプ106の運転を開始する。ターボ分子ポンプが定常運転に達した後、ゲート・バルブ1304を数秒から数分間閉じ、反応室への漏洩の有無をターボ分子ポンプ106とゲート・バルブ1304の間に設けられた圧力計1510に依り調査する。
【0101】
異常がなければゲート・バルブ1304を再び開門し、反応室を所定の温度まで昇温する。これはガスを全く導入しない10 7torr代程度以下の高真空で行っても良いし、高純度のガスを流しながら行っても良い。その後原料ガスを反応室に導入し、膜の堆積を行う。堆積終了後、真空引きや窒素等に依る反応室のパージを行った後、ターボ分子ポンプの運転を停止する。ターボ分子ポンプが停止後ゲート・バルブ1304を閉じ、反応室に窒素等の不活性ガスを導入し、大気圧等の所定の圧力に戻し、基板を取り出す。
【0102】
ターボ分子ポンプ106として実施例9で述べた磁気軸受型ターボ分子ポンプを用いた場合、ターボ分子ポンプ吸気穴はそのまま直接基板に面している為、反応室に於いて基板近傍での実効排気速度Seは正にターボ分子ポンプの排気速度Sp 等しく、
Se=Sp=22001/sec
と最大になる。こうして、反応室に窒素を100SCCM程度流した時の反応室内平衡圧力は6.9×10 4torrとなり、超低圧堆積が可能となる。これは実施例9に比較しても更に低圧となり、この為益々高品質シリコン膜がより低温で得られる。又これに依り、優良な特性を有する薄膜半導体装置が低温プロセスにて安定的に作成され得る。
【0103】
更に本発明では反応室内圧力をターボ分子ポンプ排気口の圧力に依り調整する為、例えば原料ガス流量を100SCCMとした場合、反応室内圧力を上述の6.9×10 4torrから1.6torrへと窮めて広い範囲で設定し得、一台のCVD装置に依り様々な堆積の膜形成が可能となった。
【0104】
以上述べて来た様に本発明に依れば反応室に於ける実効排気速度が10SCCM/mtorr以上で有るLPCVD装置か、或いは反応室内圧力が真空排気装置定常運転開始後10分以内に10 5torr以下となるLPCVD装置を用いてシリコン膜等の半導体膜を堆積する事に依り、半導体膜品質を大幅に向上させ、以て薄膜半導体装置の特性を飛躍的に向上せしめ、且つ製造時間の短縮・安定的大量生産を実現した。のみならず、本発明に依り、結晶質シリコン膜形成温度を従来より40度程度も低下させ、又低温での導電性シリコン膜の作成が可能となった。これに依り、本発明をアクティブ・マトリックス液晶ディスプレイなどに適応した場合、安価なガラス基板などが使用できる様になり、又他の電子装置に適応した場合も熱による素子劣化などを低減する。又、本発明のCVD装置に依ると従来よりもはるかに広い圧力範囲での膜形成が可能となり、1台のCVD装置で種々の膜形成が可能となった。かくして本発明はアクティブ・マトリックス液晶ディスプレイ装置や、集積回路等の電子装置の高性能化や低価格化を実現するという多大な効果を有する。
【0105】
【発明の効果】
以上の様に、本発明は薄膜半導体装置や集積回路、太陽電池、電荷結合装置等に適応されるシリコン膜等の半導体膜の形成方法及び、半導体膜形成に用いる減圧化学気相堆積装置とアクティブマトリックス液晶ディスプレイ等に適応される半導体膜を用いた薄膜半導体装置に適している。
【図面の簡単な説明】
【図1】本発明に依る減圧化学気相堆積装置(LPCVD装置)の概要を示す図。
【図2】(a)〜(e)は本発明の一実施例を示す薄膜半導体装置製造の名工程に於ける素子断面図。
【図3】本発明の効果を示す図。
【図4】本発明の効果を示す図。
【図5】本発明の効果を示す図。
【図6】本発明の効果を示す図。
【図7】従来の減圧化学気相堆積装置(LPCVD装置)の概要を示す図。
【図8】(a)〜(d)は本発明の一実施例を示す薄膜半導体装置製造の各工程に於ける素子断面図。
【図9】本発明に依るLPCVD装置のマニホールド部の概要を示す図。
【図10】従来のLPCVD装置のマニホールド部の概要を示す図。
【図11】発明に依る縦型減圧化学気相堆積装置(縦型LPCVD装置)の概要を示す図。
【図12】本発明に依る縦型減圧化学気相堆積装置(縦型LPCVD装置)の概要を示す図。
【図13】本発明に依る化学気相堆積装置(CVD装置)の概要を示す図。
【図14】本発明に依る化学気相堆積装置(CVD装置)の概要を示す図。
【図15】本発明に依る化学気相堆積装置(CVD装置)の概要を示す図。
【符号の説明】
101・・・反応室
102・・・基板
103・・・ガス導入管
104・・・マニホールド
105・・・ゲート・バルブ及びコンダクタンス・バルブ
106・・・ターボ分子ポンプ
107・・・ロータリー・ポンプ
108・・・ヒーター
109・・・ターン・テーブル
201・・・基板
202・・・下地保護膜
203・・・ソース・ドレイン領域
204・・・シリコン膜
205・・・チャンネル部シリコン膜
206・・・ゲート絶縁膜
207・・・ゲート電極
208・・・層間絶縁膜
209・・・ソース・ドレイン取り出し電極
703・・・排気管
705・・・真空排気装置への排気管
706・・・メカニカル・ブースター・ポンプ
801・・・基板
802・・・下地保護膜
803・・・半導体膜
804・・・ゲート絶縁膜
805・・・ゲート電極
806・・・キャップ層
807・・・チャンネル領域
808・・・ソース・ドレイン領域
809・・・層間絶縁膜
810・・・ソース・ドレイン取り出し電極
901・・・補強梁
902・・・真空排気装置吸気穴
903・・・基板挿入口
904・・・マニホールド吸気部
1103・・・ガス導入口
1206・・・磁気軸受型ターボ分子ポンプ
1304・・・ゲート・バルブ
1305・・・ガス流量調整器
1307・・・第二の真空ポンプ
1310・・・圧力計
1405・・・コンダクタンス・バルブ
1505・・・圧力調整器
1510・・・圧力計[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a semiconductor film such as a silicon film adapted to a thin film semiconductor device, an integrated circuit, a solar cell, a charge coupled device, etc., a reduced pressure chemical vapor deposition apparatus and an active matrix liquid crystal display, etc. The present invention relates to a thin film semiconductor device using a semiconductor film adapted to the above.
[0002]
[Prior art]
In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving method has shifted from the simple matrix method to the active matrix method, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmissive display is used.
[0003]
However, in order to increase the display screen and reduce the price, it is essential to use inexpensive ordinary glass as the insulating substrate. Therefore, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix liquid crystal display with stable performance on an inexpensive glass substrate while maintaining this economy.
[0004]
As the active layer of the thin film transistor, a semiconductor film such as amorphous silicon or polycrystalline silicon is usually used. However, when the thin film transistor is integrated with the drive circuit, polycrystalline silicon having a high operation speed is advantageous.
[0005]
Thus, there is a need for a technique for producing a thin film semiconductor device having a semiconductor film such as a polycrystalline silicon film as an active layer on a normal glass substrate. However, when a normal glass substrate is used, the maximum process humidity is about There is a great restriction that the glass strain point temperature is about 600 ° C. or lower. That is, a technique for forming an active layer of a thin film transistor capable of operating a liquid crystal display by a low temperature process and a thin film transistor capable of operating a driving circuit at high speed is desired.
[0006]
In order to deposit the semiconductor film by the conventional LPCVD method, first, the lowest background pressure reached is 10-3~Ten-FourUsing a torr LPCVD system, the deposition pressure is set to about 40 mtorr or higher, and a semiconductor film such as a silicon film is deposited by raising the deposition temperature to a temperature (610 ° C. to 640 ° C.) equal to or slightly higher than the glass strain point temperature. Was. Alternatively, using an LPCVD device with an effective pumping speed of 1SCCM / mtorr to 3SCCM / mtorr or less in the reaction chamber, the deposition temperature is increased to the maximum temperature (600 ° C to 620 ° C) that can be used for glass substrates. , Monosilane (SiH)Four) Was flown about 10 SCCM, and a semiconductor film such as a silicon film was volumetric with a monosilane partial pressure of several mtorr (Solid State Devices and Materials 1991, Extended Abstracts, P.614).
[0007]
In order to form an active layer semiconductor film by other methods, as a second method, for example, a semiconductor film such as a silicon film that becomes an active layer is deposited on an insulating substrate by a low pressure CVD method at a temperature of 570 ° C. or lower. A crystallized semiconductor film is formed by performing a heat treatment at a temperature of 640 ° C. or lower for about 24 hours to improve the characteristics of the thin film transistor (Japanese Patent Laid-Open No. 63-307776). The third method is to deposit an amorphous silicon film at a temperature of about 300 ° C or less by RF magnetron sputtering or plasma CVD method, and then form a silicon film by irradiating various lasers to make an active layer of the thin film transistor (Jpn.J.Appl.phys.28.P1871 (1989) and IEICE technical report EID-88-58, etc.).
[0008]
[Problems to be solved by the invention]
However, various problems are inherent in the above-described prior art. After the second silicon film is deposited, in the method of performing the heat treatment, the heat treatment temperature is too high to use a glass substrate, and if this treatment temperature is about 600 ° C. or less, the treatment time is spent several tens of hours or more, After all, a glass substrate cannot be used. In addition, there is a problem that the manufacturing process becomes redundant as compared with the manufacturing method by the first LPCVD method, resulting in a decrease in productivity and an increase in product price. In the method of performing laser irradiation after depositing the third silicon film, there is a problem that there is a large variation in semiconductor characteristics, and many thin film semiconductor devices cannot be formed uniformly over a large area. In addition, compared to the first LPCVD method, the manufacturing process is remarkably complicated and redundant as in the second method, leading to a decrease in productivity, the purchase of expensive processing equipment, and an increase in product price. Yes.
[0009]
On the other hand, in the conventional method of forming a semiconductor film such as a silicon film by LPCVD, the deposition apparatus and the deposition technique are immature, so when these semiconductor films are used as an active layer, the semiconductor characteristics are insufficient and high. There is a problem that it is still unsuitable for a switching element and a drive circuit of a fine high-resolution liquid crystal display.
[0010]
Accordingly, the present invention aims to solve such various problems, and its purpose is to provide a simple method of forming a high-quality semiconductor film only by the LPCVD method and a good thin-film semiconductor device using such a semiconductor film. And a low-pressure chemical vapor deposition apparatus capable of realizing the same.
[0011]
[Means for Solving the Problems]
  A chemical vapor deposition apparatus (CVD apparatus) according to the present invention includes at least a reaction chamber, a turbo molecular pump, and a second vacuum pump connected to an exhaust port side of the turbo molecular pump. )By flowing the inert gas into the exhaust port of the turbo molecular pump by adjusting the gas flow rate with the gas flow regulatorA pressure adjusting device is provided for adjusting the pressure in the reaction chamber by adjusting the pressure at the exhaust port of the turbo molecular pump.
[0012]
A chemical vapor deposition apparatus (CVD apparatus) of the present invention includes at least a reaction chamber, a turbo molecular pump, a gate valve, and a second vacuum pump connected to an exhaust port side of the turbo molecular pump. In the apparatus (CVD apparatus), the turbo molecular pump is installed directly in the reaction chamber, and the gate valve is installed between the turbo molecular pump and the second vacuum pump. Features.
[0013]
The chemical vapor deposition apparatus of the present invention is characterized in that a pressure adjusting device for adjusting the pressure in the reaction chamber is installed between the gate valve and the second vacuum pump.
[0014]
  The method for producing a semiconductor film of the present invention is characterized in that the semiconductor film is formed using the chemical vapor deposition apparatus (CVD apparatus) described above.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(Example 1)
Examples of the present invention will be described below, but the present invention is not limited to the following examples.
[0016]
FIG. 1 is a conceptual diagram of a low pressure chemical vapor deposition apparatus (LPCVD apparatus) according to the present invention. The LPCVD apparatus is a vertical furnace in which a 300 mm square glass substrate 102 is installed horizontally near the center of the quartz reaction chamber 101, and silane (SiHFour) Disilane (Si2H6) Or germane (GeHFourA semiconductor film such as a silicon film is deposited by utilizing thermal decomposition of the source gas. The diameter of the reaction chamber 101 is 600 mm and its volume is 184.51. In the first embodiment, the vacuum evacuation apparatus includes a turbo molecular pump 106 and a rotary pump 107.
[0017]
The vacuum evacuation device may be combined with a mechanical booster pump or a dry pump. Source gas and dilution gas such as helium, nitrogen, argon, and hydrogen are introduced into the reaction chamber 101 through a gas introduction pipe 103 as necessary, and a turbo attached directly to the manifold 104 via a gate valve and a conductance valve 105. The gas is exhausted from the molecular pump 106 through the rotary pump 107. There is no special separation between the manifold and the reactor. A heater 108 divided into three zones is installed outside the reaction chamber 101, and a soaking zone is formed at a desired temperature near the center of the reaction chamber by adjusting them independently. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is, for example, 600 ° C. and within 0.2 ° C. when set. Therefore, if the distance between the inserted substrates is 10 mm, 35 substrates can be processed in one batch. In Example 1, 17 substrates were installed in the soaking zone spread on the turntable 109 at intervals of 20 mm.
[0018]
The exhaust was performed by directly connecting the turbo molecular pump 106 and the rotary pump 107. The turbo molecular pump 106 used in the present invention is of a chemical type and can be operated even during the deposition of a semiconductor film such as a silicon film. The turbo molecular pump has a pumping speed of 22001 / sec with respect to nitrogen. In order to maximize the effective exhaust speed at the inlet of the reaction chamber 101, the turbo molecular pump 106, the gate valve, and the conductance valve 105 are directly attached to the manifold 104. As a result, the equilibrium pressure in the reaction chamber 101 when nitrogen flows through the 100 SCCM gas introduction pipe 103 with both pumps operating at a furnace temperature of 600 ° C. is 1.2 × 10-3torr, and the effective pumping speed was 83.3 SCCM / mtorr. In addition, the equilibrium pressure in each reaction chamber is 9.5 × 10 when 3.97 SCCM, 15.83 SCCM, 39.68 SCCM, and 300 SCCM are flowed under the same conditions.-Fivetorr, 2.5 × 10-Fourtorr, 5.5 × 10-Fourtorr, 3.0 × 10-3The corresponding effective pumping speeds were 41.8 SCCM / mtorr, 63.3 SCCM / mtorr, 72.1 SCCM / mtorr and 100 SCCM / mtorr, respectively.
[0019]
These pressures were measured using an ionization gauge calibrated with nitrogen. When a gas other than nitrogen was flowed, such as during the reaction, the pressure was measured using a melt film pressure gauge whose measured value did not depend on the gas type. The minimum resolution of the melt pressure gauge is 1 × 10-6It was torr.
[0020]
In the turbo molecular pump used in Example 1, when the pressure in the intake hole of the turbo molecular pump is about 3 mtorr, the pump intake hole exhaust speed Sp for nitrogen is Sp = 22001 / sec. On the other hand, the effective exhaust rate Se of the same pressure in the reaction chamber is Se = 100 SCCM / mtorr = 12671 / sec as described above. The conductance Cv of the gate valve and the conductance valve is Cv = 31501 / sec. Therefore, the total Cx of all the remaining conductances, such as the conductance between the manifold and the manifold and the reaction chamber, is
1 / se = 1 / Sp + 1 / Cv + 1 / Cx
Therefore, Cx = 579371 / sec. This is because the present invention has a sufficiently large conductance between the manifold itself and the conductance between the manifold and the reaction chamber, so that the remaining total conductance Cx can be made much larger than the pump intake hole exhaust speed Sp. As a result, the effective pumping speed Se in the reaction chamber can be increased.
[0021]
FIG. 9 shows a conceptual diagram of the manifold portion of the LPCVD apparatus according to the present invention viewed from the vertical (vertical) direction. The entire inside of the manifold 104 is formed into a cavity, and exhaust from the reaction chamber is taken through this wide cavity. Reinforcing beams 901 are provided in the interior, but since it is sufficiently thin compared to the width of the manifold cavity of 600 mm, it cannot be a factor in reducing the conductance of the manifold. The internal thickness of the manifold is 125 mm, and the cross-sectional area through which gas passes is 700 cm even at the narrowest part.2As described above, the conductance inside the manifold can be made sufficiently larger than the pump exhaust speed Sp and the conductance Cv of the gate valve and the conductance valve. As described above, the turbo molecular pump is directly attached to the lower portion of the manifold via the gate valve and the conductance valve. The diameter of the suction hole 902 of this evacuation device is 260mm, so its cross-sectional area is 531cm2There are substrate insertion ports 903 into the reaction chamber on the lower and upper surfaces of the manifold. In the LPCVD apparatus of the present invention, since a 300 mm square substrate can be installed horizontally in the reaction chamber, the diameter of the substrate insertion port 903 is 460 mm. It is desirable that the previous vacuum exhaust device intake hole 902 and the board insertion port 903 be as close as possible as long as the strength of the manifold is allowed.
[0022]
As shown in FIG. 1, a reaction chamber 101 is installed on the upper surface of the manifold. A gas introduction pipe 103 is erected on a manifold opposite to the exhaust device intake hole. Accordingly, the gas in the reaction chamber flows from top to bottom, in FIG. 9, from right to left. By arranging the gas introduction pipe and the intake hole of the manifold symmetrically, the generation of turbulent flow in the reaction chamber can be minimized, and the semiconductor film can be deposited uniformly and uniformly. Intake from the reaction chamber of the manifold is taken from the manifold intake portion 904. As shown in FIG. 1, the manifold intake portion 904 is taken on the side surface facing the manifold substrate insertion port. Of the side surface facing the substrate insertion port of the manifold, the entire semicircular portion in the direction of the vacuum evacuation device is opened, and this is the manifold intake portion 904. Since the radius of the board insertion slot is 230mm and the thickness of the manifold is 125mm, the opening area of the manifold intake part 904 is 903cm2In fact, the manifold and reaction chamber are virtually integrated. Therefore, the conductance between the manifold and the reaction chamber is much larger than the pumping speed of the pump. The opening on the entire side surface of the manifold on the reaction chamber side makes the distinction between the reaction chamber and the manifold meaningless. The difference is merely the temperature and the material, and the gas flow cannot be distinguished from each other. In this way, the cross-sectional area of the narrowest part of the manifold is made wider than the intake cross-sectional area of the vacuum exhaust system, and the effective exhaust speed in the reaction chamber is reduced as described above by taking the manifold intake section as wide as possible. I could make it bigger.
[0023]
The turbo molecular pump 106 reaches steady rotation in about 10 minutes after the start of operation. During this time, if the gate valve and the contact valve 105 are fully opened, the background pressure in the reaction chamber is 1.0 × 10 0 while the reaction chamber is kept at 600 ° C.-61.5x10 from torr-6torr. The background pressure in the reaction chamber 10 minutes after the turbo molecular pump reaches steady rotation is 4.0 × 10 at 600 ° C.-79.0 to 10 from torr-7between torr. If the gate valve is closed, the reaction chamber pressure is maintained at about 1 torr, and the turbo molecular pump is in steady operation, the gate valve is opened and the reaction chamber background pressure after 600 minutes is 600 ° C. And still 4.0 × 10-79.0 to 10 from torr-7between torr. As a result of directly connecting the turbo molecular pump to the manifold and maximizing the conductance, the effective pumping speed in the reaction chamber can be increased to 40 SCCM / mtorr or higher, so that the turbo molecular pump reaches the steady rotation or gate.・ 10 in just 10 minutes after opening the valve-7This is because the high vacuum of the torr range could be realized.
[0024]
The leakage rate of degassing and the like when inserting 17 235 mm square glass substrates into the LPCVD apparatus of the present invention and heating from 500 ° C. to 600 ° C. corresponding to the deposition temperature in a vacuum is about 2 × 10-Five7 × 10 from torr / min-FiveIt is torr / min. Therefore, the pressure rise caused by the impurity gas due to degassing in vacuum for 10 minutes is 2 × 10-Four7 × 10 from torr-FourIt is about torr.
[0025]
On the other hand, in the LPCVD apparatus of the present invention, when the vacuum exhaust apparatus such as a turbo molecular pump is in steady operation, the vacuum degree of 1 torr is 1 × 10 within 10 minutes as described above.-6Exhaust ability to reduce pressure to torr or less.
[0026]
Therefore, the LPCVD apparatus of the present invention can sufficiently exhaust unnecessary and inevitably generated degassing from a substrate, a boat jig or the like. Water (H) is used for degassing generated from substrates and boat jigs.20), oxygen (02) And the like, and these impurity gases inhibit the growth of a high-quality silicon film. That is, the impurity gas generated from the substrate or the boat jig can become a nucleus of the deposited film in the initial deposition process when depositing a semiconductor film such as a silicon film. Therefore, when the degassing is not exhausted sufficiently, a lot of impurity gases are adsorbed on the substrate surface, and many nuclei are generated. Therefore, the particle size constituting the deposited semiconductor film is reduced, which causes deterioration of the characteristics of the semiconductor film. In addition, even when an amorphous semiconductor film is deposited and later crystallized by heat treatment or laser irradiation, the presence of a large amount of nuclei due to these degassing causes the average grain size after crystal growth to be reduced. Smaller, it also reduces the semiconductor properties. Also, during the deposition, these outgas impurities suppress the surface migration of the source gas on the growth surface. Based on this, silane, disilane, germane phosphine (PHThree) ・ Diborane (B2H6), Etc., and the ability to find the most stable position in terms of crystal energy is reduced, leading to the formation of a semiconductor film with many grain boundaries and a semiconductor film containing a large amount of amorphous components. It will become. Further, when these degas impurities are taken into the grown semiconductor film, the semiconductor characteristics are further deteriorated.
[0027]
For this reason, in order to deposit a high-quality semiconductor film, an LPCVD apparatus that exhausts outgassing impurities inevitably generated from a substrate or the like sufficiently quickly is suitable. In general, the degassing rate in vacuum is 10 in 10 minutes.-FourIn order to bring about a pressure increase of about torr, an exhaust capacity larger than this degassing speed, that is, a vacuum of about 1 torr is increased to 10-FiveIn an LPCVD apparatus having a vacuum exhaust system of torr or less, degas impurities can be discarded out of the reaction chamber sufficiently quickly, and as a result, a high-quality semiconductor film is formed. Such an evacuation system eliminates unnecessary piping between the evacuation device and the reaction chamber, and the evacuation device is installed directly in the reaction chamber via the minimum required valves such as gate valves and conductance valves. This is because it is easily configured.
[0028]
2 (a) to 2 (e) are cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming an MIS type field effect transistor. In the first embodiment, a thin film semiconductor device having a non-self-aligned staggered structure is taken as an example. However, the present invention is also effective for a thin film semiconductor device having a reverse staggered structure and a self-aligned thin film semiconductor device. Yes.
[0029]
In the first embodiment, 235 mm square quartz glass is used as the substrate 201. However, as long as the substrate can withstand the semiconductor film deposition temperature, the type and size of the substrate are not limited. Furthermore, although an intrinsic silicon film is used as the semiconductor film in the first embodiment, silicon, an intrinsic germanium film, or a donor or acceptor containing impurities, such as phosphorus or poron, impurities such as donors and acceptors, or germanium are also used. A germanium film containing bismuth is also possible.
[0030]
First, a silicon dioxide film (SiO2) that serves as a base protection film on the substrate 201 by atmospheric pressure chemical vapor deposition (APCVD) or sputtering.2A film) 202 is formed, and then a silicon film containing an impurity serving as a donor or acceptor is deposited by LPCVD, followed by patterning to form a source / drain region 203. (FIG. 2-a) In Example 1, phosphorus is selected as an impurity, and phosphine (PHThree) And SiHFourA silicon film containing impurities was deposited by LPCVD at a deposition temperature of 600 ° C. to 1500 Å.
[0031]
Next, as shown in FIG. 1, a channel part silicon film 204 to be an active layer of a transistor was deposited using the LPCVD apparatus described above. (Fig. 2-b) In Example 1, SiH was used as the source gas.FourThe silicon film 204 was deposited at a deposition temperature of 600 ° C. without using any dilution gas. The substrate was inserted into the reaction chamber 101 maintained at 400 ° C. with the front side facing down. At this time, 30 SLM of pure nitrogen flows out from the gas introduction pipe 103, and the flow of air into the reaction chamber when the substrate is inserted is minimized.
[0032]
After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. The leak rate of degassing etc. at this time is 4.3 × 10-FiveIt was torr / min. Thereafter, the temperature was raised from the insertion temperature of 400 ° C. to the deposition temperature of 600 ° C. over an hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the temperature was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.8 × 10-7It was torr. During the remaining 50 minutes, the nitrogen gas with a purity of 99.9999% or more continued to flow at 300 SCCM. The equilibrium pressure in the reaction chamber at this time is 3.0 × 10-3It was torr. After reaching the deposition temperature, the source gas SiHFourWas flowed at 250 SCCM, and a Si film was deposited for 6 minutes 51 seconds. At this time, the opening and closing of the conductance valve was adjusted to maintain the reaction chamber pressure at 28.5 mtorr. The pressure during the reaction was measured using a diaphragm type pressure gauge whose measured value does not depend on the gas type. The thickness of the silicon film thus obtained was 294 angstroms. Next, this silicon film was patterned to form a channel part silicon film 205 to be an active layer of the transistor. (Figure 2-C)
Thereafter, a gate insulating film 206 is formed by an electron cyclotron resonance plasma chemical vapor deposition method (ECR-PECVD method) or an APCVD method. In Example 1, Si0 is used as the gate insulating film.2The film was used and deposited to a thickness of 1500 angstroms by ECR-PECVD. (FIG. 2-d) Subsequently, a thin film to be the gate electrode 207 is deposited by sputtering or CVD. In Example 1, chromium (Cr) was selected as the gate electrode material, and 1500 angstroms was deposited by sputtering. After depositing a thin film to be a gate electrode, patterning is performed, and further, an interlayer insulating film 208 is deposited by 5000 angstroms, contact holes are opened, and source / drain extraction electrodes 209 are formed by sputtering or the like to complete a thin film semiconductor device. (Fig. 2-e)
An example Vgs-Ids curve of the transistor characteristics of the thin film semiconductor device manufactured in this way is shown in FIGS. Here, Ids represents the source / drain current, Vgs represents the gate voltage, and the source / drain voltage Vds was 4 V and measured at a temperature of 25 ° C. The transistor channel portion had a length L = 10 μm and a width W = 10 μm. When the transistor is turned on with Vds = 4V and Vgs = 10V, the on-current is 3.34 × 10-7It was A. The off-state current when the transistor is turned off at Vgs = 0V is 2.24 × 10.-13As a result, a good thin film semiconductor device in which Ids fluctuated by 6 digits or more with respect to 10V modulation of the gate voltage was obtained. The effective electron mobility obtained from the saturation current region of this thin film semiconductor device is 6.1 cm.2/ V · sec.
[0033]
On the other hand, in FIGS. 3 and 3-b, the active layer channel part silicon film is deposited by the conventional LPCVD method, and all other processes are compared with the Vgs-Ids curve when the thin film semiconductor device is manufactured in the same manner as the present invention. For the sake of
[0034]
As shown in FIG. 7, compared with the LPCVD apparatus of the present invention shown in FIG. 1, the conventional LPCVD apparatus has the same reaction chamber size, shape, substrate type, number of sheets, insertion position, heating system, etc. In contrast, the exhaust system is very different. That is, in the conventional LPCVD apparatus, exhaust is performed by the rotary pump 107 and the mechanical booster pump 706. The exhaust from the reaction chamber 101 is taken through an exhaust pipe 703 standing on the manifold 104, and further exhausted from the manifold by an exhaust pipe 705 to a vacuum exhaust device. FIG. 10 shows a conceptual view of the manifold portion of a conventional LPCVD apparatus as viewed from the vertical (vertical) direction. The conventional manifold has a donut shape with an outer diameter of 600 mm, a manifold width of 70 mm and a thickness of 125 mm, and a cross-sectional area of 87.5 cm.2The conductance is very small. In addition, a cylindrical tube having a diameter of 40 mm and a length of 685 mm is set up as four exhaust pipes 703 between the manifold and the reaction chamber. The conductances of the exhaust pipes are each 11.641 / sec. As a result, the conductance between the manifold and the reaction chamber is about 471 / sec. Therefore, when helium is flowed at 74SCCM at a reaction chamber temperature of 600 ° C, the reaction chamber has an effective exhaust velocity of 25.2 mtorr, and the minimum background pressure in the reaction chamber is 10-FourIt was in the torr generation.
[0035]
In such a conventional LPCVD system, the deposition temperature is 600 ° C, SiHFourA Si film was deposited as the active layer channel at a flow rate of 70 SCCM and a reactor pressure of 28.4 mtorr for 8 minutes and 30 seconds. The thickness of the deposited Si film was 299 angstroms. In this way, the on-state current of the thin film semiconductor device fabricated by the prior art is 1.1 × 10-7A, off-current is 8.76 × 10-13The effective electron mobility obtained from the saturation current region is 2.48 cm.2/ V. It was in sec.
[0036]
Comparing these results informs us of the great advantages of the present invention. In other words, the present invention, for example, increases the electron mobility more than twice as much as the prior art, increases the on-current more than three times, reduces the off-current to less than one-third, and can greatly improve the transistor characteristics. It was. In addition, the deposition rate of the present invention is improved from the conventional deposition rate of 35.2 angstrom / min at the same pressure at the same temperature as 42.9 angstrom / min, which is useful for shortening the production time and improving the throughput. It is a thing. Furthermore, according to the present invention, an LPCVD apparatus having a high vacuum and a high pumping capacity, which is normally impossible with a hot wall type, can be realized by the above-described special vacuum pumping system. As a result, a large number of substrates can be processed in one batch, and at the same time, excellent uniformity can be secured. In fact, in Example 1, 17 235 mm substrates were processed at the same time, but the variation in film thickness within each substrate was less than 1% over the entire surface except within 1 cm from the corners of the substrate. . That is, 552.25 cm that a 235 mm square substrate has2Within the area of 549.11cm except for each square2The film thickness variation in the region of was less than 2 angstroms. Also, the film thickness variation between the substrates was very uniform except for the thin film of about 30 angstroms, which was placed on the bottom layer, and the remaining 16 sheets were very uniform. At 289 angstroms, the thickest substrate was 298 angstroms. As described above, the LPCVD apparatus of the present invention having a high vacuum and a high exhaust capacity makes it possible to give a high-quality semiconductor film uniformly and in large quantities.
[0037]
In general, in the silicon thin film semiconductor device, the temperature and pressure when depositing the silicon film constituting the channel portion are known as important parameters. If these are the same, a silicon film having the same film quality is deposited, It is believed that a thin film semiconductor device having equivalent transistor characteristics will be created. However, the present invention greatly improves transistor characteristics by improving the exhaust system even when the temperature and pressure are the same, and shortening the deposition time to increase the throughput and depositing a higher quality semiconductor film. succeeded in.
[0038]
(Example 2)
FIGS. 2A to 2B are cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming a MIS type field effect transistor. In Example 2, a non-self-aligned staggered groove thin film semiconductor device was created as an example. However, the present invention is also effective for a thin film semiconductor device having a reverse staggered structure and a self-aligned thin film semiconductor device. It is.
[0039]
In the second embodiment, quartz glass of 235 mm □ is used as the substrate 201, but the type and size of the substrate are of course not limited as long as the substrate can withstand the silicon film deposition temperature. Also, in the second embodiment, a silicon film is used as a semiconductor film. However, as in the first embodiment, germanium (Ge), silicon germanium (SiχGel-χ: 0 <χ <1), a donor / acceptor, and the like are included. It may be a semiconductor film.
[0040]
First, a silicon dioxide film (Sio) that serves as a base protective film on the substrate 201 by atmospheric pressure chemical vapor deposition (APCVD) or sputtering.2A film) 202 is formed, and then a silicon film containing an impurity serving as a donor or acceptor is deposited by the LPCVD method, followed by patterning to form a source / drain frame region 203. (FIG. 2-a) In Example 2, phosphorus is selected as an impurity, and phosphine (PHThree) And SiHFourA silicon film containing impurities was deposited by LPCVD at a deposition temperature of 600 ° C. to 1500 Å.
[0041]
Next, using the LPCVD apparatus shown in FIG. 1 and described in detail in Example 1, a channel portion silicon film 204 serving as an active layer of the transistor was deposited. (Fig. 2-b) In Example 2, SiH was used as the source gas.FourThe silicon film 204 was deposited at a deposition temperature of 600 ° C. without using any dilution gas. The substrate was inserted into the reaction chamber 101 maintained at 400 ° C. with the front side facing down. At this time, 30 SML of pure nitrogen flows out from the gas introduction pipe 103, and air is prevented from flowing into the reaction chamber when the substrate is inserted. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. The leak rate of degassing etc. at this time is 4.0 × 10-FiveIt was torr / min. Thereafter, the temperature was raised from the insertion temperature of 400 ° C. to the deposition temperature of 600 ° C. over an hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the moisture was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.5 × 10-7It was torr. During the remaining 50 minutes, the nitrogen gas with a purity of 99.9999% or more continued to flow at 300 SCCM. The reaction chamber equilibrium pressure at this time is 3.0 × 10-3It was torr. After reaching the deposition temperature, the source gas SiHFourWas flowed at 250 SCCM, and a Si film was deposited for 12 minutes 46 seconds. During this time, the conductance pulp was fully opened, and the reactor internal pressure was measured using a diaphragm type pressure gauge whose tide value did not depend on the gas type. Raw material SiHFourFor the first 3 minutes and 16 seconds after introduction into the reaction chamber, the equilibrium pressure in the reaction chamber was 2.55 mtorr. This pressure measurement is based on SiH with the reaction chamber temperature at 25 ° C.FourIs equivalent to the equilibrium pressure in the reaction chamber obtained when 250 SCCM flows. Under these conditions, the relationship between the deposition time t (min) and the deposited film thickness T (angstrom) is
T (Angstrom) = -87.9 (Angstrom) + 30.4 (Angstrom / min) x t (min)
Therefore, it is presumed that thermal decomposition of the raw material gas does not occur for the first three minutes after introducing the raw material gas into the reaction chamber. Thereafter, the pressure in the reaction chamber gradually increased to 2.94 mtorr 11 minutes and 16 seconds after the introduction of the raw material gas, and this pressure value was maintained until 12 minutes and 46 seconds after the introduction of the raw material gas at which deposition was completed. The increase in pressure in the reaction chamber results from the change in the reaction rate of the raw material silane and the increase in the amount of hydrogen produced. Therefore, considering this pressure change, the reaction rate of the raw material silane immediately before the end of deposition is 16.7%, and based on this, the silane partial pressure is estimated to be 2.10 mtorr.
[0042]
On the other hand, in this Example 2, 17 substrates of 235 m □ were inserted into the reaction chamber, so the total area in the reaction chamber was 44,040 cm.2It becomes. Assuming the same deposition rate throughout the reaction chamber, the reaction rate of the raw material silane and the partial pressure of silane were estimated from the deposition rate and the total area in the reaction chamber, which were 10.0% and 2.52 mtorr, respectively. The thickness of the silicon film thus obtained was 301 angstroms. Next, this silicon film was patterned to form a channel part silicon film 205 to be an active layer of the transistor. (Fig. 2-C)
After that, a gate insulating film 206 is formed by ECR-PECVD method or APCVD method. In Example 2, SiO2 is used as the gate insulating film.2Using the film, it was deposited to a thickness of 1500 angstrom by ECR-PECVD method. (FIG. 2-d) Subsequently, a thin film to be the gate electrode 207 is deposited by sputtering or CVD. In Example 2, chromium (Cr) was selected as the gate electrode material, and 1500 angstroms was deposited by sputtering. After depositing a thin film to be a gate electrode, patterning is performed, and further, an interlayer insulating film 208 is deposited by 5000 angstroms, contact holes are opened, and source / drain extraction electrodes 209 are formed by sputtering or the like to complete a thin film semiconductor device. (Fig. 2-e)
An example Vgs-Ids curve of the transistor characteristics of the thin film semiconductor device fabricated in this way is shown in FIGS. Here, Ids represents the source / drain current, Vgs represents the gate voltage, and the source / drain voltage Vds was 4 V and measured at a temperature of 25 ° C. The transistor channel portion had a length L = 10 μm and a width W = 10 μm. When the transistor is turned on with Vds = 4V and Vgs = 10V, the on-current is 95% with a reliability coefficient of ION = (2.40 + 0.08, -0.07) x 10-6It was A. The off-state current when the transistor is turned off at Vgs = 0V is IOFF = (1.82 + 0.64, -0.47) x 10-13As a result, a good thin film semiconductor device in which Ids fluctuated by 7 digits or more with respect to 10V modulation of the gate voltage was obtained. The effective electron mobility obtained from the saturation current region of this thin film semiconductor device is 10.84 ± 0.29 cm.2/ V · sec. Thus, a good thin film semiconductor device was obtained according to the present invention.
[0043]
On the other hand, in FIGS. 4 and 4-b, the conductance valve is fully closed and the effective pumping speed in the reaction chamber is lowered to deposit the silicon film of the active layer channel part. All other processes are the same as in the present invention. The Vgs-Ids curve when the device was manufactured is listed for comparison. When this conductance pulp is fully closed, the equilibrium pressure in the reaction chamber when nitrogen is passed through the reaction chamber at 100 SCCM, 200 SCCM, and 300 SCCM is 1.2 × 10 2 at a furnace temperature of 600 ° C., respectively.-2torr, 2.6 × 10-2torr, 4.0 × 10-2The corresponding effective exhaust speeds were 8.33 SCCM / mtorr, 7.69 SCCM / mtorr, and 7.50 SCCM / mtorr, respectively. This effective pumping speed is about twice as large as the effective pumping speed of the conventional LPCVD equipment and is not representative of conventional welding, but in order to compare all other manufacturing conditions as in the present invention, the effective pumping speed As a small example, a thin film semiconductor device was manufactured.
[0044]
Using the LPCVD apparatus of the present invention with the conductance valve fully opened, a channel portion silicon film serving as an active layer of the transistor was deposited. In this comparative example, SiH was used as the source gas.FourThe silicon film 204 was deposited at a deposition temperature of 600 ° C. without using any dilution gas. The substrate was inserted into the reaction chamber 101 maintained at 400 ° C. with the front side facing down. At this time, 30 SLM of pure nitrogen flows out from the gas introduction pipe 103, and the flow of air into the reaction chamber when the substrate is inserted is minimized. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. The leak rate of degassing, etc. at this time is 4.3 × 10−FiveIt was torr / min. Thereafter, the temperature was raised from the insertion temperature of 400 ° C. to the deposition temperature of 600 ° C. over one hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber, and the moisture was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.8 × 10-7It was torr. During the remaining 50 minutes, the nitrogen gas with a purity of 99.9999% or more continued to flow at 300 SCCM. The reaction chamber equilibrium pressure at this time is 3.0 × 10-3It was torr. After reaching the deposition temperature, the source gas, SiH4, was flowed at 250 SCCM, and a Si film was deposited for 6 minutes 51 seconds. At this time, the conductance valve was fully closed, and the reactor pressure was 28.5 mtorr. The pressure during the reaction was measured using a diaphragm type pressure gauge whose judgment value does not depend on the gas type. The thickness of the silicon film thus obtained was 294 angstroms. Except for this, a thin film semiconductor device was prototyped in the same manufacturing process as that of the present invention in Example 2.
[0045]
The on-state current of the thin film semiconductor device of the comparative example created in this way is ION = (3.34 + 0.11, -0.12) × 10-7A, off current is I OFF = (2.24 + 0.79, -0.58) x 10-13The effective electron mobility obtained from the saturation current region with A is 6.12 ± 0.29 cm.2/ V · sec. As can be seen from this comparative example, according to the present invention in which the channel portion silicon film is formed by the LPCVD apparatus with an effective pumping speed of 10 SCCM / mtorr or more, the conventional LPCVD apparatus having an effective pumping speed of 10 SCCM / mtorr or less is used. Compared to the technology for forming the silicon film in the channel part of thin film semiconductor devices, the on-current can be increased more than 7 times and the off-current can be kept low, resulting in an on-off ratio of 10 times that of the conventional technology. I succeeded in increasing it.
[0046]
In general, in a silicon thin film semiconductor device, temperature and pressure when depositing a silicon film constituting a channel portion are known as important parameters. For example, when a silicon film is deposited at a deposition temperature of 600 ° C, the effective pumping speed is small when the silane fraction is 3 mtorr or less in the conventional LPCVD equipment, so the deposition rate is as low as about 8 angstrom / min, and the semiconductor characteristics are also poor. There was. However, according to the present invention, by increasing the effective evacuation rate, the deposition rate is increased and the deposition time is shortened. However, the transistor characteristics have been greatly improved by the low pressure deposition.
[0047]
(Example 3)
2 (a) to 2 (e) are cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming an MIS type field effect transistor. In Example 3, a thin film semiconductor device having a non-self-aligned staggered structure was created as an example, but the present invention is also effective for a thin film semiconductor device having a reverse staggered structure and a self-aligned thin film semiconductor device. Yes.
[0048]
In the third embodiment, quartz glass of 235 m □ is used as the substrate 201, but the type and size of the substrate are of course not limited as long as the substrate can withstand the semiconductor film deposition temperature. Further, although an intrinsic silicon film is used as the semiconductor film in Example 3, the semiconductor film may be a silicon film containing a donor or an acceptor, a SiχGel-χ (0 <χ <1) or SiGex film containing germanium. I do not care. First, a silicon dioxide film (SiO2) that serves as a base protection film on the substrate 201 by atmospheric pressure chemical vapor deposition (APCVD) or sputtering.2A film) 202 is formed, and then a silicon film containing an impurity serving as a donor or acceptor is deposited by LPCVD, followed by patterning to form a source / drain region 203. (FIG. 2-a) In Example 3, phosphorus is selected as an impurity, and phosphine (PHThree) And SiH4 were mixed, and a silicon film containing impurities was deposited at 1500 Å by LPCVD at a deposition temperature of 600 ° C.
[0049]
Next, using the LPCVD apparatus of the present invention shown in FIG. 1 and described in detail in Example 1, a channel portion silicon film 204 serving as an active layer of a transistor was deposited. (Fig. 2-b) In Example 3, SiH was used as the source gas.FourThe silicon film 204 was deposited at a deposition temperature of 600 ° C. without using any dilution gas. The substrate was inserted into the reaction chamber 101 maintained at 400 ° C. with the front side facing down. At this time, 30 SLM of pure nitrogen flows out from the gas introduction pipe 103, and the flow of air into the reaction chamber when the substrate is inserted is minimized. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. The leak rate of degassing etc. at this time is 3.0 × 10-FiveIt was torr / min. Thereafter, the temperature was raised from the insertion temperature of 400 ° C. to the deposition temperature of 600 ° C. over an hour.
[0050]
During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the temperature was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 5.2 × 107Nitrogen gas with a purity of 99.9999% or more was continued to flow at 300 SCCM during the remaining 50 minutes of temperature increase. The equilibrium pressure in the reaction chamber at this time was 3.0 × 10 −3 torr. SiH, the source gas after reaching the deposition temperatureFourWas flowed at 50 SCCM, and a Si film was deposited for 26 minutes 04 seconds.
[0051]
During this time, the conductance valve was fully opened, and the pressure in the reaction chamber was measured using a diaphragm type pressure gauge whose measured value did not depend on the gas type. Raw material SiHFourWas introduced into the reaction chamber for the first 13 minutes and 30 seconds, the equilibrium pressure in the reaction chamber was 0.69 mtorr. This pressure measurement is based on SiH with the reaction chamber temperature at 25 ° C.FourIs approximately equal to 0.67 mtorr of equilibrium pressure in the reaction chamber obtained when 50 SCCM is flowed. Under these conditions, the relationship between the deposition time t (min) and the deposited film thickness T (angstrom) is T (angstrom) = -227 (angstrom) + 20.6 (angstrom / min) x t (min). It is estimated that thermal decomposition of the raw material gas does not occur for the first 12 minutes after introducing the raw material gas into the reaction chamber. Thereafter, the pressure in the reaction chamber gradually increased, and reached 0.86 mtorr 26:00 after the introduction of the raw material gas just before the deposition was completed.
The increase in pressure in the reaction chamber results from the change in the reaction rate of the raw material silane and the increase in the amount of hydrogen produced.
[0052]
Therefore, considering this pressure change, the reaction rate of the raw material silane immediately before the end of deposition is 31.5%, and based on this, the silane partial pressure is estimated to be 0.45 mtorr. On the other hand, in this Example 3, 17 substrates of 235 mm □ were inserted into the reaction chamber, so the total area in the reaction chamber was 44,040 cm.2It becomes. Assuming the same deposition rate throughout the reaction chamber, the reaction rate of the raw material silane and the partial pressure of silane were estimated from the deposition rate and the total area in the reaction chamber, resulting in 34.0% and 0.43 mtorr, respectively. The silicon film thus obtained had a thickness of 326 angstroms. Next, this silicon film was patterned to form a channel part silicon film 205 to be an active layer of the transistor. (Figure 2-C)
After that, the gate insulating film 206 is formed by ECR-PECVD method or APCVD method. In Example 3, Si0 is used as the gate insulating film.2The film was used and deposited to a thickness of 1500 angstroms by ECR-PECVD. (FIG. 2-d) Subsequently, a thin film to be the gate electrode 207 is deposited by sputtering or CVD. In Example 3, chromium (Cr) was selected as the gate electrode material, and 1500 angstroms was deposited by sputtering. After depositing a thin film to be a gate electrode, patterning is performed, and further, an interlayer insulating film 208 is deposited by 5000 angstroms, contact holes are opened, and source / drain extraction electrodes 209 are formed by sputtering or the like to complete a thin film semiconductor device. (Fig. 2-e)
When the transistor characteristics of the thin film semiconductor device prototyped in this way were measured, the source / drain current Ids when the transistor was turned on with the source / drain voltage Vds = 4V and the gate voltage Vgs = 10V was defined as the on-current ION. ION = (3.63 + 0.12, -0.11) × 10 with 95% confidence factor-6It was A. Here, the measurement was performed on a transistor having a channel portion length L = 10 μm and a width W = 10 μm at a temperature of 25 ° C. The effective electron mobility (J. Levisonetal.j, Appl, Phys. 53, 1193'82) obtained from the saturation current region is μ = 12.91 ± 0.29 cm.2It was at /v.sec. Thus, a good thin film device was obtained according to the present invention.
[0053]
(Example 4)
Except for the step of depositing the channel portion silicon film, all other steps were performed in the same manner as in Example 3 to produce a thin film semiconductor device. In this Example 4, the channel part silicon film is deposited using the LPCVD apparatus detailed in Example 1, at a deposition temperature of 600 ° C., without using a dilution gas, and a silane flow rate of 100 SCCM to 250 SCCM, set every 50 SCCM. Then, the thin film semiconductor device was fabricated by depositing the channel portion silicon film so that the film thickness was about 300 angstroms. At this time, since the conductance valve of the LPCVD apparatus is fully opened, the pressure in the reaction chamber, the deposition rate, the silane reaction rate, and the silane partial pressure change according to the change in the silane flow rate. These values for each sample are listed in Table 1. Table 1 and FIGS. 5 and 6 show the on-current and effective mobility defined in Example 3 as an example of the transistor characteristics of the thin conductor device thus obtained. In these tables and figures, error bars indicate interval estimates at a 95% confidence factor. From these tables and figures, if a channel silicon film with a silane partial pressure of 1 mtorr or less or a reaction chamber pressure of 2 mtorr or less is deposited, the film quality of the semiconductor film is greatly improved, so the corresponding transistor characteristics are clearly noticeable. You can see that it improves.
[0054]
However, from the viewpoint of high productivity, it is necessary to process as many substrates as possible in one batch. In order to satisfy this, it is necessary to keep the reaction rate of silane, which is a raw material gas, low and to make the difference in silane partial pressure between substrates as small as possible to make the film quality between substrates uniform. That is, in order to achieve both high quality film and high productivity, at least the raw material silane gas is allowed to flow about 100 SCCM or more to maintain the uniformity between the substrates, while the reactor pressure is 2 mtorr in order to deposit the high quality film. The following will inevitably become necessary. As described in detail in Example 1, the vacuum evacuation apparatus of the present invention has a evacuation speed of 22001 / sec with respect to nitrogen. Therefore, when the silane flow rate is 100 SCCM, the maximum pressure in the reaction chamber is 1.49 mtorr. Both of these conditions are satisfied without contradiction. In general, in order to satisfy these two requirements, at least the evacuation speed of the vacuum evacuation device must be 16501 / sec or more.
[0055]
[Table 1]
Figure 0003786580
[0056]
(Example 5)
Sio on a 3 inch diameter fused silica glass substrate2After depositing the film, a silicon film was formed and its physical properties were examined. First, the quartz substrate was immersed in boiling 60% nitric acid for 5 minutes to remove the substrate surface, and then immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the amorphous oxide film on the substrate surface. Immediately after, Si0 which becomes a base protective film by APCVD2Was deposited to a film thickness of 2000 Angstroms.
[0057]
Next, a silicon film was deposited using the LPCVD apparatus of the present invention shown in FIG. 1 and described in detail in Example 1. In Example 5, SiH was used as the source gas.FourA silicon film was deposited at a deposition temperature of 555 ° C. without using any dilution gas. A quartz substrate with a diameter of 3 inches is placed in the center of the 17 235mm square substrates placed as dummy substrates, and the reaction chamber is placed at the top on the ninth substrate from the bottom and kept at 400 ° C. Was inserted into 101. At this time, 30 SLM of pure nitrogen flows out from the gas introduction pipe 103, and the flow of air into the reaction chamber when the substrate is inserted is minimized. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. The leak rate of degassing, etc. at this time is 4.45 × 10-FiveIt was torr / min. Thereafter, the temperature was increased from 400 ° C insertion temperature to 555 ° C deposition temperature for one hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the moisture was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.0 × 10-7It was torr. During the remaining 50 minutes, the nitrogen gas with a purity of 99.9999% or more was continuously supplied at 300 SCCM.
[0058]
The equilibrium pressure in the reaction chamber at this time is 3.0 × 10-3It was torr. After reaching the deposition temperature, the source gas SiHFourWas flowed 100 SCCM, and a Si film was deposited for 15 hours 4 minutes 00 seconds. During this time, the conductance valve was fully opened, and the pressure in the reaction chamber was measured using a diaphragm type pressure gauge whose measured value did not depend on the gas type. Raw material SiHFourFor the first 17 minutes and 30 seconds after introduction into the reaction chamber, the equilibrium pressure in the reaction chamber was 1.21 mtorr. This pressure measurement is based on SiH with the reaction chamber temperature at 25 ° C.FourIs equivalent to the equilibrium pressure in the reaction chamber obtained when 100 SCCM is flowed. Also, under these conditions, the relationship between the deposition time t (min) and the deposited film thickness T (angstrom) is as follows for films with a deposited film thickness of less than 1000 angstroms.
T (Angstrom) = -102 (Angstrom) + 5.63 (Angstrom / min) x t (min)
Therefore, it is estimated that the pyrolysis of the source gas has not occurred for the first 18 minutes after the source gas is introduced into the reaction chamber. Thereafter, the pressure in the reaction chamber gradually increased, and reached 1.26 mtorr 15 hours and 40 minutes after the introduction of the raw material gas just before the deposition was completed.
[0059]
The increase in pressure in the reaction chamber results from the change in the reaction rate of the raw material silane and the increase in the amount of hydrogen produced.
[0060]
Therefore, considering this pressure change, the reaction rate of the raw material silane immediately before the end of deposition is 3.4%, and based on this, the silane partial pressure is estimated to be 1.17 mtorr. On the other hand, in Example 5, 17 235 mm square substrates were inserted into the reaction chamber, so the total area in the reaction chamber was 44,040 cm 2. Assuming the same deposition rate throughout the reaction chamber, the reaction rate of the raw material silane and the partial pressure of silane were estimated from the deposition rate and the total area in the reaction chamber, which were 4.6% and 1.15 mtorr, respectively. The thickness of the silicon film thus obtained was 5363 angstroms.
[0061]
Next, the crystallinity of the silicon film thus obtained was examined by X-ray diffraction and Raman spectroscopy. In the X-ray diffraction method, strong peaks were observed at diffraction angles 2θ (θ is the black angle) at 28.47 degrees, 47.44 degrees, 56.18 degrees, and 69.21 degrees. These peaks correspond to (111), (220), (311), (400) diffraction of single crystal silicon powder, and clearly show that the silicon film obtained in this Example 5 has a polycrystalline quality. Yes. The peak intensities are 5118, 16760, 2787, and 498 in order of arbitrary scale, and the silicon film obtained in Example 5 is recognized as polycrystalline silicon preferentially oriented in the (110) plane direction. Raman spectroscopy was measured in a backscattering configuration in a microscopic sample chamber.
[0062]
In order to avoid the peak shift and half-width broadening due to the annealing due to the excitation laser light and the temperature rise of the sample surface, the laser output was reduced to 10 mW, and at the same time, the beam diameter was set to the maximum 10 μm in the microscopic measurement. The measurement is performed at 25 ° C and the wave number scanning area is 600 cm.-1From 100cm-1It was in.
[0063]
As a result of such Raman spectroscopy measurement, the silicon film obtained in this Example 5 has a wave number of 519.50 cm.-1Half width 4.27cm-1It was confirmed that it was a crystalline silicon film. Also, optical mode frequency 520cm corresponding to crystalline silicon-1Nearby Raman scattering integration accuracy and 130cm frequency corresponding to amorphous silicon-1Nearby acoustic shear wave mode, 290cm-1Nearby acoustic longitudinal wave mode 405cm-1Nearby optical longitudinal wave mode and 480cm-1Example 5 where the crystallinity was obtained from the relative ratio of the optical transverse wave mode amorphous silicon that appears in the vicinity to the sum of the scattering integral intensities (Appl, Phys, Lett, 40 (6), 534 (1982)) It was measured that the silicon film obtained according to the above has a high crystallinity of 96.6%.
Here, the value of the scattering integral intensity correction coefficient K is 0.88.
[0064]
As a result of these physical property measurements, a crystalline silicon film that could not be deposited unless the deposition temperature was 580 ° C or higher was formed at a low temperature by using the LPCVD apparatus according to the present invention to a temperature of about 55 ° C or lower. It became possible for the first time to do.
[0065]
Next, phosphorus was added to the intrinsic silicon film obtained in Example 5 to produce an electrical conductor. In Example 5, impurity ions were added using a bucket type mass non-separation type ion implantation apparatus. Using phosphine with a concentration of 5% diluted in hydrogen as the source gas, 1.6 × 10 at an acceleration voltage of 110 kV161 / cm2Typed into the concentration. Next, this substrate was inserted into a furnace maintained at 400 ° C. in a nitrogen atmosphere and subjected to heat treatment. The heat treatment time was 3 hours. The sheet resistance value of the silicon film thus obtained was a low value of 185Ω / □. In silicon films created at a deposition temperature of 580 ° C or lower by the conventional LPCVD method, even if impurity ions such as phosphorus are added, the resistance value is infinite unless heat treatment is performed at a temperature of 600 ° C or higher for several tens of hours. Virtually no electricity flowed. However, when the ion implantation method according to the present invention is used for the silicon film of the present invention formed by the LPCVD apparatus according to the present invention, the electrical resistance value is sufficiently low by the low temperature deposition of 555 ° C. and the low temperature heat treatment of 400 ° C. Could show. Accordingly, the silicon film of the present invention can be formed at a low temperature of about 555 ° C. or less for a silicon film used for any electronic device such as a thin film semiconductor device, an integrated circuit (LSI), or a gate electrode or wiring of a charge coupled device (CCD). In addition, an electrical conductor can be produced even at such a low temperature. This makes it possible to protect the elements from deterioration due to high-temperature heat processes, and to form other elements, wiring, etc. with a material having low heat resistance. Can bring about
[0066]
(Example 6)
2 (a) to 2 (e) are cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming an MIS type field effect transistor. In Example 6, a non-self-aligned staggered groove thin film semiconductor device was created as an example. However, the present invention is also effective for a reverse staggered thin film semiconductor mounting and a self-aligned thin film semiconductor device. It is.
[0067]
In Example 6 of the present invention, 235 mm-square quartz glass was used as the substrate 201, but the type and size of the substrate are of course not limited as long as the substrate can withstand the silicon film deposition temperature. First, a silicon dioxide film (Si0) serving as a base protective film on the substrate 201 by atmospheric pressure chemical vapor deposition (APCVD) or sputtering.2(Film) 202 is formed, and then a silicon film containing an impurity which becomes a donor or an acceptor is formed and then subjected to buttering to form a source / drain region 203. (Fig. 2-a)
In this Example 6, using the LPCVD apparatus of the present invention shown in FIG. 1 and described in detail in Example 1, after depositing about 1500 angstroms of intrinsic silicon film at a deposition temperature of 555 ° C., phosphorus is selected as an impurity element, Phosphorus was implanted by an implantation method to form a silicon film containing impurities. The intrinsic silicon film that later becomes the source and drain regions is formed by the LPCVD apparatus of the present invention using SiH, which is a source gas.FourWas deposited at a deposition temperature of 555 ° C. for 4 hours 53 minutes 04 seconds. The relationship between the pressure change in the reaction chamber and the deposited film thickness T (angstrom) and the deposition time t (min) was the same as that shown in Example 5. That is, the source gas SiHFourThe pressure in the reaction chamber immediately after the introduction of the gas into the reaction chamber at 555 ° C. was 1.21 mtorr, and it was 1.27 mtorr 4 hours and 52 minutes after the introduction of the raw material gas just before the completion of deposition. The intrinsic silicon film thus obtained had a thickness of 1571 angstroms. Subsequently, phosphorus was added to the intrinsic silicon film by using a bucket type mass non-separation type ion implantation apparatus. The source gas used is phosphine with a concentration of 5% diluted in hydrogen, with a high frequency output of 38 W and an acceleration voltage of 110 kV, 3 × 10151 / cm2Typed into the concentration. Thereafter, heat treatment was performed at 400 ° C. for 1 hour and 30 minutes in a room atmosphere, and the sheet resistance value of the silicon film containing impurities thus obtained was 936Ω / □.
[0068]
Next, using the LPCVD apparatus of the present invention shown in FIG. 1 and described in detail in Example 1, a channel portion silicon film 204 serving as an active layer of a transistor was deposited. (Fig. 2-b) In Example 6, SiH was used as the source gas.FourThe silicon film 204 was deposited at a deposition temperature of 555 ° C. without using any dilution gas. The substrate was inserted into the reaction chamber 101 maintained at 400 ° C. with the front side facing down. At this time, 30 SLM of pure nitrogen flows out from the gas introduction pipe 103, and the flow of air into the reaction chamber when the substrate is inserted is minimized. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching steady rotation, leakage inspection was performed for 2 minutes. At this time, the degassing leak rate is 4.85 × 10-FiveIt was torr / min. Thereafter, the temperature was raised from the insertion temperature of 400 ° C. to the deposition temperature of 555 ° C. over an hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the temperature was increased in vacuum. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.4 × 10-7It was torr. During the remaining 50 minutes, the nitrogen gas with a purity of 99.9999% or more continued to flow at 300 SCCM. At this time, the equilibrium pressure in the reaction chamber is 3.0 × 10−ThreeIt was torr.
[0069]
After reaching the deposition temperature, the source gas SiHFourWas flowed 100 SCCM, and a Si film was deposited for 58 minutes 23 seconds. During this time, the conductance valve was fully opened, and the pressure in the reaction chamber was slid using a diaphragm type pressure gauge whose measured value did not depend on the gas type. Raw material SiHFourFor the first 17 minutes 30 seconds after introduction into the reaction chamber, the equilibrium pressure in the reaction chamber was 1.21 mtorr. The relationship between the deposition time t (min) and the deposited film thickness T (angstrom) is the same as in Example 5. The reaction chamber equilibrium pressure was 1.27 mtorr after 5 minutes 00 seconds after the introduction of the raw material gas just before the deposition was completed. As shown in Example 5, assuming the same deposition rate throughout the reaction chamber, the reaction rate of the raw material silane and the partial pressure of silane are estimated from the deposition rate and the total area in the reaction chamber, respectively, and are 4.6% and 1.15 mtorr, respectively. . The silicon film thus obtained had a film thickness of 199 angstroms. Next, this silicon film was buttered to form a channel portion silicon film 205 to be an active layer of the transistor. (Figure 2-C)
After that, the gate insulating film 206 is formed by ECR-PECVD method or APCVD method. In Example 6, SiO2 is used as the gate insulating film.2The film was used and deposited to a thickness of 1500 angstroms by ECR-PECVD. (FIG. 2-d) Subsequently, a thin film to be the gate electrode 207 is deposited by sputtering or CVD. In Example 6, chromium (Cr) was selected as the gate electrode material, and 1500 angstroms were deposited by sputtering. After depositing a thin film to be a gate electrode, patterning is performed, and further, an interlayer insulating film 208 is deposited to a thickness of 500 angstroms, contact holes are opened, and source / drain extraction electrodes 209 are formed by sputtering or the like, thereby completing a thin film semiconductor device. (Fig. 2-e)
When the transistor characteristics of the thin film semiconductor device prototyped in this way were measured, the source / drain current Ids when the transistor was turned on with the source / drain voltage Vds = 4V and the gate voltage Vgs = 10V was defined as the on-current ION. ION = (1.45 + 0.08, -0.07) × 10 with 95% confidence factor-6It was A. The off-state current when the transistor is turned off with Vds = 4V and Vgs = 0V is IOFF = (0.079 + 0.030, -0.022) x 10-12It was A. Here, the measurement was performed on a transistor having a channel portion length L = 10 μm and a width W = 10 μm at a temperature of 25 ° C. Effective electron mobility (J. Levinsonetal. J, APPl, Phys. 53, 1193'82) obtained from the saturation current range is μ = 9.30 ± 0.39 cm2/ V. It was in sec.
[0070]
In this way, according to the present invention, a high-quality thin film semiconductor device having a high mobility and having an Ids varying by 7 digits or more with respect to 10V modulation of the gate voltage has a maximum process temperature of 555 ° C. or less. Moreover, this was realized for the first time in a low-temperature process in which the period maintained at the maximum process temperature was within several hours. This is not only because the present invention simply improves the performance of semiconductor films and thin film semiconductor devices, but at the same time, the high quality semiconductor films and high performance thin film semiconductor devices can be manufactured in large quantities at low temperature processes that were previously considered impossible to manufacture at all. In addition, this means that we have also provided the first stable production method.
[0071]
(Example 7)
FIGS. 8A to 8D are cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming an MIS field effect transistor.
[0072]
In Example 7, 235 mm square quartz glass was used as the substrate 801, but the type and size thereof are not limited as long as the substrate can withstand a thermal environment of about 555 ° C. for 3 hours.
[0073]
First, a silicon dioxide film (SiO2) that serves as a base protection film on the substrate 801 by atmospheric pressure chemical vapor deposition (APCVD) or sputtering.2Film) 802 is formed. In Example 7, the substrate temperature is 300 ° C. by the APCVD method, the deposition rate is 3.9 angstrom / sec, and the film thickness is 2000 angstrom.2A base protective film 802 was formed by depositing the film.
[0074]
Next, a semiconductor film 803 is formed using the LPCVD apparatus of the present invention shown in FIG. In the seventh embodiment, an intrinsic silicon film is used as a semiconductor film, but other semiconductor films such as a silicon / germanium film and a gallium / arsenic film are also possible.
[0075]
In addition, the semiconductor film has impurities that become P-type or n-type 1 × 10191 / cmThreeYou may contain the trace amount below a grade. In Example 7, a silicon film was deposited at a deposition temperature of 555 ° C. and a silane flow rate of 100 SCCM for 2 hours 5 minutes 26 seconds. During deposition, the temperature was raised from 400 ° C. as the substrate insertion temperature to 555 ° C. as the deposition temperature over 1 hour, but the gas was raised in vacuum without introducing any gas into the reaction chamber for the first 10 minutes. The minimum background pressure to reach the reaction chamber 10 minutes after the start of temperature increase is 6.1 × 10-7It was torr. In addition, nitrogen gas with a purity of 99.9999% or more continued to flow for 300 SCCM during the remaining 50 minutes of temperature increase. The reaction chamber equilibrium pressure at this time is 3.0 × 10-3It was torr. Further, the equilibrium pressure in the reaction chamber 2 hours and 5 minutes after the introduction of the source gas just before the end of the deposition was 1.26 mtorr. The semiconductor film thus obtained had a film thickness of 588 angstroms. Next, this semiconductor film was patterned to form a semiconductor film 803 to be a transistor later (FIG. 8a).
[0076]
After that, a gate insulating film 804 is formed by ECR-PECVD method or APCVD method. In Example 7, SiO2 is used as the gate insulating film.2Using the film, the substrate temperature was set to 100 ° C. by the ECR-PECVD method, and the film was deposited to a thickness of 1500 Å.
[0077]
Next, a conductive film that will later become a gate electrode is formed, and a film that becomes a cap layer is further formed. The cap layer was provided so that these impurity elements did not reach the channel portion when impurities serving as donors or acceptors were later implanted into the semiconductor film using the gate electrode as a mask. Therefore, this cap layer is not required if the gate electrode has a blocking capability against impurity addition, such as a thick gate electrode. In Example 7, indium tin oxide (ITO) having a film thickness of 2000 angstroms is selected for the gate electrode 805, and 3500 angstroms of SiO2 is used for the cap layer 806.2A membrane was used. The gate electrode 805 is formed by a sputtering method at a substrate temperature of 150 ° C., and the cap layer 806 is formed by an APCVD method using SiO.2After the film was deposited at a substrate temperature of 300 ° C., the film was patterned to form a gate electrode 805 and a cap layer 806 (FIG. 8b).
In addition, the gate electrode material may be a metal material such as chromium, tungsten, or molybdenum, or a silicide film such as molybdenum, silicide, or tungsten silicide.
[0078]
Further, when these films have a film thickness of about 3500 angstroms or more, the aforementioned cap layer is not required. It is also effective to form pure aluminum as a gate electrode by a sputtering method or the like of about 8000 angstroms. Again, no cap layer is required. As the cap layer, SiO shown in Example 7 was used.2In addition to the film, silicon nitride, SiON film, metal oxide film, and the like are also possible.
[0079]
Next, an impurity element serving as a donor or an acceptor is implanted into the semiconductor film 803 using the gate electrode 805 as a mask by using a packet type mass non-separation type ion implantation apparatus. By this method, the source / drain region 808 and the channel region 807 are formed in a self-aligned manner with respect to the gate electrode 805 in the semiconductor film (FIG. 8c).
[0080]
In Example 7, because an attempt was made to make an N-type MOS, 5% phosphine (PH) diluted in hydrogen as a source gas was used.ThreeHowever, it is not limited to this as long as the hydride of the impurity element is diluted with hydrogen. For example, to make P-type MOS, diborane diluted in hydrogen (B2H6) Etc. are also possible. In this Example 7, the general gas is turned into plasma at a frequency of 13.56 MHz and an output of 50 W, and at an acceleration voltage of 110 kv, PHThree +, PH2 +, PH+, H2 +, H+, Etc. for all ion species, the total number of ions is 2 × 10161 / cm2It was driven into the semiconductor film. Thereafter, nitrogen annealing is performed at 350 ° C. for 2 hours to complete the source / drain region 808. The sheet resistance value of the source / drain region after nitrogen annealing was 17.01 kΩ / □.
[0081]
Thereafter, an interlayer insulating film 809 is deposited by APCVD at about 5000 angstroms at 300 ° C., contact holes are opened, and source / drain extraction electrodes 810 are formed to complete a thin film semiconductor device. In Example 7, source / drain extraction electrodes 810 were formed by patterning after depositing aluminum at 8000 Å by sputtering at a substrate temperature of 180 ° C.
[0082]
When the transistor characteristics of the thin film semiconductor device fabricated in this way were measured, the source / drain current I ds when the transistor was turned on with the source / drain voltage Vds = 4v and the gate voltage Vgs = 10v was defined as the on-current. I ON = 5.62 × 10 at room temperature for a transistor with both channel length and width of 10 μm 7A was obtained. The effective electron mobility obtained from the saturation current region of this transistor is 95% with a reliability coefficient of μ = 6.87 ± 0.35 cm.2/ V · sec. Furthermore, when the transistor is turned off with Vds = 4V and Vgs = 0V, the off-current is 8.48 × 10 for the same transistor. 13It was angstrom. As described above, according to the present invention, the maximum process temperature is 555 ° C., and the temperature is maintained for about 2 hours, so that a large number of excellent self-aligned thin film semiconductor devices are uniformly and large in a short time with a low temperature process. Succeeded in creating. According to the present invention, the maximum temperature after forming a high-quality semiconductor film 803 at 555 ° C. is suppressed to nitrogen annealing due to impurity activation at 350 ° C., which causes hydrogenation that contributes to variations, process variations, and reduced throughput. It depends on having completed the thin film semiconductor device without going through processes such as processing and laser irradiation. In the present invention, since 555 ° C. is the most severe thermal environment, even if relatively inexpensive glass is used as a substrate, expansion / contraction, distortion, etc. of the substrate are not a problem, and a high-definition, high-density thin film semiconductor device. Can be made inexpensively and in a large area.
[0083]
(Example 8)
As described in detail from Example 1 to Example 7, the higher the effective pumping speed in the reaction chamber, the better the quality semiconductor film can be deposited at a lower temperature. Thus, a uniform and excellent thin film semiconductor device can be stably manufactured on an inexpensive large-area substrate.
[0084]
FIG. 11 is a conceptual diagram of a vertical reduced pressure chemical vapor deposition apparatus (vertical LPCVD apparatus) according to the present invention having such an excellent function. In the LPCVD apparatus, a substrate 102 is horizontally installed in the vicinity of the center of the reaction chamber 101, and a semiconductor film such as a silicon film is deposited by utilizing thermal decomposition of a source gas such as silane, disilane, or germane. These gases and dilution gases such as nitrogen, hydrogen, and argon are introduced into the reaction chamber from a gas inlet 1103 installed at the lower part of the reaction chamber. The substrate 102 is placed on a turn table 109 in which several disks are combined, and the turn table and the substrate are rotated several times per minute during the semiconductor film deposition. The source gas that has entered the reaction chamber flows between the turntable and the inner wall of the reaction chamber, reaches the substrate, and is further exhausted by a manifold 104 or a vacuum pump installed at the top of the reaction chamber. In this Example 8, the same manifold and vacuum pump as the LPCVD apparatus of the present invention described in detail in Example 1 were used as the manifold and vacuum pump. However, for example, the manifold may be omitted as described later. There are other possible combinations. A heater 108 divided into several zones is installed outside the reaction chamber, and a desired temperature region can be formed in the reaction chamber by adjusting the temperature of each zone independently. For example, the heater 108 is divided into 5 zones, and the heater temperature is increased sequentially from the bottom heater, and a temperature gradient can be created in the reaction chamber so that the temperature rises at a constant rate from the lower substrate to the upper side. It is. Of course, it is possible to set a soaking zone where the temperature between the substrates is constant.
[0085]
In the vertical LPCVD apparatus shown in Example 8, gas flows from the bottom to the top. Therefore, strictly speaking, the pressure in the reaction chamber is lower at the upper side. As described above, in order to obtain a high-quality semiconductor film, it is preferable to deposit at a high pumping speed and a low pressure as much as possible. In the LPCVD system shown in Fig. 11, since the exhaust is taken from above, the conductance between the turntable and the reaction chamber wall does not matter, and the exhaust speed from the reaction chamber intake hole of the manifold becomes the exhaust speed that the substrate suffers as it is. Furthermore, it becomes possible to form a semiconductor film by high vacuum. Further, in the present invention, since exhaust is taken out over the entire upper surface of the reaction chamber, the occurrence of convection in the reaction chamber is greatly reduced, and a more uniform film can be formed between the substrates. In addition, silane (SiHFour), Dichlor, Silane (SiH)2Cl2In general, the molecular weight of the reaction gas is hydrogen (H2) And hydrogen chloride (HCl), etc., the molecular weight is usually larger. Therefore, in the method of setting up the exhaust pipe as in the conventional LPCVDD device shown in FIG. 7, the product gas stays in the upper part of the reaction chamber, and the ratio of the reaction gas to the product gas in the reaction chamber changes with the lapse of the deposition time. In contrast, the LPCVD shown in FIG. 11 of the present invention eliminates the retention of the product gas, and the deposition state can be adjusted at will from the beginning to the end of the deposition. Furthermore, gases with low molecular weight, such as hydrogen, generally have a poor pumping speed. If these gases stay in the reaction chamber, the exhausting speed of the substrate decreases as a result, but the LPCVD apparatus of the present invention exhausts from above. These light gases can be effectively evacuated, so that the evacuation speed that the substrate itself actually suffers can be maximized. As described above, according to the LPCVD apparatus of the present invention, a higher quality semiconductor film can be deposited at a low temperature of about 555 ° C. or less, and the deposition rate can be increased.
[0086]
(Example 9)
FIG. 12 is a conceptual diagram of a vertical reduced pressure chemical vapor deposition apparatus (vertical LPCVD apparatus) according to the present invention.
[0087]
As described in detail in Example 8, in order to more effectively form a high-quality semiconductor film, a raw material gas is introduced from the lower part of the reaction chamber in a vertical LPCVD apparatus having a high exhaust capability, and the exhaust gas is discharged from the upper surface of the reaction chamber. It is desirable to take it widely. The LPCVD apparatus of the present invention shown in FIG. 12 does not have a manifold, but a magnetic bearing type turbo molecular pump 1206 (for example, Osaka Vacuum Equipment Co., Ltd.) via a gate valve attached to the upper surface of the reaction chamber and a conductance valve 105. Made by magnetic bearing type complex molecular pump TG2203MV) directly installed in the reaction chamber. By using a magnetic bearing type turbo molecular pump, the turbo molecular pump can be used upside down, and this allows gas flow from the bottom to the top to facilitate uniform deposition and high-speed exhaust of light molecules. In addition, it is possible to obtain the maximum exhaust speed at the substrate position by eliminating the influence of the fluid resistance generated between the manifold or turntable and the reaction chamber wall on the substrate. When the above-described magnetic bearing type turbo molecular pump is used as an example, the pump intake hole exhaust speed Sp is Sp = 22001 / sec, and the gate valve and conductance Cv is Cv = 31501 / sec. The effective pumping speed Se depends on 1 / se = 1 / Sp + 1 / Cv, and Se = 12351 / sec, which is even higher than the LPCVD apparatus of the present invention described in Example 1 (FIG. 1). can get. Further, in the LPCVD apparatus of the present invention shown in Example 9 (FIG. 12), the difference between the pressure in the pump intake hole and the pressure in the substrate is also different from the pressure of the conventional LPCVD apparatus and the LPCVD apparatus shown in FIG. Much smaller than the difference, allowing deposition at substantially lower pressures. As a result, high-quality semiconductor films and excellent thin-film semiconductor devices can be given up and manufactured easily and stably.
[0088]
(Example 10)
13 and 14 are conceptual diagrams showing an example of a chemical vapor deposition apparatus (CVD apparatus) according to the present invention. In the tenth embodiment, an LPCVD apparatus is used as an example of the invention, but the present invention described here is also effective for other CVD apparatuses such as a plasma CVD apparatus (PECVD apparatus) and a photo CVD apparatus.
[0089]
An LPCVD apparatus described as an example is a vertical furnace in which a substrate 102 is installed near the center of a reaction chamber 101. In FIG. 13 and FIG. 14, the substrate is horizontally installed on the turntable 109. However, the substrate is not limited to this and can be installed in a vertical or inclined state. A heater 108 is provided outside the reaction chamber. The source gas is introduced into the reaction chamber from the gas inlet 1103 and exhausted by the turbo molecular pump 106 through the gate valve 1304. The turbo molecular pump is evacuated by a second vacuum pump 1307. In the tenth embodiment, a rotary pump is used as the second vacuum pump. However, other pumps such as a dry pump may be used. The pressure in the reaction chamber is determined by a pressure gauge 1310. In the conventional LPCVD apparatus, a conductance valve for adjusting the pressure in the reaction chamber was installed between the reaction chamber and the turbo molecular pump. In the present invention, the pressure adjusting device for adjusting the pressure in the reaction chamber is a turbo molecule. It is provided at the exhaust port of the pump. Since the exhaust speed at the intake hole of the turbo molecular pump has a negative correlation with the turbo molecular pump exhaust port pressure, for example, when the exhaust port pressure is increased, the exhaust speed at the turbo molecular pump intake hole decreases, and as a result The pressure in the reaction chamber increases. On the contrary, when the pressure at the exhaust port is lowered, the exhaust speed is increased and the pressure in the reaction chamber is lowered. Therefore, the pressure in the reaction chamber can be easily adjusted by adjusting the pressure at the exhaust port of the turbo molecular pump. In FIG. 13, a gas flow rate regulator 1305 is provided at the turbo molecular pump exhaust port, and an appropriate amount of high-purity inert gas such as helium, nitrogen, and argon flows into the exhaust port of the turbo molecular pump 106. The flow rate of this gas is adjusted by a gas flow rate regulator according to the difference between the desired reaction chamber pressure and the actual pressure measured by the pressure gauge 1310. Accordingly, when no gas is supplied to the exhaust port of the turbo molecular pump by the gas flow regulator 1305, the exhaust speed of the turbo molecular pump intake hole is maximized. On the other hand, in FIG. 14, a conductance valve 1405 is installed at the exhaust port of the turbo molecular pump. As before, the degree of opening and closing of the conductance valve 1405 is determined according to the difference between the desired reaction chamber pressure and the actual pressure measured by the pressure gauge 1310. When the conductance valve 1405 is fully open, the exhaust speed of the turbo molecular pump intake hole is maximized. As the pressure adjusting device, the above-described method using gas introduction or the method using a conductance valve alone can be used, or a combination of the two can be used, thereby enabling a high deposition pressure.
[0090]
  In general, a CVD apparatus is required to deposit various types of films with a single apparatus under various deposition conditions. In this case, it is desirable that the usable deposition conditions are as wide as possible. For example, in the case of deposition pressure, it is desirable to cover a wide pressure range from a low pressure to a relatively high pressure with a single device. In the CVD apparatus of the present invention, it is possible not only to deposit a film in such a wide pressure range,HighIt is effective in complimenting CVD equipment that requires pumping speed and low pressure.
[0091]
  When the magnetic bearing type turbo molecular pump described in the ninth embodiment is used as the turbo molecular pump 106, only the gate valve 1304 exists between the turbo molecular pump and the reaction chamber. The conductance CG of this gate valve 1304 is CG = 105001 / secTherefore, when trying to obtain the maximum pumping speed, the effective pumping speed Se in the reaction chamber increases as Se = 18191 / sec. Thus, the equilibrium pressure in the reaction chamber when nitrogen is allowed to flow through the reaction chamber at about 100 SCCM is 8.4 × 10 FourIt becomes torr, and ultra-low pressure deposition becomes possible. As stated in Example 9, 100 SCCMIt is possible to introduce a relatively large amount of source gas into the reaction chamber and to form a high-quality semiconductor film at a lower temperature by such ultra-low pressure deposition. For example, in the case of intrinsic silicon film deposition, when monosilane is used as the source gas and flowed for about 100 SCCM and the deposition temperature is set to 555 ° C., the partial pressure of silane during deposition is reduced to about 0.8 mtorr. A high quality polycrystalline silicon film having a larger grain size with a higher crystallization rate is deposited as much as the pressure is lower than that of the crystalline silicon film. In addition, a thin film semiconductor device having excellent characteristics can be easily produced by a low temperature process.
[0092]
  On the other hand, for example, in the LPCVD apparatus of the present invention shown in FIG. 13, nitrogen having a purity of about 99.9995% or more is caused to flow to the 1.4 SLM turbo molecular pump exhaust port by the gas flow rate regulator 1305, When monosilane is introduced into the 100 SCCM reaction chamber, the pressure at the turbo molecular pump outlet is as high as 1.12 torr, and the corresponding pressure in the reaction chamber is 0.45 torr. When the same deposition temperature as before is 555 ° C., the film obtained by deposition is an amorphous silicon film. Also, when the nitrogen flow from the gas flow regulator 1305 is flowed to the 2.9 SLM turbo molecular pump exhaust port and the raw material gas is introduced from the gas inlet port 1103 to the 100 SCCM reaction chamber, the pressure at the turbo molecular pump exhaust port is 2.01 torr, The pressure in the reaction chamber is 1.6 torr. Thus, in the CVD apparatus of the present invention, when the flow rate of the raw material gas introduced from the gas inlet 1103 into the reaction chamber is fixed at, for example, 100 SCCM, the pressure in the reaction chamber is set to 8.4 × 10. FourOne unit from ultra-low pressure of torr to relatively high pressure of 1.6 torrPlaceThe ratio between the minimum pressure and the maximum pressure can reach 2000 times. In response to this, various types of semiconductor films from a highly crystalline polycrystalline semiconductor film to an amorphous semiconductor film can be freely formed with one CVD apparatus of the present invention. Furthermore, even in deposition with relatively high pressure, the background pressure is increased to 10 ° C at a temperature of 400 ° C or higher by performing the heating period before deposition at an ultra-low pressure with a high pumping speed. 7It becomes possible to keep a high vacuum below the torr range. Accordingly, degassing from the substrate and the reaction chamber wall and a very small amount of leakage can be exhausted sufficiently quickly, and high-purity semiconductor film deposition can be easily performed.
[0093]
On the other hand, in the conventional LPCVD apparatus shown in FIG. 7, the minimum deposition pressure when the raw material gas flows into the reaction chamber at 100 SCCM is 33 mtorr, and the maximum pressure obtained by fully closing the conductance valve is 0.9 torr. The ratio of pressure to maximum pressure is only about 27 times. In this conventional LPCVD apparatus, when the deposition temperature is 555 ° C. and monosilane is used as the source gas, only an amorphous silicon film can be deposited.
[0094]
  In addition, even if the LPCVD equipment has a high pumping speed as shown in Fig. 1, if the conductance valve is located between the reaction chamber (manifold) and the turbo molecular pump, 100SCCM gas is introduced as the source gas.tubeWhen introduced into the reaction chamber from 103, the minimum pressure and the maximum pressure due to conductance and valve opening / closing adjustment are 1.2 mtorr and 12 mtorr, respectively. In this way, the pressure range that can be used is greatly expanded by providing the pressure regulator in the reaction chamber at the exhaust port of the turbo molecular pump, making it possible to form various types of semiconductor films with a single CVD device. At the same time, it has become possible to improve the quality of semiconductor films by ultra-low pressure deposition.
[0095]
(Example 11)
FIG. 15 is a conceptual diagram showing an example of a chemical vapor deposition apparatus (CVD apparatus) according to the present invention. In this Embodiment 11, an LPCVD apparatus was used as an example of the invention, but the present invention described here is also effective for other CVD apparatuses such as a plasma CVD apparatus (PECVD apparatus) and a photo CVD apparatus.
[0096]
An LPCVD apparatus described as an example is a vertical furnace in which a substrate 102 is installed near the center of a reaction chamber 101. In FIG. 15, the substrate is horizontally installed on the turntable 109. However, the substrate is not limited to this and can be installed in a vertical or inclined state. A heater 101 is provided outside the reaction chamber. The source gas is introduced into the reaction chamber through the gas inlet 1103 and exhausted by the turbo molecular pump 106 installed directly in the reaction chamber. The turbo molecular pump is evacuated by a second vacuum pump 1307. In the present embodiment 11, a rotary pump is used as the second vacuum pump, but other pumps such as a dry pump may be used.
The pressure in the reaction chamber is determined by a pressure gauge 1310.
[0097]
In the conventional LPCVD apparatus, a gate valve is provided between the reaction chamber and the turbo molecular pump. In the present invention, the gate valve 1304 is provided at the exhaust port of the turbo molecular pump. A pressure adjusting device 1505 for adjusting the pressure in the reaction chamber is provided between the gate valve 1304 and the second vacuum pump 1307. The pressure adjusting device includes a method of adding a predetermined amount of high purity inert gas, a method of using a conductance valve, and the like. The pressure adjusting device works according to the difference between the reaction chamber actual pressure measured by the pressure gauge 1310 and the desired pressure.
[0098]
Hereinafter, an example of the operation procedure of the CVD apparatus of the present invention will be described.
First, after inserting the substrate, the gate valve 1304 is opened.
[0099]
At this time, the second vacuum pump 1307 is in steady operation, and roughing the reaction chamber through the turbo molecular pump 106.
[0100]
The pressure in the reaction chamber may be at atmospheric pressure when the gate / valve is opened or a vacuum of about 1 torr. Simultaneously with the opening of the gate valve, the operation of the turbo molecular pump 106 is started. After the turbo molecular pump reaches steady operation, the gate valve 1304 is closed for several seconds to several minutes, and the presence or absence of leakage into the reaction chamber is determined by a pressure gauge 1510 provided between the turbo molecular pump 106 and the gate valve 1304. investigate.
[0101]
If there is no abnormality, the gate valve 1304 is opened again to raise the temperature of the reaction chamber to a predetermined temperature. This does not introduce any gas10 7It may be performed in a high vacuum of the order of torr or less, or may be performed while flowing a high purity gas. Thereafter, a source gas is introduced into the reaction chamber, and a film is deposited. After the deposition, the reaction chamber is purged with vacuum or nitrogen, and then the turbo molecular pump is stopped. After the turbo molecular pump is stopped, the gate valve 1304 is closed, an inert gas such as nitrogen is introduced into the reaction chamber, the pressure is returned to a predetermined pressure such as atmospheric pressure, and the substrate is taken out.
[0102]
  When the magnetic bearing type turbo molecular pump described in Example 9 is used as the turbo molecular pump 106, the turbo molecular pump intake hole directly faces the substrate as it is, so that the effective exhaust velocity in the vicinity of the substrate in the reaction chamber. Se is exactly the turbo pump speedSp Inequally,
  Se = Sp = 22001 / sec
And become the maximum. Thus, the reaction chamber equilibrium pressure when about 100 SCCM of nitrogen is passed through the reaction chamber is 6.9 × 10 6. FourIt becomes torr, and ultra-low pressure deposition becomes possible. This is a lower pressure than that of Example 9, so that a higher quality silicon film can be obtained at a lower temperature. In addition, a thin film semiconductor device having excellent characteristics can be stably produced by a low temperature process.
[0103]
Furthermore, in the present invention, the pressure in the reaction chamber is adjusted depending on the pressure at the exhaust port of the turbo molecular pump. For example, when the raw material gas flow rate is 100 SCCM, the pressure in the reaction chamber is 6.9 × 10 6 as described above. FourIt can be set in a wide range from torr to 1.6 torr, and it is possible to form various deposited films with a single CVD system.
[0104]
As described above, according to the present invention, the LPCVD apparatus has an effective exhaust speed of 10 SCCM / mtorr or more in the reaction chamber, or the pressure in the reaction chamber is 10 within 10 minutes after the start of steady operation of the vacuum exhaust apparatus. FiveBy depositing a semiconductor film such as a silicon film using an LPCVD system that is less than torr, the quality of the semiconductor film is greatly improved, thereby dramatically improving the characteristics of the thin film semiconductor device and reducing the manufacturing time.・ Stable mass production was realized. In addition, according to the present invention, the crystalline silicon film forming temperature has been lowered by about 40 ° C., and it has become possible to produce a conductive silicon film at a low temperature. Accordingly, when the present invention is applied to an active matrix liquid crystal display or the like, an inexpensive glass substrate can be used, and when it is applied to other electronic devices, element deterioration due to heat is reduced. Further, according to the CVD apparatus of the present invention, it is possible to form a film in a much wider pressure range than before, and various films can be formed with one CVD apparatus. Thus, the present invention has a great effect of realizing high performance and low price of an active matrix liquid crystal display device and an electronic device such as an integrated circuit.
[0105]
【The invention's effect】
As described above, the present invention provides a method for forming a semiconductor film such as a silicon film applicable to a thin film semiconductor device, an integrated circuit, a solar cell, a charge coupled device, and the like, and a low-pressure chemical vapor deposition apparatus and an active device used for forming the semiconductor film. It is suitable for a thin film semiconductor device using a semiconductor film adapted to a matrix liquid crystal display or the like.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of a low pressure chemical vapor deposition apparatus (LPCVD apparatus) according to the present invention.
FIGS. 2A to 2E are element cross-sectional views in a typical process of manufacturing a thin film semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram showing the effect of the present invention.
FIG. 4 is a diagram showing the effect of the present invention.
FIG. 5 is a diagram showing the effect of the present invention.
FIG. 6 is a diagram showing the effect of the present invention.
FIG. 7 is a diagram showing an outline of a conventional low pressure chemical vapor deposition apparatus (LPCVD apparatus).
FIGS. 8A to 8D are cross-sectional views of elements in respective steps of manufacturing a thin film semiconductor device according to an embodiment of the present invention.
FIG. 9 is a diagram showing an outline of a manifold portion of an LPCVD apparatus according to the present invention.
FIG. 10 is a view showing an outline of a manifold portion of a conventional LPCVD apparatus.
FIG. 11 is a diagram showing an outline of a vertical reduced pressure chemical vapor deposition apparatus (vertical LPCVD apparatus) according to the invention.
FIG. 12 is a diagram showing an outline of a vertical reduced pressure chemical vapor deposition apparatus (vertical LPCVD apparatus) according to the present invention.
FIG. 13 is a diagram showing an outline of a chemical vapor deposition apparatus (CVD apparatus) according to the present invention.
FIG. 14 is a diagram showing an outline of a chemical vapor deposition apparatus (CVD apparatus) according to the present invention.
FIG. 15 is a diagram showing an outline of a chemical vapor deposition apparatus (CVD apparatus) according to the present invention.
[Explanation of symbols]
101 ・ ・ ・ Reaction chamber
102 ... Board
103 ... Gas introduction pipe
104 ... Manifold
105 ... Gate valves and conductance valves
106 ・ ・ ・ Turbo molecular pump
107 ・ ・ ・ Rotary pump
108 ・ ・ ・ Heater
109 ・ ・ ・ Turn table
201 ... Board
202 ・ ・ ・ Base protective film
203 ... Source / drain region
204 ・ ・ ・ Silicon film
205 ・ ・ ・ Channel silicon film
206 ・ ・ ・ Gate insulation film
207 ... Gate electrode
208 ・ ・ ・ Interlayer insulation film
209 ... Source / drain extraction electrode
703 ... Exhaust pipe
705 ... Exhaust pipe to vacuum exhaust system
706 ・ ・ ・ Mechanical booster pump
801 ... Board
802: Undercoat protective film
803 ... Semiconductor film
804 ... Gate insulation film
805 ... Gate electrode
806 ... Cap layer
807 ... Channel area
808 ・ ・ ・ Source / drain region
809 ... Interlayer insulating film
810 ... Source / drain extraction electrode
901 ・ ・ ・ Reinforcement beam
902 ・ ・ ・ Vacuum exhaust air intake hole
903 ... Substrate insertion slot
904 ... Manifold intake section
1103 ・ ・ ・ Gas inlet
1206 ... Magnetic bearing type turbo molecular pump
1304 ・ ・ ・ Gate valve
1305 ・ ・ ・ Gas flow regulator
1307 ・ ・ ・ Second vacuum pump
1310 ・ ・ ・ Pressure gauge
1405 ... Conductance valve
1505 ・ ・ ・ Pressure regulator
1510 ... Pressure gauge

Claims (3)

少なくとも反応室とターボ分子ポンプとゲート・バルブと該ターボ分子ポンプの排気口側に接続された第二の真空ポンプを具備する化学気相堆積装置(CVD装置)
に於いて、該ターボ分子ポンプが該反応室に直接設置されて居り、且つ該ゲート・バルブが該ターボ分子ポンプと該第二の真空ポンプの間に設置されて居り、前記ターボ分子ポンプの吸気穴が基板に面している事を特徴とする化学気相堆積装置。
Chemical vapor deposition apparatus (CVD apparatus) comprising at least a reaction chamber, a turbo molecular pump, a gate valve, and a second vacuum pump connected to the exhaust port side of the turbo molecular pump
The turbo molecular pump is installed directly in the reaction chamber, and the gate valve is installed between the turbo molecular pump and the second vacuum pump, A chemical vapor deposition apparatus characterized in that the hole faces the substrate.
反応室内の圧力を調整する為の圧力調整装置がゲート・バルブと第二の真空ポンプの間に設置されて居る事を特徴とする請求項1記載の化学気相堆積装置。2. The chemical vapor deposition apparatus according to claim 1, wherein a pressure adjusting device for adjusting the pressure in the reaction chamber is provided between the gate valve and the second vacuum pump. 請求項1及び請求項2のいずれかに記載の化学気相堆積装置(CVD装置)
を用いて半導体膜を形成することを特徴とする半導体膜の製造方法。
A chemical vapor deposition apparatus (CVD apparatus) according to any one of claims 1 and 2.
A method of manufacturing a semiconductor film, comprising forming a semiconductor film using
JP2001028240A 1991-07-16 2001-02-05 Chemical vapor deposition apparatus and semiconductor film manufacturing method using the same Expired - Lifetime JP3786580B2 (en)

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JP3-175393 1991-07-16
JP17539391 1991-07-16
JP23340791 1991-09-12
JP3-233407 1991-09-12
JP28436091 1991-10-30
JP3-284360 1991-10-30
JP4-122135 1992-05-14
JP12213592 1992-05-14
JP2001028240A JP3786580B2 (en) 1991-07-16 2001-02-05 Chemical vapor deposition apparatus and semiconductor film manufacturing method using the same

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