JP3786638B2 - Frame data identification device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a frame data identification device for identifying frame data in which specified data is inserted at a specified position from serially input frame data, and identifies high-speed frame data with a small hardware configuration. It relates to technology to make it possible.
[0002]
[Prior art]
For example, when performing a network test, output test frame data to the network under test, receive it from the network, compare the transmitted frame data with the content of the received frame data, or transfer delay time. Etc. are detected.
[0003]
When performing such a test, in order to distinguish the other frame data transmitted on the network from the test frame data, the predetermined data is inserted and transmitted at a predetermined position in the frame. Then, it is checked whether or not predetermined data is inserted at a predetermined position of the input frame data to identify whether or not it is frame data for testing.
[0004]
As a frame data identification device used for such a purpose, it is necessary to extract data inserted at an arbitrary position of the frame data. However, such processing is performed in real time on high-speed serial frame data. Since this is difficult, usually, serially input frame data is converted into parallel data having a predetermined bit width, data to be compared is extracted, and the extracted data is compared with reference data.
[0005]
Here, when the head position of the data to be compared matches the most significant bit of one parallel data and the data to be compared is in one parallel data, the parallel data and the reference data However, the start position of the data to be compared does not match the most significant bit of one parallel data, and the data to be compared exists across two or more parallel data If to have such can not be simply compared with the reference data and the parallel data.
[0006]
For this reason, conventionally, the parallel data including the data to be compared is subjected to a shift process, and then compared with the reference data.
[0007]
FIG. 4 shows a configuration of a conventional frame data identification device 10 used for such a purpose.
[0008]
4, an interface 11 is connected to the network 1, for example, takes in frame data D that is serially transmitted over the network 1, converts it into parallel data d (1), d (2),. To do. Here, the bit width W of each parallel data d (i) output from the interface 11 is set to one-multiple of the frame length to be captured.
[0009]
The position specifying means 12 is for specifying the head position P of the data to be matched in the input frame data. For example, the position specifying means 12 is specified by the number of bits or the number of bytes from the head of the frame data.
The reference data setting means 13 is for setting reference data dr that is a criterion for coincidence determination.
[0010]
The data extracting unit 14 extracts the data dx at the position specified by the position specifying unit 12 from the parallel data d (i) output from the interface 11.
[0011]
The extracted data shift means 15 is arranged when the position designation means 12 makes a position designation such that the arrangement of the data dx extracted by the data extraction means 14 is different from the input order in the serial state of the data dx. The position designation means 12 performs position designation so that the arrangement of the data dx extracted by the data extraction means 14 matches the input order in the serial state of the data dx. Sometimes, the extracted data dx is output as it is.
[0012]
The determination unit 16 determines whether or not the pattern of the reference data dr set by the reference data setting unit 13 matches the pattern of the data dx ′ output from the extracted data shift unit 15.
[0013]
Next, the operation of the frame data identification device 10 will be described. Here, a case where the bit length of the reference data dr is equal to the bit width W of the parallel data d (i) will be described.
[0014]
For example, when the frame data D shown in FIG. 5A is input in order from the bit data b (0), the interface 11 receives, for example, a 128-bit width (W = 128) as shown in FIG. 5B. Parallel data d (1), d (2),... Are sequentially output.
[0015]
Here, a position P equal to an integer multiple of the output bit width W (128 bits in this case) of the parallel data d (i) from the beginning of the frame, for example, P = 128 in bit units is specified by the position specifying means 12 in advance. 5, the data extraction unit 14, as shown in FIG. 5C, out of the parallel data output from the interface 11, the P + 1 bit, that is, the 129th bit data b (128) to 256 (P + L). ) The second parallel data d (2) in which the bit data b (255) up to the bit is arranged in the input order is extracted and output to the extracted data shift means 15.
[0016]
Since the arrangement of the extracted data dx (= d (2)) coincides with the input order at the time of serial input of the data dx, the extracted data shift means 15 receives the data as shown in (d) of FIG. Data dx ′ equal to the extracted data dx is output to the determination means 16 to determine whether or not it matches the reference data dr.
[0017]
Further, a position P that is not equal to an integer multiple of the output bit width W (128 bits in this case) of the parallel data d (i) from the head of the frame, for example, P = 8 in bit units is specified by the position specifying means 12 Then, when the same frame data D is input as shown in FIG. 6A and 128-bit parallel data d (i) is output from the interface 11 as shown in FIG. 6B, As shown in FIG. 6C, the data extracting unit 14 includes the 9th (= P + 1) th bit to the 128th bit included in the first parallel data d (1) among the parallel data output from the interface 11. Bit data from bit 129 to bit 136 (= P + L) included in bit data b (8) to b (127) and second parallel data d (2) (128) outputs ~b and the 128-bit data consisting of (135) as the extraction data dx.
[0018]
In this extracted data dx, bit data b (128) to b (135) inputted later are arranged higher than bit data b (8) to b (127) inputted at the time of serial input. The input order in the serial state is not consistent.
[0019]
Therefore, the extracted data shift means 15 cyclically shifts this extracted data dx by 8 bits to match the input order in the serial state, as shown in FIG. Data dx ′ is output to determination means 16.
[0020]
The determination unit 16 determines whether or not the shifted extracted data dx ′ matches the reference data dr.
[0021]
In the frame data identification device 10 configured as described above, when the arrangement of the extracted data dx output from the data extracting unit 14 does not match the input order of the serial state, the extracted data is shifted to input the serial state. Since the comparison with the reference data dr is performed after matching in order, it is possible to determine the coincidence of data at an arbitrary position in the frame.
[0022]
[Problems to be solved by the invention]
However, in the conventional frame data identification apparatus 10 that performs the shift process on the extracted data dx as described above, it is necessary to perform the shift process by the extracted data shift means 15 every time frame data is input, and the parallel data d ( If the output bit width of i) is increased, the time for the shift process becomes longer, it is impossible to cope with high-speed frame data, and the identification becomes difficult.
[0023]
Further, there is a problem that the hardware configuration of the extracted data shift means 15 becomes enormous as the output bit width increases.
[0024]
An object of the present invention is to solve this problem and provide a frame data identification device capable of identifying high-speed frame data with a small hardware configuration.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, the frame data identification device of the present invention provides:
In the frame data identification device for identifying the frame data in which the designated data is inserted at the designated position among the serially inputted frame data,
An interface (21) for outputting a time series frame data the serial input is divided into parallel data of a predetermined bit width,
Position specifying means (22) for specifying a position in the frame data;
Reference data setting means (23) for setting reference data;
Data extraction means (24) for extracting, from the parallel data output from the interface, data at a position designated by the position designation means by the number of bits equal to the reference data ;
When the position designation means makes a position specification such that the data arrangement extracted by the data extraction means matches the input order at the time of serial input, the reference data arrangement set by the reference data setting means is not changed. output to, when said sequence of data that the data extracting means for extracting is made the input order is different from such a position specified at the time of the serial input by said position specifying means, in accordance with the sequence of data to which the data extracting means extracts Reference data array changing means (25) for changing and outputting the reference data array set by the reference data setting means ;
Are as characterized by a determination means for determining whether or not the pattern data extracted by the pattern and the data extraction means of the output reference data is consistent (26) from the reference data sequence changing means .
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a frame data identification device 20 to which the present invention is applied.
[0027]
In FIG. 1, an interface 21 is connected to, for example, the network 1, takes in frame data D that is serially transmitted over the network 1, converts it into parallel data d (1), d (2),. To do. Here, the bit width W of each parallel data d (i) output from the interface 21 is set to one-multiple of the bit length of the frame to be captured.
[0028]
The position specifying means 22 is for specifying the head position P of the data to be matched in the input frame data. For example, the position specifying means 22 is specified by the number of bits or the number of bytes from the head of the frame data.
The reference data setting means 23 is for setting reference data dr that is a criterion for coincidence determination.
[0029]
The data extracting unit 24 extracts the data dx at the position specified by the position specifying unit 22 from the parallel data d (i) output from the interface 21.
[0030]
The reference data arrangement changing means 25 is configured to perform reference data setting means when the position designation means 22 performs position designation such that the arrangement of the data dx extracted by the data extraction means 24 is different from the input order at the time of serial input of the data dx. 23 changes the arrangement of the reference data dr set in accordance with the arrangement of the extracted data dx and outputs it to the determination means 26. Here, the arrangement is changed by cyclic shift processing on the reference data dr. The case where it does is demonstrated.
[0031]
In addition, when the position designation unit 22 performs position designation so that the arrangement of the data dx extracted by the data extraction unit 24 matches the input order at the time of serial input of the data dx, it is set by the reference data setting unit 23. The reference data dr is output to the determination means 26 as it is.
[0032]
The determination unit 26 determines whether or not the pattern of the reference data dr ′ output from the reference data arrangement changing unit 25 matches the pattern of the data dx output from the data extraction unit 25.
[0033]
Next, the operation of the frame data identification device 20 will be described. Here, a case where the bit length of the reference data dr is equal to the bit width W of the parallel data d (i) will be described.
[0034]
For example, when the frame data D shown in FIG. 2A is sequentially input from the bit data b (0), the interface 21 receives, for example, a 128-bit width (W = 128) as shown in FIG. 2B. Parallel data d (1), d (2),... Are sequentially output.
[0035]
Here, a position P equal to an integer multiple of the output bit width W (128 bits in this case) of the parallel data d (i) is designated in advance by the position designating means 22, for example, P = 128 in bit units. 2, the data extraction means 24, as shown in FIG. 2C, out of the parallel data output from the interface 21, the bit data b (128) to 256 (P + L) of the P + 1 bit, that is, the 129 bit. ) The second parallel data d (2) in which the bit data b (255) up to the bit is arranged in the input order is extracted and output to the determination means 26.
[0036]
The arrangement of the extracted data dx (= d (2)) matches the input order when the data dx is serially input.
[0037]
In this way, when the position designation is made such that the bit arrangement of the extracted data dx matches the input order in the serial state, the reference data arrangement changing means 25 sets the reference data setting as shown in FIG. Data dr ′ equal to the reference data dr set by the means 23 is output to the determining means 26, and the determining means 26 determines whether or not the pattern of the data dr ′ and the extracted data dx match. The reference data dr is composed of bit data br (0) to br (127).
[0038]
Further, a position P that is not equal to an integer multiple of the output bit width W (128 bits in this case) of the parallel data d (i) from the beginning of the frame, for example, P = 8 in bit units is specified by the position specifying means 22 in advance. In the state, when the same frame data D is input as shown in FIG. 3A, and parallel data d (i) having a 128-bit width is output from the interface 21 as shown in FIG. 3B. As shown in FIG. 3 (c), the data extraction means 24 is 128 bits from the 9th (= P + 1) th bit included in the first parallel data d (1) among the parallel data output from the interface 21. Bit data from bit 129 to bit 136 (= P + L) included in bit data b (8) to b (127) up to the eye and second parallel data d (2) And outputs the 128-bit data consisting of the data b (128) ~b (135) as the extraction data dx.
[0039]
In this extracted data dx, bit data b (128) to b (135) inputted later are arranged higher than bit data b (8) to b (127) inputted earlier at the time of serial input. And the input order in the serial state does not match.
[0040]
In this way, when the position designation is made such that the bit sequence of the extracted data dx does not match the input order when it is input in the serial state, the reference data sequence changing means 25 is as shown in FIG. Then, the reference data dr set by the reference data setting means 23 is cyclically shifted by 8 bits to match the extracted data dx array, and the shifted reference data dr ′ is output to the determination means 26.
[0041]
The determination unit 26 determines whether or not the shifted reference data dr ′ matches the extracted data dx.
[0042]
As described above, in the frame data identification device 20 of the embodiment, when the position designation is made such that the arrangement of the extraction data dx output from the data extraction unit 24 does not match the input order of the serial state, the extraction data dx The reference data dr is shifted in accordance with the arrangement, and the shifted reference data dr ′ is compared with the extracted data dx.
[0043]
This eliminates the need for shift processing on the extracted data dx, greatly reduces the processing time of the entire apparatus, and enables high-speed frame data identification.
[0044]
The shift process for the reference data dr need only be performed when the position P designated by the position designating unit 22 is changed, can be realized by software processing, and the entire apparatus can be configured on a small scale.
[0045]
In the above description, when the position designation is made such that the sequence of the extracted data dx output by the data extracting unit 24 does not match the input order of the serial state, the reference data sequence changing unit 25 Although the reference data dr is shifted in accordance with the array, the array changing process for the reference data dr only needs to correspond to the extraction structure of the data extracting unit 24. In addition to the cyclic shift process described above, Alternatively, data replacement processing or a combination of shift processing and replacement processing may be used.
[0046]
【The invention's effect】
As described above, the frame data identification device according to the present invention uses the extracted data array when the position of the data array extracted by the data extracting means is specified so as not to match the input order of the serial state. At the same time, the arrangement of the reference data is changed, and the reference data with the changed arrangement is compared with the extracted data.
[0047]
This eliminates the need for shift processing on the extracted data, greatly reduces the processing time of the entire apparatus, and enables high-speed frame data identification.
[0048]
The arrangement changing process for the reference data may be performed only when the position specified by the position specifying unit is changed, and can be realized by software processing, and the entire apparatus can be configured on a small scale.
[Brief description of the drawings]
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the embodiment. FIG. 3 is a diagram for explaining the operation of the embodiment. FIG. 5 is a diagram for explaining the operation of the conventional apparatus. FIG. 6 is a diagram for explaining the operation of the conventional apparatus.
DESCRIPTION OF SYMBOLS 1 ... Network, 20 ... Frame data identification device, 21 ... Interface, 22 ... Position designation means, 23 ... Reference data setting means, 24 ... Data extraction means, 25 ... Reference data arrangement change means, 26 …… Judgment means

Claims (1)

In the frame data identification device for identifying the frame data in which the designated data is inserted at the designated position among the serially inputted frame data,
An interface (21) for outputting a time series frame data the serial input is divided into parallel data of a predetermined bit width,
Position specifying means (22) for specifying a position in the frame data;
Reference data setting means (23) for setting reference data;
Data extraction means (24) for extracting, from the parallel data output from the interface, data at a position designated by the position designation means by the number of bits equal to the reference data ;
When the position designation means makes a position specification such that the data arrangement extracted by the data extraction means matches the input order at the time of serial input, the reference data arrangement set by the reference data setting means is not changed. output to, when said sequence of data that the data extracting means for extracting is made the input order is different from such a position specified at the time of the serial input by said position specifying means, in accordance with the sequence of data to which the data extracting means extracts Reference data array changing means (25) for changing and outputting the reference data array set by the reference data setting means ;
Characterized by comprising a determining means for determining whether a pattern of data extracted matches the pattern and the data extraction means of the output reference data (26) from the reference data sequence changing means Frame data identification device.

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