JP3789011B2 - Parallel computer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a parallel computer having a resource shared by these processors in a computer system having a plurality of processors, and in particular, to a resource in a parallel computer in which a plurality of nodes each having a processor are coupled via a network. The present invention relates to a configuration method of a parallel computer distributed and arranged in a plurality of nodes.
[0002]
[Prior art]
As a media server that supplies a large amount of media information, a parallel computer composed of a plurality of processors or a client-server type distributed processing system composed of a plurality of computers is known. In this specification, a computer that executes distributed processing of a distributed processing system in order to make a distinction between a plurality of processors that constitute a parallel computer and a plurality of computers that constitute a client-server type distributed processing system. Elements are called “nodes”.
[0003]
Media information is often distributed and held in a plurality of disk devices in a parallel computer, and an access processing request from a user is processed by a cooperative operation of a plurality of nodes.
[0004]
For example, as an example of a media server, there is a video on demand server that stores a large amount of video information such as a movie and supplies video information to a plurality of users. The video information has a feature that when the supply time is extended, the image is interrupted or the screen flickers. For this reason, shortening the delay time is an important issue.
[0005]
By the way, regarding the video on demand processing, it may be necessary to consider the reduction of the delay time. It is an access pattern to media information. That is, the video-on-demand server must provide video information at a high speed regardless of whether a plurality of users access different titles simultaneously or access the same title.
[0006]
In order to solve the former problem, video information may be distributed to a plurality of nodes for each title. Thereby, the load can be distributed to a plurality of nodes. The user may communicate with the node storing the title he / she wants to see and supply video data. If a plurality of titles requested simultaneously by the user are evenly distributed to a plurality of nodes, the processing load can be distributed.
[0007]
However, this configuration cannot solve the latter problem. In the system configuration described above, when accesses are concentrated on the same title, the load is applied only to the node storing the title even if the number of nodes constituting the distributed system is large. This does not change the performance of a system consisting of one node.
[0008]
Therefore, a method is often used in which one video title is divided into a plurality of cell data, and the cell data is distributed and arranged on a plurality of disks in accordance with a distribution condition such as a hash function. This is called “striping”. For example, see Reference 1: “Nikkei Electronics” No. 602, No. 1994.2.28, pages 13-14. Extending this striping from a disk to a node and distributing the same title to a plurality of nodes is called “inter-striping”. Thereby, even when a plurality of users access the same title, the load can be distributed to a plurality of nodes, and the processing performance of the distributed system can be improved.
[0009]
[Problems to be solved by the invention]
However, when the conventional inter-node striping method is applied to a video-on-demand server, the following problem occurs.
[0010]
A node that supplies video data to one user (referred to as an interface node) must guarantee the continuity and order of the video data, and collect cell data stored in a distributed manner by striping between nodes. Must be supplied to the user.
[0011]
However, when TCP / IP is used as a data exchange method often used in a distributed processing system, software processing such as interrupt and acknowledge return is required every time a message storing transferred cell data arrives. is there. This software processing interferes with the user interface processing originally performed by the interface node. In addition, since this overhead increases in proportion to the number of nodes that perform striping between nodes, increasing the number of data supply nodes in order to improve performance makes the interface nodes busy with cell arrival confirmation, which further hinders user interface processing. As a result, the quality of user service deteriorates.
[0012]
In addition, since the video information is large-scale, for example, when watching a two-hour movie, the data supply performance from the node storing the data to the interface node is fast enough not to make the user feel the video is interrupted. There must be. Therefore, it is necessary to continuously supply data from the node storing the data to the interface node. (Hereinafter referred to as stream processing.) In order to realize this stream processing, it is necessary to perform flow control on the data receiving side and the sender side.
[0013]
As a flow control method, TCP / IP generates an interrupt every time a packet is received, and the OS (operating system) calculates the capacity of the reception buffer and returns it as an acknowledge. Reference 2: “Design and Implementation of UNIX 4.3 BSD”, pages 374 to 397; J. et al. Leffler et al. (1991).
[0014]
However, such a flow control method has the following problems. As the number of data supply nodes that one interface node has to deal with increases due to inter-node striping, the number of times flow control information is returned to the transmission node increases, impeding the user interface processing that is the original processing. End up.
[0015]
Therefore, the first object of the present invention is that the divided data gathered when accessing resources (data such as movie information, and processes etc. are also considered as data) distributed to a plurality of nodes. It is to provide a parallel computer that can be confirmed at high speed.
[0016]
A second object of the present invention is to provide a parallel computer capable of high-speed flow control for data transfer between nodes.
[0017]
[Means for Solving the Problems]
In order to achieve the first object, a parallel computer of the present invention interconnects a plurality of nodes each having at least one processor and the nodes for exchanging messages between the plurality of nodes. Node having at least one resource that can be used by the plurality of nodes and means for dividing the resource into a plurality of nodes and making an access request to the resource Means for storing whether or not an access result is returned in response to a series of access requests when a series of access requests are made to a plurality of nodes that store the resource in a divided manner (referred to as a flag) And the node that has received the access request returns the access result together with the flag when returning the access result to the access request. In order to record that the own node has returned the access result, the node having designated the flag and the means for designating the recording method for the flag. When the result is received, the flag indicated by the means for specifying the flag to be attached is recorded by the means specified by the recording method for the flag, and the flag is answered from all nodes. And a circuit for generating an interrupt in the processor when it is determined that there is a response from all nodes.
[0018]
In order to achieve the second object, the parallel computer of the present invention mutually connects a plurality of nodes each having at least one processor and the nodes for exchanging messages between the plurality of nodes. In a parallel computer comprising a network to be connected, the parallel computer has at least one resource that can be used by the plurality of nodes, the node having a first node having means for directly accessing the resource, and direct access There is a second node that cannot be used, and the second node has means for storing a plurality of access results when the resource is accessed, and the first node is a free number of the access result storage means. And a circuit for reducing the number of vacancies stored in the storage means when a result of the access is returned to the second node And when the second node releases the access result storage means by using the access result, the number of empty spaces stored in the means for storing the empty number in the first node. The first node has a circuit for determining whether or not the access result storage means of the second node has a vacancy, and the result of the vacancy judgment is not vacant Means for delaying the response of the access result.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the parallel computer according to the present invention will be described in more detail with reference to the embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar items. Hereinafter, one example of the embodiment will be referred to as an example.
[0020]
(1) Examples
FIG. 1 shows a parallel computer according to the first embodiment. In this parallel computer, a plurality of nodes 2 are connected by a network 1, and each node 2 includes at least one processor 24 and a disk device 25, and data distributed by inter-node striping is stored in the disk device 25. Is retained. Each data can be accessed only from a node (data supply node) that holds the data, and another node (data consumption node) that wants to access this data makes a data supply request to this data supply node.
[0021]
In this parallel computer, all the nodes have the same configuration and can perform the same processing. In this embodiment, in order to make the explanation easy to understand, in FIG. The supply node, node # 2, is positioned as a data consumption node. A case where the node # 2 accesses data distributed to the nodes # 0 and # 1 will be described.
[0022]
In the first embodiment, when the node # 2 reads the data 35 distributedly stored in the disk devices 25 of the node # 0 and the node # 1, both the data transferred by the node # 0 and the data transferred by the node # 1 are It is the first feature that it is determined at high speed that they are aligned. The data consumption node has a circular buffer 38 so that data can be continuously received from the data supply node. The second feature is that the data supply node can determine the free capacity of the circular buffer 38 at high speed. For these two, the node 2 is provided with an event control circuit 500, a flag 37 indicating the arrival of data to the circular buffer, a flag register 58 for operating this flag, and a flow control register group 52. The circular buffer 38 is provided for performing data transfer from the data supply node and processing for providing a service to the user using the transferred data by the data consumption node, and has a configuration as shown in FIG. . That is, a buffer area for storing data transferred from node # 0 and node # 1, node [m] for node # 0, [m] for node # 1, and a flag [ m]. The data supply node transfers data to the data consumption node in order from m = 0, and the data consumption node consumes in order from m = 0.
[0023]
The flag register 58 is a register that temporarily stores the flag 37 on the local memory when the node 2 receives the message 11.
[0024]
The flow control register group 52 is a register that manages the free capacity of the circular buffer 38 and is used in the data supply node. The free capacity of the circular buffer 38 of the node to which data is to be transferred, here the data consuming node, is stored. In this embodiment, when the data supply node transfers the data to the data consumption node, the corresponding flow control register is decreased, and when the data consumption node finishes processing the transferred data, the corresponding flow control register of the data supply node It is characterized by increasing. As a result, the data supply node can determine that the data can be transferred if the corresponding flow control register is greater than 0, and the data consumption node can flow when the data is consumed, not when the message arrives. Control can be performed. Therefore, the data consumption node can prevent useless interruption to service processing for the user.
[0025]
Hereinafter, the circuit of this embodiment and details of its operation will be described.
[0026]
(Node 2)
As shown in FIG. 1, each node 2 includes a processor 24 that executes a data supply program 31 and a data consumption program 32, a local memory 23, a disk device 25 that stores data 35 distributed to the nodes, and the present embodiment. The transmission control circuit 21 for performing characteristic high-speed flow control processing and the reception control circuit 22 are configured. This parallel computer is a so-called distributed memory type parallel computer, and the local memory 23 cannot be accessed from other nodes, and only the node to which the local memory belongs can be accessed. The local memory 23 stores a program executed at the node and data used or generated by the program. Further, in this embodiment, the data supply node stores transfer data 36 in which data 35 read from the disk device 25 is temporarily stored. On the other hand, the data consuming node is provided with a circular buffer 38 and its flag 37 for receiving data.
[0027]
Each circuit in this node is connected to the system bus 26 and can be accessed by the memory mapped IO method without being distinguished from the local memory 23 by a memory access instruction such as a load instruction or a store instruction from the processor 24. it can.
[0028]
The transmission control circuit 21 includes a message generation circuit 41, a transmission parameter storage register 42, and a transmission status register ST43. The reception control circuit 22 includes an input buffer 51, a memory access circuit 60, and a flow control register group 52. The memory access circuit 60 writes the data received from the network to the local memory 23, reads the flag 37, updates it, and writes it back. The event control circuit 500 includes a coincidence control circuit 53 that determines whether or not two inputs are the same, a magnitude determination circuit 54 that compares the magnitudes of the two inputs, addition, subtraction, bit set, and bit reset of the two inputs. , And an AND circuit 59.
[0029]
(Network 1)
The network 1 transmits the message to the node indicated by the node number Nad of the message 11 although the form is not particularly defined. For example, it may be the same as that described in Japanese Patent Application No. 6-53405.
[0030]
Hereinafter, a procedure in which the node # 2 reads the media data 35 stored in the disks of the node # 0 and the node # 1 will be described.
[0031]
(Initialization of flow control register group 52)
Each node 2 initializes the flow control register group 52 to 0 when the system is activated.
[0032]
(Initialization of circular buffer 38)
The node # 2 reserves a circular buffer 38 for reading media data and a flag 37 indicating the completion of reading in the local memory 23, and 0 is written in the flag 37 as an initial value. As shown in FIG. 2, the circular buffer 38 has (m + 1) sets of the data area for the node # 0, the data area for the node # 1, and their flags as one set. As will be described later, the node # 0 and the node # 1 use the head of the circular buffer 38 as a data transfer destination and proceed to the (m + 1) th set. Next, it is used by circulating to the 0th set. By using it in such a manner, it is possible to perform processing such as reading media data larger than the circulation buffer 38 and displaying it on a display device, for example.
[0033]
(Read request to node # 0 and node # 1)
The node # 2 receives the title of the media data to be read to the node # 0, the address of the area for the node # 0 of the received circular buffer 38, the address of the flag, the size (m + 1) of the circular buffer 38, and the flow control. R #, which is the ID of the flow control register used in the above, is transmitted via the network. Although not shown in FIG. 1, a conventional technique such as Ethernet may be used. Similarly, the read request is transmitted to the node # 1. Further, node # 2 transmits the number of inter-node stripes characteristic in the present embodiment to node # 0 and node # 1. Here, it is 2 because it is divided into node # 0 and node # 1. In general, n is divided into n nodes. At this time, 0 is set in the flow control register to be used. This seems to be equivalent to the fact that the circular buffer 38 has no free space from the data supply program 31 of the node # 0. Therefore, node # 0 and node # 1 stop supplying data and wait for the flow control register to become larger than zero.
[0034]
(Read start instruction to node # 0 and node # 1)
At this stage, the node # 0 and the node # 1 are on standby because they recognize that the circular buffer 38 of the node # 2 is free. Therefore, the node # 2 issues a read start instruction to the node # 0 and the node # 1 according to the following procedure when the preparation of the data consumption program 32 of the own node is completed. More specifically, the start instruction is to set the free capacity of the circular buffer 38 in the flow control registers of the node # 0 and the node # 1.
[0035]
That is, the processor 24 sets the next value in the transmission parameter storage register 42 via the system bus 26 and transmits the message to the node # 0 and the node # 1.
[0036]
Nad: = identifier of node # 0 or node # 1
CTL (R): = 1 [indicating that the message is addressed to a flow control register group]
CTL (R #): = destination flow control register identifier
Dad: = 0 [not referenced in this message]
Dln: = 0 [not referenced in this message]
Fad: = 0 [not referenced in this message]
Int: = 0 [not referenced in this message]
D0: = 0 [not referenced in this message]
D1: = (m + 1) [capacity of the circular buffer 38]
Ct0: = 0 [not referenced in this message]
Ct1: = code indicating value setting
Tad: = 0 [not referenced in this message]
By setting the transmission parameters in this way, the message generation circuit 41 generates the message 11 and sends it to the network 1. Then, a code indicating completion of transmission is written in the transmission status register ST43.
[0037]
The network 1 delivers the message to the node indicated by Nad of the message 11, here, the node # 0 or the node # 1.
[0038]
Next, operations of node # 0 and node # 1 that have received the message will be described.
[0039]
In the node 2, the message 11 received from the network 1 is temporarily stored in the input buffer 51, and each field is cut out. Since this message is CTL (R) = 1, it is determined that this message is an update request to the flow control register. Further, since Ct1 is “value setting”, the event control circuit 500 controls the selector 57 to select D1, and the flow control register group 52 sets D1 to D1 for the register indicated by CTL (R #). Write the stored (m + 1).
[0040]
As a result, (m + 1) is set as the free capacity of the circular buffer 58 in the flow control register [R #].
[0041]
(Data transfer from the data supply node)
On the other hand, in the processor 2 of the node, the data supply program 31 monitors the flow control register [R #] via the system bus 26 and waits until it becomes larger than zero. Since the flow control register [R #] is (m + 1) by the read request from the node # 2, the data supply program 31 performs the data transfer process according to the following procedure.
[0042]
The processor 24 reads data 35 from the disk device 25 via the system bus 26 and stores it as transfer data 36 in the local memory 23. Then, this data is transferred to the node # 2.
[0043]
That is, the processor 24 sets parameters in the transmission parameter storage register 42 through the system bus 26 as follows.
[0044]
Nad: = identifier of node # 2
CTL (R): = 0 [indicating that it is not addressed to the flow control register but is addressed to memory]
Dad: = Start address of data storage area [i] for node # 0 (or node # 1), i = 0 at the very beginning.
Dln: = data length [same as the capacity of the data storage area [i] above]
Fad: = first address of flag storage area [i], i = 0 at the very beginning.
Int: = 1 [indicates that an interrupt will be generated]
D0: = 2 [number of data stripes between nodes]
D1: = 1 [represents flag increment]
Ct0: = 0 [indicating that coincidence determination is selected]
Ct1: = code indicating addition
Tad: = start address of transfer data 36
When the processor writes these parameters, the message generation circuit 41 generates the message 11 and sends it to the network 1. At this time, the transfer data field of the message 11 is packed with the head address stored in the Tad, that is, the transfer data 36.
[0045]
(Updating the flow control register at the data supply node)
When data is transferred to the data consuming node, the data supply node updates the flow control register. That is, the processor 24 subtracts 1 from the flow control register [R #] via the system bus 26. When this result is 0, the data supply program 31 enters a standby state. Further, the data supply program 31 updates the address of the circular buffer 38 to which data is to be transferred next to the data storage area [i + 1] for the node # 0 (or node # 1) and the flag address [i + 1] for the data. To do. If these addresses are larger than the data storage area [m] and the flag area [m], respectively, it is updated to the data storage area [0] and the flag area [0] which are the leading addresses of the circular buffer. Then, these operations are repeated until all the data designated by the title is transferred to the node # 2.
[0046]
(Reception of data at the data consumption node)
Next, the operation of the node # 2 that has received the message will be described.
[0047]
In the node 2, the message 11 received from the network 1 is temporarily stored in the input buffer 51, and each field is cut out. Since this message is CTL (R) = 0, it is determined that this message is data transfer to the local memory 23. The memory access circuit 60 writes the transfer data having the length indicated by Dln of the message 11 to the start address of the data storage area of the circular buffer 38 indicated by Dad via the system bus 26. Next, the flag is updated. This is a characteristic operation in this embodiment. The memory access circuit 60 reads the contents of the flag storage area [i] from the address indicated by Fad of the message 11 and stores it in the flag register 58.
[0048]
(When data transfer to the area corresponding to the flag is the first time)
In this case, the flag stored in the flag area [i] has an initial value of 0. The event control circuit 500 selects the flag register 58 by the selector 61 because CTL (R) is 0, and inputs the flag register 58 to one of the arithmetic circuits 56. Then, D1 is input to the other input of the arithmetic circuit 56, that is, 1 here. The event control circuit 500 controls the arithmetic circuit 56 and the selector 57 and outputs the addition result of the two inputs of the arithmetic circuit 56 to the output of the selector 57 because Ct1 is a code representing addition. Here, 0 + 1 = 1. Then, it is written back to the flag register 58. Next, since the event control circuit 500 is Ct0 = 0, that is, a code indicating coincidence determination, D0, which is 2 here, is selected by the input of the coincidence determination circuit 53, and the other is selected by the selector 61. The contents of the completed flag register 58, here, 1 is input. The match determination circuit 53 outputs 0 because the two input lines do not match. For this reason, the output selected by the selector 55 becomes 0, and the output of the AND circuit 59 becomes 0. Therefore, no interrupt is generated for the processor 24. That is, if only one side of data arrives, no unnecessary interrupt is generated in the processor 24. Thereby, the effect which does not inhibit execution of a data consumption program is realizable.
[0049]
Then, the memory access circuit 60 writes the updated flag value 1 stored in the flag register 58 back to the flag storage area [i] indicated by Fad via the system bus 26.
[0050]
(When the data transfer to the area corresponding to the flag is the second)
Similarly, the flag is updated, but the value of the flag read from the flag storage area [i] of the local memory 23 is 1 this time. Accordingly, the value of the flag added with 1 by the arithmetic circuit 56 is 2, and this value is stored in the flag register 58. Since the two inputs of the coincidence determination circuit 53 are both 2 this time, the output of the coincidence determination circuit 53 is 1. Since the two inputs of the AND circuit 59 have Int of 1, 1 is output. Thus, the event control circuit 500 can interrupt the processor 24, and the processor can know that it has received usable data without waste.
[0051]
Then, the memory access circuit 60 writes the updated flag value 2 stored in the flag register 58 back to the flag storage area [i] indicated by Fad via the system bus 26.
[0052]
(Data consumption by node # 2)
When node # 2 is notified of data reception by the data reception completion interrupt received from event control circuit 500, it consumes data in the following procedure. That is, the flag 37 of the circular buffer 38 is read via the system bus 26 and an entry whose flag 37 is 2 is searched. Here, a value of 2 indicates that the data divided into the node # 0 and the node # 1 has been correctly received. The data consumption program 32 performs processing such as extracting data from the data storage area that has been correctly received and displaying the data on the display device. When the data stored in this entry is completely consumed, the area is released in the following procedure. That is, the processor 24 writes 0 in the flag storage area corresponding to the area stored in the local memory 23 via the system bus 26. This indicates that there is no valid data in the corresponding area, that is, this area is a free area. Then, a message is transmitted in the following procedure in order to inform node # 0 and node # 1 that the free space in the circular buffer 38 has increased.
[0053]
(Communication of increase in free space in circular buffer 38 by node # 2)
That is, the processor 24 sets the next value in the transmission parameter storage register 42 via the system bus 26 and transmits the message to the node # 0 and the node # 1.
[0054]
Nad: = identifier of node # 0 or node # 1
CTL (R): = 1 [indicating that the message is addressed to a flow control register group]
CTL (R #): = destination flow control register identifier
Dad: = 0 [not referenced in this message]
Dln: = 0 [not referenced in this message]
Fad: = 0 [not referenced in this message]
Int: = 0 [not referenced in this message]
D0: = 0 [not referenced in this message]
D1: = 1 [Increase in free capacity of circular buffer 38]
Ct0: = 0 [not referenced in this message]
Ct1: = code indicating addition
Tad: = 0 [not referenced in this message]
By setting the transmission parameters in this way, the message generation circuit 41 generates the message 11 and sends it to the network 1. Then, a code indicating completion of transmission is written in the transmission status register ST43.
[0055]
The network 1 delivers the message to the node indicated by Nad of the message 11, here, the node # 0 or the node # 1.
[0056]
Next, operations of node # 0 and node # 1 that have received the message will be described.
[0057]
In the node 2, the message 11 received from the network 1 is temporarily stored in the input buffer 51, and each field is cut out. Since this message is CTL (R) = 1, it is determined that this message is an update request to the flow control register. Since Ct1 is “addition”, the event control circuit 500 controls the arithmetic circuit 56 and selectors 57 and 61 to change the value 1 stored in D1 to the value stored in the flow control register [R #]. The addition result is output to the output of the selector 57. Then, the output result is written back to the flow control register [R #]. At this time, since Int is 0, the output of the AND circuit 59 is 0, and the event control circuit 500 does not generate an interrupt to the processor 24.
[0058]
As a result, the free capacity of the circular buffer 58 stored in the flow control register is increased by one.
[0059]
(End of reading)
The data supply program 31 that has read all the data designated by the title waits until the next data read request is received.
[0060]
On the other hand, when the data consuming program consumes the last data, it returns the value of the flow control register of the data supply node to the initial value 0 according to the following procedure. That is, the processor 24 sets the next value in the transmission parameter storage register 42 via the system bus 26 and transmits the message to the node # 0 and the node # 1.
[0061]
Nad: = identifier of node # 0 or node # 1
CTL (R): = 1 [indicating that the message is addressed to a flow control register group]
CTL (R #): = destination flow control register identifier
Dad: = 0 [not referenced in this message]
Dln: = 0 [not referenced in this message]
Fad: = 0 [not referenced in this message]
Int: = 0 [not referenced in this message]
D0: = 0 [not referenced in this message]
D1: = 0 [initial value]
Ct0: = 0 [not referenced in this message]
Ct1: = code indicating value setting
Tad: = 0 [not referenced in this message]
By setting the transmission parameters in this way, the message generation circuit 41 generates the message 11 and sends it to the network 1. Then, a code indicating completion of transmission is written in the transmission status register ST43.
[0062]
The network 1 delivers the message to the node indicated by Nad of the message 11, here, the node # 0 or the node # 1.
[0063]
Next, operations of node # 0 and node # 1 that have received the message will be described.
[0064]
In the node 2, the message 11 received from the network 1 is temporarily stored in the input buffer 51, and each field is cut out. Since this message is CTL (R) = 1, it is determined that this message is an update request to the flow control register. Further, since Ct1 is “value setting”, the event control circuit 500 controls the selector 57 to select D1, and the flow control register group 52 sets D1 to D1 for the register indicated by CTL (R #). Write the stored 0.
[0065]
As a result, the free capacity of the circular buffer 58 is set to 0 in the flow control register [R #]. As a result, when flow control is performed again using this flow control register, it is guaranteed that the data supply program waits until a read start request is received.
[0066]
By performing the above operations, the data consumption program (node # 2) interrupts the data consumption program 32, which is the original process, only when all the divided data is ready, good. As a result, it is possible to prevent the data consumption program from being disturbed, for example, the display processing on the display device being interrupted, and the image from being disturbed.
[0067]
Regarding the management of the free capacity of the circular buffer, the data consumption program is not disturbed each time a message arrives, and the free capacity may be transmitted to the data supply program 31 only when the buffer is actually released. . In the description of the present embodiment, the case where one entry of the circular buffer is consumed has been described. However, for reasons of the structure of the data consumption program 32, a plurality of entries may be consumed at once. In this case, the increment of the free capacity of the circular buffer 38 transmitted from the data consumption node to the data supply node is larger than 1.
[0068]
In the data supply node, the data supply program 31 can know the free capacity of the transmission destination circular buffer 38 by examining the value of the flow control register disposed locally.
[0069]
Thus, since each program can operate based on local information, parallel processing can be performed and the performance of the parallel computer can be improved.
[0070]
(2) Modification
Next, a modification of the first embodiment described above will be shown. In the first embodiment, the number of data divisions is used for confirming the arrival of the divided data. In Example 1 above, it was 2 because it was divided into 2 parts. In the modification, the above-described embodiment is modified and realized so that the data that has arrived and the data that has not arrived can be distinguished.
[0071]
In the modified example, the meaning that data has arrived from the data supply node is given to each bit of the value stored in the flag 37.
[0072]
For example, bit 0 of the flag is assigned to node # 0, and bit 1 is assigned to node # 1.
[0073]
Hereinafter, only differences from the first embodiment will be described based on this bit allocation.
[0074]
(Reading request by node # 2)
In the first embodiment, instead of notifying the division number 2, in the first modification, 2 ^ 0 + 2 ^ 1 = 3, that is, the expected value of the flag when the data arrives correctly from both the node # 0 and the node # 1 is notified. Here, “^” represents a power. Further, the node # 0 is instructed to add 2 ^ 0 = 1 to the flag when writing data, and the node # 1 is instructed to add 2 ^ 1 = 2.
[0075]
(Data transfer from the data supply node)
Unlike the first embodiment, the value of the transmission parameter storage register is set as follows when the data supply node transfers data to the node # 2.
[0076]
Nad: = identifier of node # 2
CTL (R): = 0 [indicating that it is not addressed to the flow control register but is addressed to memory]
Dad: = start address of data storage area [i] for node # 0 (or node # 1)
The first is i = 0.
[0077]
Dln: = data length [same as the capacity of the data storage area [i] above]
Fad: = start address of flag storage area [i]
The first is i = 0.
[0078]
Int: = 1 [indicates that an interrupt will be generated]
D0: = 3 [Expected value of flag when both data arrives = 2 ^ 0 + 2 ^ 1]
D1: = 2 ^ 0 = 1 (in the case of node # 0) or 2 ^ 1 = 2 (in the case of node # 1) [representing the increment of the flag]
Ct0: = 0 [indicating that coincidence determination is selected]
Ct1: = code indicating addition
Tad: = start address of transfer data 36
(When data transfer to the area corresponding to the flag is first)
In this case, the flag stored in the flag area [i] has an initial value of 0. The event control circuit 500 selects the flag register 58 by the selector 61 because CTL (R) is 0, and inputs the flag register 58 to one of the arithmetic circuits 56. Then, D 1, that is, 1 or 2 here is input to the other input of the arithmetic circuit 56. The event control circuit 500 controls the arithmetic circuit 56 and the selector 57 to output the addition result of the two inputs of the arithmetic circuit 56 to the output of the selector 57 because Ct1 is a code representing addition. Here, it is 1 or 2. Then, it is written back to the flag register 58. Next, since the event control circuit 500 is Ct0 = 0, that is, a code indicating a coincidence determination, D0 is input to one input of the coincidence determination circuit 53, and 3 is selected by the selector 61 in this case. The contents of the flag register 58, 1 or 2 are input here. The match determination circuit 53 outputs 0 because the two input lines do not match. For this reason, the output selected by the selector 55 becomes 0, and the output of the AND circuit 59 becomes 0. Therefore, no interrupt is generated for the processor 24. That is, if only one side of data arrives, no unnecessary interrupt is generated in the processor 24. Thereby, the effect which does not inhibit execution of a data consumption program is acquired.
[0079]
Then, the memory access circuit 60 writes the updated flag value 1 or 2 stored in the flag register 58 back to the flag storage area [i] indicated by Fad via the system bus 26.
[0080]
As a result, the data consumption program 32 reads out the flag storage area [i], and can determine that neither is received if this value is 0. If it is 1, it can be determined that data is received only from node # 0. If it is 2, it can be determined that data is received only from the node # 1. If it is 3, it can be determined that both are received.
[0081]
(When the data transfer to the area corresponding to the flag is the second)
Similarly, the flag is updated, but the value of the flag read from the flag storage area [i] of the local memory 23 is 1 or 2 this time. Therefore, when the other data is received, 2 or 1 is added by the arithmetic circuit 56, so that the flag value is 3 in both cases, and this value is stored in the flag register 58. Since the two inputs of the coincidence determination circuit 53 are both 3 this time, the output of the coincidence determination circuit 53 is 1. Since the two inputs of the AND circuit 59 have Int of 1, 1 is output. Thus, the event control circuit 500 can interrupt the processor 24, and the processor can know that it has received usable data without waste.
[0082]
【The invention's effect】
When a node accesses a series of data to a distributed node, an interrupt is generated when the entire series of data is received from the distributed node. Therefore, compared to when individual data of a series of data is received. The number of interruptions can be reduced, and the number of times the original processing is interrupted at the node can be reduced, and the processing efficiency of the node can be improved.
[0083]
In addition, since it has means for delaying the response of the access result according to the number of free space for storing the access result in the node at the time of node access, it is necessary to transmit / receive the flow control signal compared to the case of transmitting / receiving the flow control signal between the nodes Therefore, high-speed flow control can be performed without placing a new load on signal transmission / reception between nodes.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a parallel computer according to the present invention.
FIG. 2 is a detailed configuration diagram of the circular buffer 38 of FIG.
[Explanation of symbols]
1 network
2 nodes
21 transmission control circuit,
22 reception control circuit,
23 local memory,
24 processor,
25 disk units,
38 circular buffer,
42 Transmission parameter storage register,
500 Event control circuit.

Claims (2)

In a parallel computer comprising a plurality of nodes each having at least one processor and a network interconnecting the nodes for exchanging messages between the plurality of nodes,
At least one resource that can be used by the plurality of nodes, and means for storing the resource divided into a plurality of nodes;
Whether a node that makes an access request for the resource makes a series of access requests to a plurality of nodes that divide and store the resource, and whether an access result is returned for the series of access requests A flag storage area for storing flag information indicating
In order to record that the node that has received the access request returns the access result to the flag storage area of the node that performs the access request when the access result is returned to the access request. and means for designating the address of the flag storage area, and means for specifying a recording method for the flag storage area, the recording method specified as the address of the flag storage area specified in the data of the access result is at least incidental Means for forming and sending a send message ;
When receiving the transmission message , the node that made the access request records the address in the flag storage area attached to the access result data by a method specified by the recording method attached to the access result data. Means for determining whether or not the flag information formed by recording indicates that there is a response from all nodes, and interrupts the processor when it is determined that there is a response from all nodes. A parallel computer having a circuit for generating In a parallel computer comprising a plurality of nodes each having at least one processor and a network interconnecting the nodes for exchanging messages between the plurality of nodes,
The parallel computer has at least one resource available to the plurality of nodes;
The node has a first node having means for directly accessing the resource and a second node that cannot be directly accessed,
The second node has a circular buffer for sequentially storing a plurality of access result data when accessing the resource;
Storing said first node includes a register for storing the number of free buffers of said circular buffer within the second node, when reply data of said access result to the second node, to said register A circuit for reducing the number of free buffers that have been
When the second node uses the access result data stored in the circular buffer and releases the used access result data from the circular buffer, an empty buffer among the circular buffers of the subject node A circuit for transmitting to the first node a message indicating that the number of
The first node receives the message and increases the number of free buffers stored in the register, and whether the circular buffer of the second node has a free buffer in the register. A circuit that makes a determination based on the number of stored empty buffers, and delays the response of data of the access result to the previous resource executed in response to a request from the second node when the result of the empty determination is that there is no empty buffer . A parallel computer further comprising means.

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