JP3789309B2 - Serial bus tester - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial bus tester, and more particularly, to a serial bus tester capable of quickly executing processing for testing a large number of packets transmitted through a serial bus.
[0002]
[Prior art]
In recent years, a serial bus called IEEE 1394 (hereinafter referred to as “high-speed serial bus”) that enables a high-speed communication between arbitrary node devices by connecting a PC, a printer, a digital camera, an external hard disk, etc. in a daisy chain or tree structure. ") Was put to practical use. This high-speed serial bus is characterized in that a very large number of node devices can be connected using a small cable, and a large amount of data such as moving image data can be transferred smoothly.
[0003]
FIG. 18 shows a connection example of a high-speed serial bus. In FIG. 18, the high-speed serial bus 1 is a serial bus cable 1 ₁ ~ 1 _n-1 A plurality of node devices 2 ₁ ~ 2 _n Are serially connected to each node device 2 _i Is the upper controller 3 _i Physical layer circuit 4 that performs serial communication protocol control at the hardware level in accordance with _i And link layer circuit 5 _i have. Physical layer circuit 4 _i Is serial bus cable 1 _i-1 1 _i Connected to the serial bus cable 1 _i-1 (Or 1 _i When the transmission signal from the other node device transmitted over is received, the same transmission signal is sent to the serial bus cable 1. _i (Or 1 _i-1 ) And converted into received data, and the link layer circuit 5 _i Output to. The link layer circuit 5 _i When transmission data is input from, it is converted to a transmission signal and serial bus cable 1 _i And 1 _i-1 Output to.
[0004]
Link layer circuit 5 _i Is the upper controller 3 _i In accordance with the instruction, a transmission packet addressed to another node device is generated, and transmission data constituting the transmission packet is transmitted to the physical layer circuit 4. _i Output to. Specifically, in the case of an isochronous packet that is guaranteed to be transferred in a 125 microsecond cycle, the header information including the data length, channel number, and synchronization code and the actual data are transferred to the controller 3. _i Is added to the error detection header CRC (cyclic redundancy check) data, data CRC data, etc., and an isochronous packet of a predetermined format consisting of an integer multiple of 4 bytes is generated (see FIG. 19). , Send in 2 bits from the beginning (for 100Mbit / s transfer rate), 4 bits (for 200Mbit / s transfer rate), or 1 byte (for 400Mbit / s transfer rate) Data to physical layer circuit 4 _i Output to. In the case of an asynchronous packet transferred asynchronously, there is a difference such that the node ID (transmission destination ID) of the transmission destination node device and the node ID (transmission source ID) of the transmission source node device are added to the header instead of the channel number. (See FIG. 20).
[0005]
The link layer circuit 5 _i Is the physical layer circuit 4 _i When the received data is input from, the received packet to be fetched by the own node is taken out, the presence or absence of an error is determined using error detection data such as header CRC data and data CRC data, and the controller 3 if there is no error. _i Output to. For example, the presence or absence of a header CRC error is determined based on whether or not the header CRC value calculated from each byte data constituting the header matches the header CRC data added to the header. The determination is made based on whether or not the data CRC value calculated from each byte data constituting the data block matches the data CRC data added to the data block. Link layer circuit 5 _i And physical layer circuit 4 _i Sends and receives control signal data via three control lines CTL0, CTL1, LReq, and eight data lines D while handshaking ₀ ~ D ₇ D ₀ And D ₁ 2 (100Mbit / s transfer rate) or D ₀ ~ D _Three 4 (200Mbit / s) or D ₀ ~ D ₇ Send / receive data is received / received using 8 (400Mbit / s or more). Physical layer circuit 4 _i Performs bus arbitration during transmission or link layer circuit 5 _i It also has a function of outputting a clock SCLK synchronized with control signal data and transmission / reception data transmitted / received to / from.
[0006]
A serial bus tester for performing an operation test of various node devices connected to a high-speed serial bus has been developed. This serious bus tester is denoted by reference numeral 2 in FIG. _n As shown in FIG. 2, the bus is connected as one node device in the same manner as other node devices, and a bus test controller 3 composed of, for example, a microcomputer. _n , Link layer circuit 5 _n Physical layer circuit 4 _n , A memory 10, a display device 11, an operation panel 12, and the like. For example, node device 2 that performs isochronous transfer with channel number 1 ₁ In the case where it is desired to perform the test, the node device 2 is stored in the memory 10 in advance. ₁ Test data used for testing, node equipment 2 ₁ Channel number for isochronous transfer, node device 2 ₁ Node ID, Serious Bus Tester 2 _n The node ID and the like are stored.
[0007]
Node device 2 on the operation panel 12 ₁ Instructs the controller 3 to transfer data. _n Refers to the memory 10, the transfer speed (here, 100 Mbit / s), the node device 2 ₁ Destination ID which is the node ID of the serial bus tester 2 _n The link layer circuit 5 uses the transmission source ID, which is the node ID, header information including the data length of the asynchronous packet, and actual data including the data transfer command. _n Output to. Link layer circuit 5 _n Generates an asynchronous packet (see FIG. 20) of a predetermined format while adding header CRC data, data CRC data, and the like, and the physical layer circuit 4 through the control line LReq. _n The request for securing the right to use the high-speed serial bus 1 and the transfer speed are notified to the physical layer circuit 4. _n Wins the arbitration of access to the high-speed serial bus and gives transfer permission through the control lines CTL0 and CTL1, then the link layer circuit 5 _n (CTL0, CTL1) = (01) for a certain number of clocks as viewed from the clock SCLK, data line D ₀ ~ D ₇ Are all set to 0, and then the data line D is synchronized with the clock SCLK. ₀ And D ₁ The transmission data divided into two bits from the beginning of the asynchronous packet using the physical layer circuit 4 _n (In this case, the link layer circuit 5 _n (CTL0, CTL1) = (10) indicates that transmission data is being output).
[0008]
Physical layer circuit 4 to which transmission data is input _n Converts to an electrical transmission signal according to the standard and outputs it to a high-speed serial bus.
Link layer circuit 5 _n When the transmission data output for one packet is finished and there is no other packet to be transmitted, the link layer circuit 5 _n (CTL0, CTL1) is changed from (10) to (00) to indicate the completion of transmission. _n Shifts to other processing.
[0009]
Serial bus tester 2 _n Node device 2 that has received the transmission signal of the asynchronous packet transmitted from ₁ When transmitting a transmission signal of isochronous packets at a constant cycle at a transfer rate of 100 Mbit / s, all other node devices 2 ₂ ~ 2 _n Physical layer circuit 4 ₂ ~ 4 _n Is received, converted into received data, and the link layer circuit 5 ₂ ~ 5 _n (At this time, the physical layer circuit 4 ₂ ~ 4 _n Indicates that receiving data is being output by outputting (CTL0, CTL1) = (10) through the control lines CTL0, CTL1).
[0010]
Link layer circuit 5 ₂ ~ 5 _n When the control signal data indicating that received data is being output appears on the control lines CTL0 and CTL1, the received data is input in synchronization with the clock SCLK, the packet type is analyzed, and the header is an isochronous packet. It is checked whether the channel number included in is instructed to be received from the host controller. If not specified, the received packet is ignored. If specified, the header CRC data and the data CRC data are used to check for errors in the header and data block. Output to the controller. Serial bus tester 2 _n Then, the channel number included in the header is the controller 3 _n Is received in advance, and when there is no error in the header and the actual data, the link layer circuit 5 _n Is node equipment 2 ₁ Received packets from the controller 3 _n To the controller 3 _n Is stored in the memory 10. Node equipment 2 ₁ The same processing is repeated each time an isochronous packet is repeatedly received from.
If display is instructed on the operation panel 12, the controller 3 _n Displays the received packet stored in the memory 10 on the display device 11 so that the operator can check it.
[0011]
Here, when testing a node device connected to the high-speed serial bus 1, it is necessary to check whether the node device to be tested is correctly transmitting and receiving packets. All transmitted packets must be monitored.
Some link layer circuits have a snoop function that captures all received packets from the received data string input from the physical layer circuit and outputs them to the controller. If an attempt is made to send a desired packet to a device, a very high processing speed is required, and the burden on the configuration is large. In addition, since the packet taken in by the snoop function of the link layer circuit does not include a transmission packet, it is not possible to monitor all packets transmitted on the serial bus in time series order.
[0012]
In view of this point, the inventor of the present invention previously invented a serial bus tester that can monitor all packets transmitted on the high-speed serial bus 1 in chronological order with a simple configuration (Japanese Patent Application No. Hei 10- 124099). This serial bus tester is represented by reference numeral 2 in FIG. _n As shown in FIG. _n And link layer circuit 5 _n In the meantime, a packet capturing circuit 32 for extracting data transmitted and received between them and writing it in the capture memory 30 is provided. The packet capturing circuit 32 starts the physical layer circuit 4 after starting the serial bus test. _n And link layer circuit 5 _n Controller 3 in advance _n Thus, a series of data having a fixed time relationship is extracted from the designated data of the desired reference packet set in the reference packet setting circuit 27 and stored in the capture memory 30. After that, the controller 3 for testing the high-speed serial bus 1 _n Analyzes various types of analysis, such as packet type, transfer speed, packet length, channel number, transmission destination ID, transmission source ID, header CRC error, data CRC error, etc. for the capture memory 30 The result is stored in the memory 10 and the analysis result and the contents of the packet are displayed on the display device 11.
[0013]
[Problems to be solved by the invention]
By the way, in recent years, a large amount of moving image data (MPEG1, MPEG2) photographed with a digital video camera is transferred to a personal computer or a digital recording device using an IEEE1394 serial bus based on a standard called MPEG-TS (MPEG transport stream). In many cases, an optical disk device or a hard disk device is accessed via an IEEE 1394 serial bus based on a standard called SBP-2 (serial bus protocol 2). In MPEG-TS, the consistency with the standard cannot be evaluated unless data in units much larger than the unit of packet is collected, and in SBP2, the consistency with the standard is not collected unless packets transmitted on the serial bus are collected for a long time. Cannot be evaluated.
[0014]
Therefore, it is necessary to use a large capacity of several tens of Mbytes or more for the capture memory 30 in FIG. In this case, after capturing the data in the capture memory 30, the controller 3 for serial bus test _n However, it takes a long time to analyze the packet in the capture memory 30, and it takes a few minutes to a dozen minutes until the analysis result of the desired packet can be displayed.
An object of the present invention is to provide a serial bus tester capable of quickly executing analysis of data captured in a capture memory in view of the above-described problems of the prior art.
[0015]
[Means for Solving the Problems]
The serial bus tester according to claim 1 of the present invention receives a packet transmission signal from another node device connected to the serial bus and transmitted over the serial bus, converts it into reception data, or transmits transmission data. A physical layer circuit that converts the signal into a transmission signal and outputs it to the serial bus, and generates a transmission packet that is connected to the physical layer circuit and is addressed to the other node device according to the instruction of the serial bus test controller. The transmission data that constitutes the data is output to the physical layer circuit together with the control signal data for handshaking, or the received data is input from the physical layer circuit together with the control signal data for handshaking, and a predetermined received packet is taken out to perform the serial bus test Between the link layer circuit that outputs to the controller and the physical layer circuit and link layer circuit Connected to a capture memory that temporarily stores received data and a signal line that connects the physical layer circuit and the link layer circuit, extracts data transmitted and received between the physical layer circuit and the link layer circuit, and writes it to the capture memory A serial bus test controller that performs a desired test process on a packet written in the capture memory. An index memory that temporarily stores index information and a data extraction / write circuit determine the packet while inputting the data extracted by the data extraction / write circuit and the write position to the capture memory. An index containing the storage location at And an index information analysis circuit for storing the index information for each packet in the index memory, and the serial bus test controller performs a desired test process on the packet written in the capture memory. When performing, first, the desired packet is searched for the index information for each packet stored in the index memory to obtain the index information, and the storage location of the desired packet in the capture memory is determined, and the desired memory is retrieved from the capture memory. It is characterized in that the data of the packet is read out.
According to the first aspect, in parallel with the data extraction / write circuit extracting the data transmitted / received between the physical layer circuit and the link layer circuit and writing it to the capture memory, the index information analysis circuit The index information including the storage position on the capture memory is analyzed, and the index information is stored in the index memory for each packet. Therefore, since the index information has already been analyzed after the capture of data into the capture memory is completed, the controller for the serial bus test quickly searches and reads the data of the desired packet in the capture memory with reference to the index memory. As a result, the desired processing for the test can be quickly performed on the desired packet. In particular, when it is desired to perform analysis processing on a desired packet in the capture memory, it is sufficient to analyze only items that are not analyzed by the index information analysis circuit, and the entire analysis processing can be performed quickly.
The serial bus tester according to claim 8 of the present invention receives a packet transmission signal from another node device connected to the serial bus and transmitted over the serial bus, converts it into reception data, or transmits transmission data. A physical layer circuit that converts the signal into a transmission signal and outputs it to the serial bus, and generates a transmission packet that is connected to the physical layer circuit and directed to another node device according to the instructions of the external controller for serial bus testing Outputs the transmission data string that constitutes the packet to the physical layer circuit together with the control signal data for handshake, or inputs the received data string from the physical layer circuit together with the control signal data for handshake to extract a predetermined received packet Link layer circuit to output to external controller for serial bus test and cap for temporarily storing data And a data extraction / write circuit connected to a signal line connecting the physical layer circuit and the link layer circuit, extracting data transmitted and received between the physical layer circuit and the link layer circuit, and writing to the capture memory. The serial bus test external controller temporarily stores the index information of the packets temporarily stored in the capture memory in the serial bus tester that allows the desired test processing to be performed on the packets written in the capture memory. The packet is determined while inputting the data extracted from the data extraction / write circuit and the write position to the capture memory from the index memory and the data extraction / write circuit, and the packet type and the storage position on the capture memory are determined. Analyze the index information including Includes and index information analyzing circuit to be stored in by preparative index information in the index memory, and the index information in the packet stored in the index memory external controller for serial bus test is characterized, it has freely read.
According to the eighth aspect of the invention, in parallel with the data extraction / write circuit extracting the data transmitted / received between the physical layer circuit and the link layer circuit and writing it to the capture memory, the index information analysis circuit determines the packet type and The index information including the storage position on the capture memory is analyzed, and the index information is stored in the index memory for each packet. Therefore, since the index information has already been analyzed after the data is captured into the capture memory, the external controller for serial bus test refers to the index memory to quickly search and read out the data of the desired packet in the capture memory. As a result, the desired processing for the test can be quickly performed on the desired packet. In particular, when it is desired to perform analysis processing on a desired packet in the capture memory, it is sufficient to analyze only items that are not analyzed by the index information analysis circuit, and the entire analysis processing can be performed quickly.
9. The serial bus tester according to claim 1, wherein the data extraction / write circuit transmits and receives data between the physical layer circuit and the link layer circuit after a desired reference timing, before the reference timing or before and after the reference timing. May be extracted and written to the capture memory. Thereby, it is possible to easily perform a test for a desired time range such as immediately after the desired operation of the node device to be tested is started, immediately before the desired operation is started, or before and after the desired operation is started.
9. The serial bus tester according to claim 1, wherein the data extraction / write circuit includes a reference packet designation data setting circuit for setting data for designating a packet for reference timing, a physical layer circuit, and a link layer circuit. A comparison circuit that compares the data transmitted and received with the reference packet designation data, and the physical layer before or after the reference timing, or before and after the reference timing, when the extracted data and the reference packet designation data match Data transmitted and received between the circuit and the link layer circuit may be extracted and written to the capture memory. Thereby, the reference timing for testing a desired time range can be determined accurately.
9. The serial bus tester according to claim 1, wherein the serial bus test controller or the serial bus test external controller analyzes the result of analyzing an arbitrary packet stored in the capture memory. It may be added to the index memory as packet index information. As a result, when a packet that has already been analyzed by the serial bus test controller or the serial bus test external controller is searched again later, the analysis result can be quickly obtained.
9. The serial bus tester according to claim 1, wherein the index information analyzed by the index information analysis circuit includes a part of the header information of the packet in addition to the packet type and the storage position on the capture memory. All or the packet transfer rate or the presence or absence of a packet error may be included.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a block diagram of a serial bus test system including a serial bus tester according to the present invention. The same components as those in FIG. 21 are denoted by the same reference numerals.
Node equipment 2 ₁ 2 ₂ , ..., and serial bus tester (functions as one of node devices) 20 _n Are connected by a high-speed serial bus 1.
Serial bus tester 20 _n Among them, 70 is a capture memory having a storage capacity of, for example, several tens of megabytes, and can store data for one unit at each of (M + 1) addresses from address 0 to M. Here, (M + 1) is a multiple of 2 and one unit of data is 11 bits long here. The capture memory 70 is the physical layer circuit 4 _n And link layer circuit 5 _n Data of a large number of packets exchanged between the two is stored in time series in association with the control signal data CTL0, CTL1, LReq (see FIG. 5).
[0017]
Reference numeral 60 denotes a data extraction / write circuit, which is a link layer circuit 5 _n And physical layer circuit 4 _n Link layer circuit 5 connected to various signal lines connecting _n And physical layer circuit 4 _n All the data exchanged between them is extracted and written into the capture memory 70. The data extracted by the data extraction / write circuit 60 is the data line D here. ₀ ~ D ₇ 8 bits and 3-bit control signal data of the control lines CTLO, CTL1, and LReq. The data extraction / write circuit 60 manages the write address CRA of the capture memory 70 by a built-in write address counter (not shown), and outputs write address data CRA along with the data when performing one write. Then, after writing to the address indicated by the write address data CRA, the write address CRA is incremented (the initial value of the write address is 0 and returns to 0 after reaching M). The data extraction / write circuit 60 also has a function of outputting the extracted data and the write address CRA to the outside.
[0018]
The data extraction / write circuit 60 is specifically configured as shown in FIG. In FIG. 2, reference numeral 61 denotes a register circuit, which is formed by connecting three 11-bit parallel registers (hereinafter simply referred to as registers) 62, 63, and 64 in series. The input side of the register 62 is the data line D from the lower side. ₀ ~ D ₇ Are connected to three control lines CTL0, CTL1, and LReq. The register 62 receives D every time the clock SCLK is input. ₀ ~ D ₇ And CTL0, CTL1, and LReq are simultaneously captured and output. The register 22 outputs the D output from the register 62 every time the clock SCLK is input. ₀ ~ D ₇ And CTL0, CTL1, and LReq are simultaneously captured and output. The register 64 outputs D output from the register 22 every time the clock SCLK is input. ₀ ~ D ₇ And CTL0, CTL1, and LReq are simultaneously captured and output. Therefore, the data line D ₀ ~ D ₇ Each bit data of the control lines CTL0, CTL1, and LReq is sequentially transferred from the registers 62 to 64.
[0019]
Reference numeral 65 denotes a transfer rate identification circuit, which monitors the output of the register 64. When a packet is received, D of the outputs of the register 64 ₀ ~ D ₇ CTL0 and CTL1 identify the transfer rate, and at the time of packet transmission, the transfer rate is identified from LReq among the outputs of the register 64. That is, the physical layer circuit 4 _n When receiving a transmission signal from the high-speed serial bus 1 and outputting received data in synchronization with the clock SCLK, first, (CTL0, CTL1) is changed from (00) to (10) and viewed with the clock SCLK. (D ₀ ~ D ₇ ) = (11111111) = (FF) ₁₆ Is output, the transfer rate code is output, and then the received data is output from the head of the received packet. For 100 Mbit / s, the transfer rate code is (D ₀ ~ D ₇ ) = (00xxxxxxxx), 200 Mbit / s, the transfer rate code is (D ₀ ~ D ₇ ) = (0100xxxx), 400Mbit / s, the transfer rate code is (D ₀ ~ D ₇ ) = (01000000) (x is 0, link layer circuit 5) _n Ignored).
[0020]
For 100Mbit / s, the received data is D ₀ And D ₁ Is output 2 bits at a time, and when 200Mbit / s, the received data is D ₀ ~ D _Three Is output 4 bits at a time, and if it is 400Mbit / s, the received data is D ₀ ~ D ₇ Are output 8 bits at a time. The transfer rate identification circuit 65 monitors CTL0 and CTL1 output from the register 64. When (CTL0, CTL1) changes from (00) to (10), (D ₀ ~ D ₇ ) Is (FF) ₁₆ The first (D ₀ ~ D ₇ The transfer rate is identified from the value of (), and the transfer rate identification data is immediately output to a byte position detection circuit and a pattern detection circuit described later.
[0021]
The link layer circuit 5 _n When the network tries to transmit a packet, the link layer circuit 5 _n The physical layer circuit 4 sends the transfer rate data together with the transmission request through the control line Req in advance. _n Output to. The transfer rate identification circuit 65 monitors Req output from the register 64. When transfer rate data is input together with a transmission request, the transfer rate is identified, and then (CTL0, CTL1) is changed from (00) to (00) ( The transfer speed identification data is output at the time of changing to (01).
[0022]
Reference numeral 66 denotes a byte position detection circuit. Based on CTL0 and CTL1 output from the register 64 and the transfer rate identification data input from the transfer rate identification circuit 24, the byte number of the transmitted packet or the received packet is the D in the register 64. ₀ ~ D ₇ Detect if output from. Specifically, when transfer rate identification data is input in a state where (CTL0, CTL1) is changed from (00) to (10), the D of register 23 is input when the next clock SCLK is input. ₀ ~ D ₇ To receive the first received data of the received packet.
Therefore, if the transfer rate is 100 Mbit / s, after (CTL0, CTL1) is changed from (00) to (10), the count value K initialized to −1 is input to the transfer rate identification data. Each time the clock SCLK is input, the count is incremented by +1, and a value obtained by adding +1 to the quotient q obtained by dividing the count value K by 4 is output as byte position detection data.
[0023]
If the transfer rate is 200 Mbit / s, the count value K initialized to −1 when (CTL0, CTL1) changes from (00) to (10) is input to the transfer rate identification data, and then the clock SCLK Is incremented by +1, and a value obtained by adding 1 to the quotient q obtained by dividing the count value K by 2 is output as byte position detection data. If the transfer rate is 400 Mbit / s, the count value K initialized to −1 when (CTL0, CTL1) changes from (00) to (10) is input to the transfer rate identification data, and then the clock SCLK Is incremented by one each time a value is added, and the value obtained by adding +1 to the count value K is output as byte position detection data.
[0024]
Conversely, when transfer rate identification data is input when (CTL0, CTL1) changes from (00) to (01), when (CTL0, CTL1) changes from (01) to (10), 23 D ₀ ~ D ₇ To output the first transmission data of the transmission packet.
Therefore, when transfer rate identification data is input when (CTL0, CTL1) changes from (00) to (01), the count value K when (CTL0, CTL1) changes from (01) to (10). If the transfer rate is 100 Mbit / s after initializing the bit to zero, the count is incremented by +1 every time the clock SCLK is input, and the byte position detected by adding the count value K divided by 4 to the quotient q Output as data. If the transfer rate is 200 Mbit / s, the count value K is initialized to zero when (CTL0, CTL1) changes from (01) to (10), and then increments by one each time the clock SCLK is input. In addition, a value obtained by adding 1 to the quotient q obtained by dividing the count value K by 2 is output as byte position detection data. If the transfer rate is 400Mbit / s, the count value K is initialized to zero when (CTL0, CTL1) changes from (01) to (10), and then increments by one each time the clock SCLK is input. At the same time, the count value K is output as byte position detection data.
The byte position detection circuit 66 outputs the data output strobe signal ST at a timing when T / 2 has elapsed after changing the output of the byte position detection data, where T is the period of the clock SCLK. The byte position detection circuit 66 sets the byte position detection data to zero when (CTL0, CTL1) is (00).
[0025]
Reference numeral 67 denotes a pattern detection circuit which outputs an 8-bit pattern at the byte position in the transmission packet or reception packet detected by the byte position detection circuit 66. When the pattern detection circuit 26 receives the transfer rate identification data indicating 100 Mbit / s, the output D of the register 64 will be referred to. ₀ And D ₁ D ₀ And d ₁ , Output 63 of register 63 ₀ And D ₁ D ₂ And d _Three , Output D of register 62 ₀ And D ₁ D _Four And d _Five , Link layer circuit 5 _n Output D ₀ And D ₁ D ₆ And d ₇ As (d ₀ d ₁ d ₂ d _Three d _Four d _Five d ₆ d ₇ ) Are arranged in parallel and output in parallel to output 8-bit byte data (here, at 100 Mbit / s, the MSB, 2SB, 3SB, 4SB, 5SB, 6SB, 7SB, LSB is 2 bits at a time (D ₀ D ₁ ) = (MSB2SB), (D ₀ D ₁ ) = (3SB4SB), (D ₀ D ₁ ) = (5SB6SB), (D ₀ D ₁ ) = (7SBLSB) and the physical layer circuit 4 _n And link layer circuit 5 _n To be transferred between).
[0026]
When the pattern detection circuit 67 receives the transfer rate identification data indicating 200 Mbit / s, the output D of the register 64 will be referred to. ₀ ~ D _Three D ₀ ~ D _Three , Output 63 of register 63 ₀ ~ D _Three D _Four ~ D ₇ As (d ₀ d ₁ d ₂ d _Three d _Four d _Five d ₆ d ₇ ) Are arranged in parallel and output in parallel, thereby outputting 8-bit pattern data (here, at 200 Mbit / s, the MSB, 2SB, 3SB, 4SB, 5SB, 6SB, 7SB, LSB is 4 bits each (D ₀ D ₁ D ₂ D _Three ) = (MSB2SB3SB4SB), (D ₀ D ₁ D ₂ D _Three ) = (5SB6SB7SBLSB) and the physical layer circuit 4 _n And link layer circuit 5 _n To be transferred between).
[0027]
When the transfer rate identification data indicating 400 Mbit / s is input, the output D of the register 64 is thereafter applied. ₀ ~ D ₇ D ₀ ~ D ₇ As (d ₀ d ₁ d ₂ d _Three d _Four d _Five d ₆ d ₇ ) To output 8-bit pattern data (in this case, at 400 Mbit / s, the MSB, 2SB, 3SB, 4SB, 5SB, 6SB, 7SB, etc. of each byte data constituting the packet) LSB is (D ₀ D ₁ D ₂ D _Three D _Four D _Five D ₆ D ₇ ) = (MSB2SB3SB4SB5SB6SB7SBLSB) and the physical layer circuit 4 _n And link layer circuit 5 _n To be transferred between).
[0028]
Reference numeral 80 denotes a reference packet setting circuit, and the controller 30 _n Thus, data that designates a reference packet for capturing a desired series of packets among the transmission through the high-speed serial bus 1 is set. Here, as an example, one or a plurality of combinations of byte positions in a packet and 1-byte data at the byte positions are set. When a plurality of settings are made, the order is byte positions (see FIG. 3). Reference numeral 68 denotes a collation circuit which takes in the byte position detection data output from the byte position detection circuit 66 and the byte data output from the pattern detection circuit 67 when the data output strobe signal (ST) is input from the byte position detection circuit 66. The acquired byte position detection data and byte data are collated with the combination of the byte position set by the reference packet setting circuit 80 and the combination of 1 byte data at the byte position, and the setting by the reference packet setting circuit 80 is performed. When all match in order, the reference packet detection signal is output to the data extraction / write control circuit and an index information analysis circuit described later.
[0029]
A data extraction / write control circuit 69 has a write address counter (not shown) that is incremented in synchronization with the clock SCLK, and is output from the register 64 of the register circuit 60 in synchronization with the clock SCLK. Data line D ₀ ~ D ₇ And 11-bit data (DATA) of the control signal lines CTL0, CTL1, and LReq are written into the write address (CRA) designated by the write address counter in the capture memory 70.
[0030]
The data extraction / write control circuit 69 is connected to the serial bus tester 20. _n Is activated, data DATA is written to the capture memory 70 in order from address 0 (after writing up to address M, it returns to address 0 and continues to be written), depending on the capture mode set by the controller described later. In the case of the reference packet start mode (or trigger signal start mode), (M + 1) pieces of data are written from the time when the reference packet detection signal is input from the verification circuit 68 (or when the trigger signal is input from the controller). At the time, writing is finished, and a capture end signal is output to the controller and an index information analysis circuit described later. In the case of the reference packet stop mode (or trigger signal stop mode), the writing is completed and the capture end signal is output when the reference packet detection signal is input from the collating circuit 68 (or when the trigger signal is input from the controller). . In the case of the reference packet step over mode (or trigger signal step over mode), (M + 1) / 2 pieces of data DATA from the time when the reference packet detection signal is input from the verification circuit 68 (or the time when the trigger signal is input from the controller). At the time of writing, writing is finished and a capture end signal is output.
[0031]
The register circuit 61, the transfer speed identification circuit 65, the byte position detection circuit 66, the pattern detection circuit 67, the collation circuit 68, and the data extraction / write control circuit 69 constitute a data extraction / write circuit 60.
[0032]
Reference numeral 90 denotes an index memory, which can store analysis information for each packet and management information of the index memory for a large number of packets. The index memory 90 includes a serial number, a packet type, a packet length, a transfer rate, a channel number (in the case of an isochronous packet), a transmission destination ID (in the case of an asynchronous packet), and a transmission source ID (in the case of an asynchronous packet). ), The primary item of the packet start capture memory address and the packet end capture memory address (the primary item corresponds to the index information in this embodiment), the presence / absence of the header CRC error and data CRC error of the packet, and a predetermined standard Storage area PF for storing time stamp secondary items indicating time difference from timing, analysis progress, and preliminary information (annotation information input by the user) ₀ ~ PF _N (N is a sufficiently large integer of 1000 or more) (see FIG. 4).
[0033]
A management information storage area RF is provided at the end of the index memory 90, and a storage area PF in which index information for packets at the reference timing is stored. _Z Start address AD _Z , A storage area PF in which index information for the oldest packet in the capture memory 70 is stored _S Start address AD _S , A storage area PF in which index information for the newest packet in the capture memory 70 is stored _E Start address AD _E Is memorized.
[0034]
91 is an index information analysis circuit which inputs 11-bit data DATA and a write address CRA output from the data extraction / write control circuit 69 of the data extraction / write circuit 60 and discriminates and analyzes the packet. Packet type, packet length, transfer speed, channel number (for isochronous packets), destination ID (for asynchronous packets), source ID (for asynchronous packets), packet head capture memory address, packet end capture The storage area PF of the index memory 90 using the memory address analysis result (the primary item) as index information together with the packet serial number. ₀ ~ PF _N Is stored in units of packets.
[0035]
The index information analysis circuit 91 is connected to the serial bus tester 20. _n Is in an operating state, packet discrimination, index information analysis, and top storage area PF of the index memory 90 are performed based on the data DATA and the write address CRA input from the data extraction / write control circuit 69. ₀ From the last storage area PF _N After writing up to the top storage area PF ₀ If the reference packet start mode (or trigger signal start mode) is selected according to the capture mode set by the controller, the reference packet detection signal (or the trigger signal from the controller) is sent from the verification circuit 68. Analysis of the data DATA and the write address CRA input from the data extraction / write control circuit 69 during a fixed time (the time required to store 90% of (M + 1) pieces of data in the capture memory 70) from the input time. The result is stored in the index memory 90, and in the reference packet stop mode (or trigger signal stop mode) and the reference packet step over mode (or trigger signal step over mode), the reference packet detection signal (or the controller) G Analysis of the data DATA and the write address CRA input from the data extraction / write control circuit 69 during a fixed time (time required to store (M + 1) pieces of data in the capture memory 70) until the input of the (riga signal). The result is stored in the index memory 90.
[0036]
If the index information analysis circuit 91 is in the reference packet start mode (or trigger signal start mode), the data extraction / write control circuit 69 is input when the reference packet detection signal (or the trigger signal from the controller) is input from the verification circuit 68. Storage area PF in which index information analyzed for a packet including data DATA being input from is stored _i Start address A _(i) AD _S And AD _Z In addition, a storage area PF in which index information of a packet that has been analyzed immediately before inputting a capture end signal from the data extraction / write control circuit 69 is stored _j Start address A _(j) AD _E Is stored in the management information storage area RF.
[0037]
In the case of the reference packet stop mode (or trigger signal stop mode), the storage area PF in which the index information of the packet that has been analyzed immediately before the capture end signal is input from the data extraction / write control circuit 69 is stored. _i Start address A _(i) AD _E And AD _z In the capture memory 70, the index memory is the first of the packets stored after the address next to the write address CRA input from the data extraction / write control circuit 69 when the capture end signal is input. 90 is a storage area PF in which index information is stored for a packet in which index information is written in 90 and the analysis progress data is the primary item analysis _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0038]
In the case of the reference packet step over mode (or trigger signal step over mode), the data being input from the data extraction / write control circuit 69 when the reference packet detection signal (or the trigger signal from the controller) is input from the verification circuit 68. Storage area PF storing index information analyzed for packets including DATA _i Start address A _(i) AD _Z In addition, a storage area PF in which index information of a packet that has been analyzed immediately before inputting a capture end signal from the data extraction / write control circuit 69 is stored _j Start address A _(j) AD _E Further, in the capture memory 70, when an end-of-capture signal is input, the first index is stored in the packets stored after the address next to the write address CRA being input from the data extraction / write control circuit 69. Storage area PF in which index information is stored for a packet in which index information is written in the memory 90 and analysis progress status data has been analyzed for the primary item _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0039]
Reference numeral 10 denotes a memory, which stores programs and data necessary for the evaluation test of the node device. The memory 10 has a serial bus tester 20 during the evaluation test. _n The packet transmitted to the destination is also stored. 11 is a display device for displaying the result of the evaluation test, and 12 is an operation panel for performing a capture mode selection operation for performing the evaluation test, a data setting operation for designating a reference packet, a display instruction operation for displaying the evaluation test result, and the like. Do.
[0040]
30 _n Is a controller for serial bus testing, and is composed of, for example, a microcomputer. This controller 30 _n Performs an evaluation test of a desired node device using an evaluation test program and data stored in the memory 10 in accordance with an instruction on the operation panel 12 by an operator. Specifically, in order to make the desired node device perform a desired operation, the link layer circuit 5 _n To send a packet addressed to the desired node device, or from the desired node device to the serial bus tester 20 _n The packet transmitted to the destination is received and output, and stored in the memory 10. Then, the contents of the received packet stored in the memory 10 are displayed according to the operator's instruction. In addition, in order to capture all packets transmitted on the high-speed serial bus 1 during a certain period of time, capture mode setting for the data extraction / write circuit 60 and the index information analysis circuit 91, output of a trigger signal, Set the specified data of the reference packet. Further, among the predetermined number of packets stored in the capture memory 70, items other than the analysis target of the index information analysis circuit 91 are analyzed, and the analysis result of the index information analysis circuit 91 is combined with the analysis result in the display device 11. Display.
Serial bus tester 20 _n The other components are the same as those shown in FIG.
[0041]
Next, the operation of the above-described embodiment will be briefly described with reference to FIGS. 5 to 7 are explanatory diagrams of the storage contents of the capture memory 70, FIGS. 8 to 9 are explanatory diagrams of the storage contents of the index memory 90, and FIG. 10 is the storage contents and indexes of the capture memory 70 in the reference packet step over mode. FIG. 11 is an explanatory diagram showing the relationship between the storage content of the memory 90, FIG. 11 is an explanatory diagram showing the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 in the reference packet start mode, and FIG. FIG. 13 is a diagram illustrating the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 in FIG. 13, and FIG. 13 shows the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 in the trigger signal step over mode. FIG. 14 shows a capture memo in the trigger signal start mode. FIG. 15 is an explanatory diagram showing the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 in the trigger signal stop mode. .
Here, the node equipment 2 ₁ Each node device 2 connected to the high-speed serial bus 1 ₁ 2 ₂ , ... and serial bus tester 20 _n Are in the operating state in advance, and the node device 2 is stored in the memory 10 in advance. ₁ Data required for testing, node equipment 2 ₁ Channel number for isochronous transfer, node device 2 ₁ Node ID, Serious Bus Tester 20 _n It is assumed that the node ID and the like are stored. The link layer circuit 5 _n Shall not have a snoop function.
[0042]
(1) Reception of packets from the high-speed serial bus
Node equipment 2 ₁ 2 ₂ Are outputting a packet transmission signal on the high-speed serial bus 1, the serial bus tester 20 _n Physical layer circuit 4 _n Is received and the received data is synchronized with the clock SCLK in the link layer circuit 5. _n Output to. At this time, first, (CTL0, CTL1) is changed from (00) to (10), and the data line D is transferred by a predetermined number of clocks. ₀ ~ D ₇ (FF) ₁₆ And then the data line D for one clock ₀ ~ D ₇ After the transfer speed data is output, the received packet is synchronized with the clock SCLK and the data line D is ₀ ~ D _h (H = 7 when the transfer rate is 400 Mbit / s, h = 3 when the transfer rate is 200 Mbit / s, h = 1 when the transfer rate is 100 Mbit / s) _n Indicates (CTL0, CTL1) = (01) indicating that received data is being output). Link layer circuit 5 _n Is the physical layer circuit 4 _n When the packet is received and the control lines CTL0 and CTL1 are changed from (00) to (10), the received data is input in synchronization with the clock SCLK. And controller 30 in advance _n The received packet instructed as a target to be captured by the own node is taken out, error detection data such as header CRC data, data CRC data, etc. is used to determine the presence or absence of an error. _n Output to. Controller 30 _n Is the link layer circuit 5 _n When the received packet is input from, it is stored in the memory 10. Then, in accordance with an instruction on the operation panel 12, necessary processing such as display on the display device 11 is performed.
Physical layer circuit 4 _n When the reception data output for one packet is completed, (CTL0, CTL1) is changed from (01) to (00) to indicate reception completion.
[0043]
(2) Sending packets to the high-speed serial bus
Conversely, the controller 30 _n Link layer circuit 5 based on _n Is physical layer circuit 4 _n When outputting the transmission data of the transmission packet addressed to the other node device, the serial stream data is output to LReq in advance, and the physical layer circuit 4 _n For this, a request for securing the right to use the high-speed serial bus 1 and a transfer speed are specified. Physical layer circuit 4 _n Wins the arbitration (CTL0, CTL1) for one clock (11) and gives transfer permission, the link layer circuit 5 _n (CTL0, CTL1) by (01), (D ₀ ~ D ₇ ) To (00) ₁₆ The transmission packet is prepared, and (CTL0, CTL1) is set to (10) and the transmission packet is synchronized with the clock SCLK to start the data line D ₀ ~ D _h (When the transfer speed is 400 Mbit / s, h = 7, when 200 Mbit / s, h = 3, when 100 Mbit / s, h = 1) (in this case, the link layer circuit 5 _n (CTL0, CTL1) = (10) indicates that transmission data is being output).
Physical layer circuit 4 to which transmission data is input _n Is converted into an electrical transmission signal according to the standard and output to the high-speed serial bus 1.
Link layer circuit 5 _n When the transmission data output for one packet is finished and there is no other packet to be transmitted, the link layer circuit 5 _n (CTL0, CTL1) is changed from (10) to (00) to indicate the completion of transmission. _n Shifts to other processing.
[0044]
By the way, the link layer circuit 5 having no snoop function _n Is the physical layer circuit 4 _n It is not possible to capture all received packets based on the received data input from. In this embodiment, since the capture memory 70 and the data extraction / write circuit 60 are provided, a series of desired large number of packets transmitted on the high-speed serial bus 1 can be captured, and the index Since the memory 90 and the index information analysis circuit 91 are provided, the captured packet is also analyzed in parallel with the packet capture operation.
[0045]
That is, the serial bus tester 20 _n During the operation of the physical layer circuit 4 in the data extraction / write circuit 60 _n And link layer circuit 5 _n Data line D exchanged between ₀ ~ D ₇ 11 bits of data, which is a combination of the control signal data of the control lines CTLO, CTL1, and LReq, are sequentially transferred from the registers 62 to 64 in synchronization with the clock SCLK. Is output. The data extraction / write control circuit 69 writes the 11-bit data output from the register 64 in the capture memory 70 in order from the start address 0 in synchronization with the clock SCLK. The operation of returning to the top address and sequentially writing again is repeated. It should be noted that the register 64 D is received when a packet is received. ₀ ~ D ₇ When the transfer rate data is output from the LReq, or when the transfer rate data is output from the LReq of the register 64 at the time of packet transmission, the transfer rate identification circuit 65 identifies the transfer rate and sends it to the byte position detection circuit 66 and the pattern detection circuit 67. Output.
[0046]
On the other hand, serial bus tester 20 _n During the operation, the index information analysis circuit 91 receives the 11-bit data DATA and the write address CRA output from the data extraction / write control circuit 69 and performs analysis in real time to determine the packet and the type of the packet. Packet length, transfer rate, channel number (for isochronous packets), destination ID (for asynchronous packets), source ID (for asynchronous packets), packet start capture memory address, packet end capture memory address The analysis result (primary item) and the analysis progress data indicating that the primary item has been analyzed and the secondary item has not been analyzed, together with the packet serial number (initial value is 1) Storage area PF ₀ Are written in order from packet to packet, and the last storage area PF _N After reaching the top storage area PF ₀ The operation of returning to step S3 and writing again in order is repeated.
[0047]
For example, the storage area PF of the index memory 90 _i-1 Until the writing of the primary item of the packet is in progress (storage area PF _i-1 The serial number written in is assumed to be a), and then the physical layer circuit 4 _n When receiving a packet transmission signal from the high-speed serial bus 1 and outputting received data in synchronization with the clock SCLK, first, (CTL0, CTL1) is changed from (00) to (10). The index information analysis circuit 91 monitors (CTL0, CTL1) and LReq of the data DATA and determines that the preceding part of the received packet has started when (CTL0, CTL1) changes from (00) to (10). Then, the write address CRA at that time is used as the packet head capture memory address and the storage area PF _i Address A _(i) Write to +7. And storage area PF _i-1 The serial number (= a + 1) obtained by adding 1 to the serial number of the packet of the address A _(i) Write to. D of data DATA by a predetermined number of clocks from the time (CTL0, CTL1) changes from (00) to (10) ₀ ~ D ₇ Is (FF) ₁₆ Immediately after becoming D for one clock ₀ ~ D ₇ Indicates the transfer rate data. _(i) Write to +3.
[0048]
Subsequently, when the transfer rate is 400 Mbit / s, D of data DATA ₀ ~ D ₇ From (CTL0, CTL1) to just before the change from (10) to (00), the main part of the received packet is output byte by byte from the beginning (RA in FIG. 5). ₀ ~ RA _m ) When the transfer rate is 200Mbit / s, D of data DATA ₀ ~ D _Three Until (CTL0, CTL1) immediately before (CTL), (CTL1) changes from (10) to (00), the main part of the received packet is output bit by bit from the top (RB in FIG. 5). ₀ ~ RB _m ) When the transfer rate is 100Mbit / s, D of data DATA ₀ And D ₁ Until (CTL0, CTL1) immediately before (CTL), (CTL1) changes from (10) to (00), the main part of the received packet is output bit by bit from the top (RC in FIG. 6). ₀ ~ RC _m ). Therefore, the index information analysis circuit 91 analyzes the main part of the received packet, identifies the packet type from the transaction code (tcode; transaction code) in the header, etc. _(i) Write to +1, and if the type is an isochronous packet, the channel number in the header is set to address A _(i) If it is an asynchronous packet, write the destination ID and source ID in the header to address A _(i) +5, A _(i) Write to +6. Then, the length (number of bytes) of the main part of the received packet is counted, and the address A _(i) Write to +2. Finally, when the data DATA (CTL0, CTL1) changes from (10) to (00), it is determined that the received packet has ended, and the address immediately before the write address CRA at that time is set as the packet end capture memory. Address A as address _(i) Write to +8. Address the analysis progress data indicating that the primary item has been analyzed and the secondary item has not been analyzed. _(i) Write to +11.
[0049]
For example, if the received packet RA in FIG. 5 is an analysis target, among the primary items, transfer rate = 400 Mbit / s, packet length = 200 bytes, packet head capture memory address = 111, packet end capture memory address = 316 (Refer to FIG. 8 (1).) If the received packet RB is an object to be analyzed, among the primary items, transfer rate = 200 Mbit / s, packet length = 460 bytes, packet head capture memory address = 350, packet end Capture memory address = 1275 (see FIG. 8B). If the received packet RC shown in FIG. 6 is to be analyzed, among the primary items, transfer rate = 100 Mbit / s, packet length = 600 bytes, packet start capture memory address = 11301, and packet end capture memory address = 3706. (See FIG. 8 (3). Note that x in FIGS. 5 to 7 is 0, but is ignored as data constituting the packet).
[0050]
In addition, the storage area PF of the index memory 90 _j-1 Until the writing of the primary item of the packet is in progress (storage area PF _j-1 The serial number written to the link layer circuit 5 is c). _n Is physical layer circuit 4 _n When outputting transmission data of a transmission packet addressed to another node device, the index information analysis circuit 91 monitors the data DATA (CTL0, CTL1) and LReq, and the link layer circuit 5 _n When the serial stream data is output to LReq, the transmission speed in the data is temporarily stored, and then the transmission packet is changed when (CTL0, CTL1) of the data DATA changes from (01) to (10). The memory area PF is determined to have started and the write address CRA at that time is used as the packet head capture memory address _j Address A _(j) Write to +7. And storage area PF _j-1 The serial number (= c + 1) obtained by adding 1 to the serial number of the packet of the address A _(j) Write to.
[0051]
And when the transfer rate is 400Mbit / s, D of data DATA ₀ ~ D ₇ Until (CTL0, CTL1) immediately before (CTL), (CTL1) change from (10) to (00), the main part of the transmission packet is output byte by byte (TA in FIG. 6). ₀ ~ TA _m ) When the transfer rate is 200Mbit / s, D of data DATA ₀ ~ D _Three Until (CTL0, CTL1) immediately before the change from (10) to (00), the main part of the transmission packet is output bit by bit from the beginning (TB in FIG. 7). ₀ ~ TB _m ) When the transfer rate is 100Mbit / s, D of data DATA ₀ And D ₁ Until (CTL0, CTL1) immediately before (CTL), (CTL1) changes from (10) to (00), the main part of the transmission packet is output 2 bits at a time from the beginning (TC in FIG. 7). ₀ ~ TC _m ). Therefore, the index information analysis circuit 91 analyzes the main part of the transmission packet, identifies the packet type from the transaction code (tcode) in the header, etc. _(j) Write to +1, and if the type is an isochronous packet, the channel number in the header is set to address A _(j) If it is an asynchronous packet, write the destination ID and source ID in the header to address A _(j) +5, A _(j) Write to +6. Then, the length (number of bytes) of the main part of the transmission packet is counted, and the address A _(j) Write to +2. Finally, when the data (CTL0, CTL1) changes from (10) to (00), it is determined that the transmission packet has ended, and the address immediately before the write address CRA at that time is set as the packet end capture memory. Address A as address _(j) Write to +8. Address the analysis progress data indicating that the primary item has been analyzed and the secondary item has not been analyzed. _(j) Write to +11.
[0052]
For example, if the transmission packet TA in FIG. 6 is an analysis target, among the primary items, transfer rate = 400 Mbit / s, packet length = 200 bytes, packet head capture memory address = 3862, packet end capture memory address = 4061 If the transmission packet TB in FIG. 7 is an analysis target, the transfer rate is 200 Mbit / s, the packet length is 460 bytes, and the packet head capture memory address is 4122. Packet end capture memory address = 5042 (see FIG. 9B). If the transmission packet TC in FIG. 7 is an analysis target, among the primary items, the transfer rate = 100 Mbit / s, the packet length = 600 bytes, the packet start capture memory address = 5125, and the packet end capture memory address = 7524. (See FIG. 9 (3)).
[0053]
(3) Capture in reference packet step-over mode (see FIG. 10)
As described above, the data extraction / write circuit 60 is connected to the physical layer circuit 4. _n And link layer circuit 5 _n In the state where various data exchanged between the nodes is written in the capture memory 70 and the index information analysis circuit 91 is analyzing the index information of the packets written in the capture memory 70 in parallel. ₁ Suppose that it is desired to monitor all transmission packets on the high-speed serial bus 1 over a certain time range before and after a certain desired operation command is given as an asynchronous packet with a transfer rate of 100 Mbit / s. The memory 10 includes a node device 2 connected to the high-speed serial bus 1. ₁ Node ID and Serious Bus Tester 20 _n Is stored.
[0054]
First, when the operator performs an operation of setting the reference packet step-over mode on the operation panel 12, the controller 30 _n Sets the data extraction / write control circuit 69 and the index information analysis circuit 91 to the reference packet step over mode. Subsequently, the node device 2 is used as data for designating the reference packet on the operation panel 12. ₁ The transmission destination ID and the transmission source ID of the asynchronous packet for the desired operation command given to, and the actual data (here, 4 bytes long) representing the desired operation command are input. For example, node device 2 ₁ Is input as the destination ID, and the serial bus tester 20 _n Node ID is input as a transmission source ID, and 4-byte data representing a desired operation command is input as actual data. Then, the controller 30 _n 3 inputs the upper byte and lower byte of the transmission destination ID input by the operator as the first and second bytes of the reference packet to the reference packet setting circuit 80 as shown in FIG. Are input as the 5th and 6th bytes of the reference packet, and the 1st to 4th bytes of the actual data representing the desired operation instruction are set as the 21st to 24th bytes of the reference packet, respectively.
[0055]
Thereafter, the operator uses the operation panel 12 to connect the node device 2. ₁ Instructing the controller 30 to transmit an asynchronous packet for a desired operation command to the controller 30 _n Refers to the memory 10, the transfer speed (here, 100 Mbit / s), the node device 2 ₁ The link layer circuit 5 includes the transmission destination ID indicating the serial bus tester, the transmission source ID indicating the serial bus tester, the data length of the asynchronous packet, the header information including the synchronization code, and the actual data of the desired operation instruction. _n Node device 2 ₁ To send an asynchronous packet for a desired operation command.
[0056]
Controller 30 _n Link layer circuit 5 that has received a transmission instruction from _n Generates an asynchronous packet (see FIG. 20) of a predetermined format while adding a header CRC, data CRC, and the like, and uses the physical layer circuit 4 through the control line LReq. _n The request for securing the right to use the high-speed serial bus 1 and the transfer speed are notified to the physical layer circuit 4. _n Wins the arbitration of access to the high-speed serial bus 1 and gives the transfer permission by setting the control lines CTL0 and CTL1 to (11) for only one clock, the link layer circuit 5 _n (CTL0, CTL1) by (01), (D ₀ ~ D ₇ ) To (00) ₁₆ The transmission packet is prepared while (CTL0, CTL1) is set to (10) and synchronized with the clock SCLK to the data line D ₀ And D ₁ The transmission data divided into two bits from the beginning of the asynchronous packet using the physical layer circuit 4 _n (In this case, the link layer circuit 5 _n (CTL0, CTL1) = (10) indicates that transmission data is being output).
[0057]
Physical layer circuit 4 to which transmission data is input _n Is converted into an electrical transmission signal according to the standard and output to the high-speed serial bus 1.
Link layer circuit 5 _n When the transmission data output for one packet is finished and there is no other packet to be transmitted, the link layer circuit 5 _n (CTL0, CTL1) is changed from (10) to (00) to indicate the completion of transmission. _n Shifts to other processing.
[0058]
Node equipment 2 ₁ In order to give a desired operation command to the link layer circuit 5 _n And physical layer circuit 4 _n The various data exchanged between and are written in the capture memory 70 in synchronization with the clock SCLK in the form of 11-bit data DATA by the data extraction / write circuit 60, and at the same time, the index information analysis circuit 91 discriminates the packet. The primary items are analyzed and written to the index memory 90. In the data extraction / write circuit 60, when a request for securing the right to use the high-speed serial bus 1 and the transfer speed are output from the LReq of the register 64, the transfer speed identification circuit 65 identifies the transfer speed, When (CTL0, CTL1) output from the register 64 changes from (00) to (01), transfer speed identification data indicating the current 100 Mbit / s is output to the byte position detection circuit 66 and the pattern detection circuit 67.
[0059]
When the byte position detection circuit 66 inputs transfer rate identification data indicating 100 Mbit / s when the output (CTL0, CTL1) of the register 64 changes from (00) to (01), (CTL0, CTL1) becomes (01 ) To (10), the count value K is initialized to zero, and is incremented by +1 each time the clock SCLK is input. Then, a value obtained by adding 1 to the quotient q obtained by dividing the count value K by 4 is output as byte position detection data (the byte position detection circuit 65 initializes the byte position detection data to zero in advance). When the pattern detection circuit 67 inputs the transfer rate identification data indicating 100 Mbit / s, the output D of the register 64 is thereafter applied. ₀ And D ₁ D ₀ And d ₁ , Output 63 of register 63 ₀ And D ₁ D ₂ And d _Three , Output D of register 62 ₀ And D ₁ D _Four And d _Five , Link layer circuit 5 _n Output D ₀ And D ₁ D ₆ And d ₇ As (d ₀ d ₁ d ₂ d _Three d _Four d _Five d ₆ d ₇ ) In order and output in parallel to output 8-bit pattern data.
[0060]
Each time the collation circuit 68 inputs the data strobe signal ST from the byte position detection circuit 66, the detected byte position output from the byte position detection circuit 66 at that time coincides with each byte position set in the reference packet setting circuit 80. When they match, it is checked whether the 8-bit pattern detected by the pattern detection circuit 67 at that time matches the byte data set in the reference packet setting circuit 80 in association with the byte position.
[0061]
The detection pattern when the detection byte position is 1 matches the upper byte data of the transmission destination ID set corresponding to the first byte position 1 set in the reference packet setting circuit 80, and then the detection byte position Is equal to the lower byte data of the transmission destination ID set corresponding to the second byte position 2 set in the reference packet setting circuit 80, and then the detected byte position is 5 The detection pattern when the detection byte position matches the upper byte data of the transmission source ID set corresponding to the third byte position 5 set in the reference packet setting circuit 80 and the detection byte position is 6 Matches the lower byte data of the transmission source ID set in correspondence with the fourth byte position 6 set in the reference packet setting circuit 80, and the detected byte positions are 21-24. Detection patterns of the first byte to the fourth byte of 4-byte data representing desired operation instructions set corresponding to the fifth to eighth byte positions 5 to 8 set in the reference packet setting circuit 80, and When they match, the collation circuit 68 outputs a reference packet detection signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.
[0062]
The data extraction / write control circuit 69 set in advance in the reference packet step over mode continues to write the data DATA to the capture memory 70 after the input of the reference packet detection signal. When the data DATA has been written by half the total number of addresses of 70, the writing to the capture memory 70 is stopped and a capture end signal CE is output. On the other hand, the index information analysis circuit 91 set in the reference packet step-over mode in advance has received the reference packet detection signal and the primary item until the capture end signal CE is input from the data extraction / write control circuit 69 after the input of the reference packet detection signal. And writing to the index memory 90, the packet including the data DATA being input at the time when the reference packet detection signal is input (reference character PC in FIG. 10). ₀ The storage area for writing the primary item analyzed for _i When it becomes, storage area PF _i Start address A _(i) AD _Z Is written in the management information storage area RF.
[0063]
Serial bus tester 20 _n Node device 2 that has received the transmission signal of the asynchronous packet transmitted from ₁ When the transmission signal of isochronous packet is transmitted at a constant cycle at a transfer rate of 100 Mbit / s, the serial bus tester 20 _n Physical layer circuit 4 _n Is received, converted into received data, and the link layer circuit 5 _n Output to. Link layer circuit 5 _n Since the received data is input in synchronization with the clock SCLK and is an isochronous packet, the channel number included in the header is the upper controller 30. _n If it is instructed, the header CRC and the data CRC are used to check for errors in the header and data block. _n Output to. Controller 30 _n Is stored in the memory 10.
[0064]
Node device 2 ₁ Physical layer circuit 4 when a packet is received from _n And link layer circuit 5 _n In the same manner as described above, the various data exchanged between and are written in the capture memory 70 by the data extraction / write circuit 60 in the time series order, and the packet is discriminated by the index information analysis circuit 91 and the primary item is analyzed. Is written in the index memory 90. Node equipment 2 ₁ The isochronous packet from the serial bus tester 20 _n The same process is repeated each time.
[0065]
After that, when data DATA has been written by an amount corresponding to half of the total number of addresses in the capture memory 70 after the reference packet detection signal has been input first, the data extraction / write control circuit 69 writes to the capture memory 70. And the capture end signal CE is sent to the controller 30. _n And output to the index information analysis circuit 91. When receiving the capture end signal CE, the index information analysis circuit 91 receives the packet being analyzed at that time (the code PC in FIG. 10). _{# 0} For reference), the analysis operation is finished without writing to the index memory 90 (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed immediately before the capture end signal CE is input (the symbol PC in FIG. 10). _{# 1} ) Storage area PF in which index information is written _j Start address A _(j) AD _E As a write address CRA (reference code ad in FIG. 10) being input from the data extraction / write control circuit 69 when the capture end signal CE is input. _{# 0} ) After the next address (after the first address when CRA is M), the index information is written to the index memory 90 earliest and the analysis progress data is analyzed for the primary item. Packet (reference character PC in FIG. 10) _{# 2} Storage area PF in which index information is written _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0066]
As a result, the capture memory 70 stores the node device 2. ₁ Asynchronous packet PC for giving desired operation command to ₀ The information of a series of all packets transmitted within a predetermined time on the high-speed serial bus 1 is stored, and the index memory 90 stores the index information of each packet stored in the capture memory 70. Therefore, the node equipment 2 will be later ₁ The operating characteristics can be inspected accurately and quickly.
Here, for convenience of explanation, it is assumed that the relationship between the storage contents of the capture memory 70 at the end of capture and the storage contents of the index memory 90 is as shown in FIG.
[0067]
(6) Analysis of secondary items and display of analysis information in reference packet step over mode
Controller 30 that has received capture end signal CE under the reference packet step over mode _n First, a work area is secured in the memory 10. Then, the AD of the management information storage area RF of the index memory 90 _Z The address AD of the index memory 90 is referred to _Z Storage area PF starting from _i Address A _(i) B and address A _(i) Add packet capture memory address stored at +7 to ad ₀ In the work area, and further, AD in the management information storage area RF _S And AD _E The address AD of the index memory 90 is referred to _S Storage area PF starting from _k Address A _(k) Is the serial number stored in bs, address AD _E Storage area PF starting from _j Address A _(j) Is stored in the work area as bE.
[0068]
First, a group (b-50) to (b + 49) of 100 serial numbers centering around b is determined as the 0th group. The group of 100 {(b-150) to (b-51)} immediately before the 0th group is the first group, and the group of 100 {(b-250) to (b- 151)} is divided into the -2nd group, the -rth group {bs to (b-((r-1) * 100 + 51))}, and the 100 immediately after the 0th group {(b + 50) The group of (b + 149)} is the first group, the group of 100 {(b + 150) to (b + 249)} immediately after the first group is the second group, and so on, and the r ′ group {(b + (r′−) 1) Divide from x100) to bE}.
[0069]
Then, all the storage areas (PFs) corresponding to the 0th group in the index memory 90 are displayed. _a ~ PF _c And all the stored contents are transferred to the work area secured in the memory 10. The code and address of each storage area transferred onto the work area of the memory 10 are the same as those on the index memory 90 (PF _a ~ PF _c ) And address. First, the storage area PF corresponding to the first serial number (b-50) of the 0th group in the work area. _a Address A _(a) Check whether the analysis progress data of +11 has already been analyzed for the secondary items. If analyzed, address A _(a) +7 packet head capture memory address (= ad _as And address A _(a) +8 packet end capture memory address (= ad _ae The packet PC of the serial number (b-50) from the capture memory 70. _(b-50) About data (address ad _as ~ Ad _ae Data) and move to the work area, packet configuration data (each data constituting the packet format such as header and data block) or packet configuration data and CLT0, CLT1, LReq control signal data), primary item index Information, presence / absence of various errors in secondary items, time stamp, and annotation information, if present, are initially displayed on the display device 11 in a predetermined format. However, since the analysis of the secondary item is not yet performed here, first the address A _(a) +7 packet start capture memory address and address A _(a) Referring to the +8 packet end capture memory address, packet PC of serial number (b-50) from capture memory 70 _(b-50) The data about is read and moved to the work area.
[0070]
And address A _(a) When the packet type of +1 indicates a packet including a header, CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and compared with the header CRC value added at the end of the header. By doing so, it is determined whether or not there is a header CRC error. In addition, address A _(a) When the packet type of +1 indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, whether there is an error separately for the header CRC error and the data CRC error, the storage area PF of the work area of the memory 10 _a Address A _(a) Write to +9. Subsequently, in the capture memory 70, the storage area PF _a Address A _(a) Packet start capture memory address stored in +7 (= ad _as ) Data DATA and ad stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _a Address A _(a) Write to +10 (ad ₀ When written earlier, the time stamp has a negative sign, and when written later, the time stamp has a positive sign. ₀ The time stamp is 0). Finally, storage area PF _a Address A _(a) The secondary item analyzed is added as the analysis progress data of +11. Packet configuration data (or packet configuration data and CLT0, CLT1, and LReq control signal data), primary item index information, presence / absence of various secondary item errors, time stamp, address address A _(a) If there is annotation information of +12 to 39, the annotation information is combined and displayed on the display device 11 as analysis information in a predetermined format.
[0071]
Next, the controller 30 _n Is a storage area PF corresponding to the second serial number (b-49) of the 0th group in the work area of the memory 10. _{a + 1} Address A _{(a + 1)} Check whether the analysis progress data of +11 has already been analyzed for secondary items. Address A _{(a + 1)} +7 packet head capture memory address and address A _{(a + 1)} With reference to the +8 packet end capture memory address, the data of the packet of serial number (b-49) is read from the capture memory 70 and moved to the work area. And address A _{(a + 1)} When the packet type of +7 indicates a packet including a header, CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and compared with the header CRC value added at the end of the header By doing so, the presence or absence of a header CRC error is determined. In addition, address A _{(a + 1)} When the packet type of +1 indicates a packet including a data block, the CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, the presence or absence of an error is determined for the header CRC error and the data CRC error, and the storage area PF of the work area _{a + 1} Address A _{(a + 1)} Write to +9.
[0072]
Subsequently, in the capture memory 70, the storage area PF _{a + 1} Address A _{(a + 1)} Data DATA stored in the packet head capture memory address stored in +7 and ad ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _{a + 1} Address A _{(a + 1)} Write to +10. Finally, storage area PF _{a + 1} Address A _{(a + 1)} The secondary item analyzed is added as the analysis progress data of +11.
Similarly, for each packet corresponding to the third to 100th serial numbers (b-48) to (b + 50) of the 0th group in the work area of the memory 10, the presence / absence of a header CRC error and a data CRC error is determined. Analyzing the time stamp, the storage area PF in the work area of the memory 10 _{a + 2} ~ PF _c Write to
[0073]
0th group first packet configuration data (or packet configuration data and CLT0, CLT1, and LReq control signal data), primary item index information, secondary item presence / absence of various errors, and time stamp After the initial display on the display device 11 in the format, when the operator wants to display analysis information regarding the second packet of the 0th group, the operator presses the down cursor key once on the operation panel 12. Then, the controller 30 _n Is a storage area PF corresponding to the second packet of the 0th group in the work area of the memory 10 in parallel with the analysis processing of the secondary item of each packet of the 0th group. _{a + 1} Address A _{(a + 1)} +7 packet head capture memory address and address A _{(a + 1)} With reference to the +8 packet end capture memory address, the data of the packet with the serial number (b-49) is read from the capture memory 70 and moved to the work area of the memory 10. And address A _{(a + 1)} +111 analysis progress data is referenced to check whether the secondary item has been analyzed. If it has been analyzed, packet configuration data (or packet configuration data and control signal data for CLT0, CLT1, LReq), primary item Index information, the presence / absence of various errors in secondary items, time stamps, and annotation information, if any, are displayed on the display device 11 in a predetermined format as packet analysis information. If the secondary item is still unanalyzed, the secondary item is removed and displayed, and then added to the display when it has been analyzed.
[0074]
Similarly, when the down cursor key is pressed once in the state where the analysis information of the 0th group f (where 1 ≦ f <100) packet is displayed, the controller 30 _n Displays the analysis information on the packet next to the currently displayed packet in the 0th group. On the other hand, when the up cursor key is pressed once in the state where the analysis information of the f-th packet of the 0th group (where 1 <f ≦ 100) is displayed, the controller 30 _n Displays analysis information on the packet immediately before the packet currently being displayed in the 0th group. Pressing the down cursor key with the analysis information of the last packet of the 0th group displayed is ignored, and pressing the up cursor key with the analysis information of the first packet of the 0th group displayed is also ignored. Is done.
[0075]
The 50th packet of the 0th group is the node device 2 to be tested ₁ A packet (reference character PC in FIG. _(b) Therefore, the node device 2 is checked by checking the analysis information of 100 packets of the 0th group. ₁ Before and after giving a desired operation command to the node device 2 ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet of the 0th group has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0076]
When displaying the analysis information of the 50th packet of the 0th group, the controller 30 _n Also displays a mark indicating the reference packet. Also, the controller 30 _n When the user inputs arbitrary annotation information on the operation panel 12 while the analysis information of the f-th packet in the 0th group is displayed, the annotation information is additionally displayed and the storage area PF of the work area is displayed. _{(a + f-1)} Address A _{(a + f-1)} Write to +12 to 39.
[0077]
When the operator wants to check the analysis information of the packet of the (−1) group immediately before the 0th group, the operator presses the front group key once on the operation panel 12. Controller 30 _n When the analysis of the secondary items of all the packets of the 0th group is not yet completed when the front group key is pressed, the pressing of the front group key is ignored. 0th group storage area PF _a ~ PF _c Are all saved in the corresponding storage area of the index memory 90. Then, in the index memory 90, all the storage areas (PF) corresponding to the (−1) th group _d ~ PF _e And all the stored contents are transferred to the work area secured in the memory 10. The code and address of each storage area transferred to the work area have the same code (PF) as the index memory 90. _d ~ PF _e ) And address. First, the storage area PF corresponding to the first serial number (b-150) of the (−1) -th group in the work area. _d Storage area PF _d It is checked whether or not the analysis progress data stored in the column has been analyzed for the secondary items. If analyzed, the packet start capture memory address and the packet end capture memory address are referred to, the data of the packet with the serial number (b-150) is read from the capture memory 70, moved to the work area, and the packet configuration data (Or packet configuration data and CLT0, CLT1, and LReq control signal data) Primary item index information, secondary item error status and time stamp, and annotation information, if any, in a predetermined format Initial display is performed on the display device 11. However, since the analysis of the secondary item is not yet performed here, first, the data of the packet with the serial number (b-150) is read from the capture memory 70 and moved to the work area.
[0078]
And storage area PF _d When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, whether there is an error separately for the header CRC error and the data CRC error, the storage area PF of the work area of the memory 10 _d Write to. Subsequently, in the capture memory 70, the storage area PF _d Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _d Write to. Finally, storage area PF _d The secondary item analyzed is added to the analysis progress data stored in. Then, packet configuration data (or packet configuration data and CLT0, CLT1, and LReq control signal data), primary item index information, presence / absence of various secondary item errors and time stamps, and annotation information are included in the annotation information. Together, it is initially displayed on the display device 11 as analysis information in a predetermined format.
[0079]
Next, the controller 30 _n Is a storage area PF corresponding to the second serial number (b-149) of the (−1) -th group in the work area. _{d + 1} Storage area PF _{d + 1} It is checked whether or not the analysis progress data stored in the second item has been analyzed, and the serial number (b-149) is retrieved from the capture memory 70 with reference to the packet start capture memory address and the packet end capture memory address. ) Is read and moved to the work area. And storage area PF _{d + 1} When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, whether there is an error separately for the header CRC error and the data CRC error, the storage area PF of the work area of the memory 10 _{d + 1} Write to.
[0080]
Subsequently, the storage area PF of the work area of the memory 10 in the capture memory 70. _{d + 1} Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _{d + 1} Write to. Finally, storage area PF _{d + 1} The secondary item analyzed is added to the analysis progress data stored in.
Similarly, for each packet corresponding to the third to 100th serial numbers (b-148) to (b-51) in the (-1) group in the work area, the header CRC error and the data CRC error are determined. The presence / absence and time stamp are analyzed, and the storage area PF in the work area of the memory 10 _{d + 2} ~ PF _e Write to
[0081]
First packet configuration data (or packet configuration data and control signal data of CLT0, CLT1, LReq) of the (−1) group, primary item index information, presence / absence of various types of errors and time stamps, After the annotation information is displayed on the display device 11 in a predetermined format, when the user wants to display analysis information regarding the second packet in the (−1) -th group, the down cursor key is pressed once on the operation panel 12. Then, the controller 30 _n Is a storage area PF corresponding to the second packet of the (-1) group in the work area in parallel with the analysis processing of the secondary item of each packet of the (-1) group described above. _{d + 1} Referring to the packet head capture memory address and the packet end capture memory address stored in, the data of the packet with the serial number (b-149) is read from the capture memory 70 and moved to the work area. And storage area PF _{d + 1} The analysis progress data stored in is checked to check whether the secondary item has been analyzed, and if analyzed, packet configuration data (or packet configuration data and CLT0, CLT1, LReq control signal data), 1 The index information of the next item, the presence / absence of various errors of the secondary item, the time stamp, and the annotation information, if any, are displayed on the display device 11 in a predetermined format as packet analysis information. If the secondary item is still unanalyzed, the secondary item is removed and displayed, and then added to the display when it has been analyzed.
[0082]
Similarly, when the down cursor key is pressed once in a state where the analysis information of the f-th packet (where 1 ≦ f <100) of the (−1) -th group is displayed, the controller 30 _n Displays analysis information on the next packet of the currently displayed packet in the (-1) th group. On the other hand, when the up cursor key is pressed once in the state where the analysis information of the f-th packet of the (−1) -th group (where 1 <f ≦ 100) is displayed, the controller 30 _n Displays analysis information on the packet immediately before the currently displayed packet in the (−1) -th group. The pressing of the down cursor key in the state where the analysis information of the last packet of the (-1) group is displayed is ignored, and the analysis information of the first packet of the (-1) group is displayed. Cursor key presses are also ignored.
Since the primary item of each packet of the (−1) -th group has also been analyzed during the capture, the controller 30 after the capture _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0083]
Similarly, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the controller 30 is pressed. _n Is a storage area PF corresponding to all packets in the h-th group in the work area on condition that −r <h ≦ r ′. _u ~ PF _v Are saved in the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h-1) th group from the index memory 90 is saved. _w ~ PF _t Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed. On the other hand, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the next group key is pressed, the controller 30 _n Is a storage area PF corresponding to all packets in the h-th group in the work area on condition that −r ≦ h <r ′. _u ~ PF _v Are saved to the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h + 1) th group from the index memory 90 is saved. _p ~ PF _q Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed.
[0084]
(5) Capture in reference packet start mode (see FIG. 11)
In the above description, the case where the capture is performed in the reference packet step over mode has been described. ₁ To capture and analyze a packet transmitted on the high-speed serial bus 1 within a certain period of time after giving a desired operation command to the operator, the operator first performs an operation of setting the reference packet start mode on the operation panel 12. Controller 30 _n Thus, the data extraction / write control circuit 69 and the index information analysis circuit 91 are set to the reference packet start mode. Thereafter, data for designating an asynchronous packet for a desired operation command as a reference packet is input on the operation panel 12, and the controller 30 _n Then, after the reference packet setting circuit 80 is set, the transmission of a desired operation command is further instructed.
[0085]
The data extraction / write control circuit 69 set in the reference packet start mode writes data to the capture memory 70 when the data DATA has been written by 90% of the total number of addresses of the capture memory 70 from the input time of the reference packet detection signal. Stop and output a capture end signal CE. On the other hand, the index information analysis circuit 91 set in the reference packet start mode receives a packet including the data DATA being input at the time when the reference packet detection signal is input (reference character PC in FIG. 11). ₀ The storage area for writing the primary item analyzed for _i When it becomes, storage area PF _i Start address A _(i) AD _Z And AD _S When the capture end signal CE is input to the management information storage area RF, the packet being analyzed at that time (the code PC in FIG. 11) _{# 0} For reference), the analysis operation is finished without writing to the index memory 90 (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed just before the capture end signal CE is input (the code PC in FIG. 11). _{# 1} Storage area PF in which index information is written) _j Start address A _(j) AD _E Is written in the management information storage area RF.
[0086]
As a result, the capture memory 70 stores the node device 2. ₁ Since a desired operation command is given to, information of a series of all packets transmitted within a predetermined time on the high-speed serial bus 1 is stored, and the index memory 90 stores each information stored in the capture memory 70. Since packet index information is stored, node device 2 will be ₁ The operating characteristics can be inspected accurately and quickly.
Here, for convenience of explanation, it is assumed that the relationship between the storage contents of the capture memory 70 and the storage contents of the index memory 90 is as shown in FIG.
[0087]
(6) Analysis of secondary items and display of analysis information in reference packet start mode
Controller 30 that has received capture end signal CE under the reference packet start mode _n First, a work area is secured in the memory 10. Then, the AD of the management information storage area RF of the index memory 90 _S The address AD of the index memory 90 is referred to _S Storage area PF starting from _i Address A _(i) Is the serial number stored in bs, address A _(i) Add packet capture memory address stored at +7 to ad ₀ In the work area, and further, AD in the management information storage area RF _E The address AD of the index memory 90 is referred to _E Storage area PF starting from _j Address A _(j) Is stored in the work area as bE.
[0088]
First, a collection of 100 serial numbers bs to (bs + 99) in order from bs is defined as the 0th group. A group of 100 {(bs + 100) to (bs + 199)} immediately after the 0th group is referred to as a first group, and a group of 100 ((bs + 200) to (bs + 299)} immediately after the first group is referred to as a second group. The condition is divided into the r′th group {(bs + r ′ × 100) to bE}.
[0089]
Then, as in the case of the reference packet step over mode, all the storage areas (PFs) corresponding to the 0th group in the index memory 90 are stored. _i ~ PF _c And all the stored contents are transferred to the work area secured in the memory 10. The code (PF) of each storage area transferred to the work area _i ~ PF _c ) And an address are assigned a code and an address on the index memory 90. First, the storage area PF corresponding to the first serial number bs of the 0th group in the work area of the memory 10. _i Storage area PF _i It is checked whether or not the analysis progress data stored in the second item has been analyzed, and since it is not yet, the serial number b is read from the capture memory 70 with reference to the packet start capture memory address and the address packet end capture memory address. _s Packet (reference character PC in FIG. ₀ Data) is read and moved to the work area.
[0090]
And storage area PF _i When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, the presence or absence of an error is determined for the header CRC error and the data CRC error, and the storage area PF of the work area _i Write to. Subsequently, in the capture memory 70, the storage area PF _i Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _i Write to (ad ₀ When written earlier, the time stamp has a negative sign, and when written later, the time stamp has a positive sign. ₀ The time stamp is 0). Finally, storage area PF _i The analysis of the secondary item is added to the analysis progress data of. Then, packet configuration data (or packet configuration data and CLT0, CLT1, and LReq control signal data), primary item index information, presence / absence of various secondary item errors and time stamps, and annotation information are included in the annotation information. Together, it is initially displayed on the display device 11 as analysis information in a predetermined format.
[0091]
Next, the controller 30 _n Is a storage area PF corresponding to the second serial number (bs + 1) of the 0th group in the work area of the memory 10. _{i + 1} Therefore, it is checked whether the analysis progress status data has already been analyzed for the secondary item, and the storage area PF _{i + 1} Referring to the packet start capture memory address and the packet end capture memory address, the packet data of the serial number (bs + 1) is read from the capture memory 70 and moved to the work area. And storage area PF _{i + 1} When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, the presence or absence of an error is determined for the header CRC error and the data CRC error, and the storage area PF of the work area _{i + 1} Write to.
[0092]
Subsequently, in the capture memory 70, the storage area PF _{i + 1} Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _{i + 1} Write to. Finally, storage area PF _{i + 1} The analysis of the secondary item is added to the analysis progress data of.
Similarly, for each packet corresponding to the third to 100th serial numbers bs + 2) to (bs + 99) of the 0th group in the work area, the presence / absence of a header CRC error and a data CRC error and the time stamp are analyzed. , Storage area PF in the work area _{i + 2} ~ PF _c Write to
[0093]
After the analysis information of the first packet of the 0th group is initially displayed on the display device 11, when the user wants to display the analysis information regarding the second packet of the 0th group, the down cursor key is set to 1 on the operation panel 12. Press once. Then, the controller 30 _n Is a storage area PF corresponding to the second packet of the 0th group in the work area in parallel with the analysis processing of the secondary item of each packet of the 0th group described above. _{i + 1} Referring to the packet start capture memory address and the packet end capture memory address of the packet of the serial number (bs + 1) from the capture memory 70 (reference character PC in FIG. 11). _{(bs + 1)} Data) is read and moved to the work area. And storage area PF _{i + 1} Referring to the analysis progress data, check whether the secondary item has been analyzed, and if analyzed, packet configuration data (or packet configuration data and CLT0, CLT1, LReq control signal data) Index information, presence / absence of various errors in secondary items, time stamp, and annotation information, if any, are combined and displayed on the display device 11 as packet analysis information in a predetermined format. If the secondary item is still unanalyzed, the secondary item is removed and displayed, and then added to the display when it has been analyzed.
[0094]
Similarly, when the down cursor key is pressed once in a state where the analysis information of the f-th packet in the 0th group (where 0 ≦ f <100) is displayed, the controller 30 _n Displays the analysis information on the packet next to the currently displayed packet in the 0th group. On the other hand, when the up cursor key is pressed once in the state where the analysis information of the f-th group of the 0th group (where 1 <f ≦ 100) is displayed, the controller 30 _n Displays analysis information on the packet immediately before the packet currently being displayed in the 0th group. Pressing the down cursor key with the analysis information of the last packet of the 0th group displayed is ignored, and pressing the up cursor key with the analysis information of the first packet of the 0th group displayed is also ignored. Is done.
[0095]
The first packet of the 0th group is the node device 2 to be tested ₁ Therefore, by checking the analysis information of 100 packets of the 0th group, the node device 2 ₁ After giving a desired operation command to the node device 2 ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet of the 0th group has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0096]
When the user wants to check the analysis information of the first group packet after the 0th group, the user presses the next group key once on the operation panel 12. Controller 30 _n When the next group key is pressed, if the analysis of the secondary items of all the packets of the 0th group has not been completed, the pressing of the next group key is ignored. 0th group storage area PF _i ~ PF _c Are all saved in the corresponding storage area of the index memory 90. Then, all the storage areas (PFs) corresponding to the first group in the index memory 90 are stored. _d ~ PF _e Are stored in the work area secured in the memory 10, and analysis of secondary items of each packet and display of analysis information of desired packets of the operator are performed.
Since the primary item of each packet of the first group has also been analyzed during capture, the controller 30 after capture _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0097]
Similarly, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the controller 30 is pressed. _n Is a storage area PF corresponding to all packets in the h-th group in the work area, provided that 0 <h ≦ r ′. _u ~ PF _v Are saved in the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h-1) th group from the index memory 90 is saved. _w ~ PF _t Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed.
On the other hand, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the next group key is pressed, the controller 30 _n Is a storage area PF corresponding to all packets in the h-th group in the work area, provided that 0 ≦ h <r ′. _u ~ PF _v Are saved to the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h + 1) th group from the index memory 90 is saved. _p ~ PF _q Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed.
[0098]
(7) Capture in reference packet stop mode (see Fig. 12)
Unlike this, node device 2 ₁ To capture and analyze a packet transmitted on the high-speed serial bus 1 within a certain period of time immediately before giving a desired operation command to the operator, the operator first performs an operation for setting the reference packet stop mode on the operation panel 12. Controller 30 _n Thus, the data extraction / write control circuit 69 and the index information analysis circuit 91 are set to the reference packet stop mode. Thereafter, data for designating an asynchronous packet for a desired operation command as a reference packet is input on the operation panel 12, and the controller 30 _n Then, after the reference packet setting circuit 80 is set, the transmission of a desired operation command is further instructed.
[0099]
The data extraction / write control circuit 69 set in the reference packet stop mode stops writing to the capture memory 70 when the reference packet detection signal is input, and outputs a capture end signal CE. On the other hand, the index information analysis circuit 91 set in the reference packet stop mode receives the packet being analyzed (reference character PC in FIG. 12) at the time when the capture end signal CE is input. _{# 0} For reference), the analysis operation is finished without writing to the index memory 90 (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed immediately before the capture end signal CE is input (the code PC in FIG. 12). _{# 1} Storage area PF in which index information is written) _j Start address A _(j) AD _E The write address CRA (reference code ad in FIG. 12) being input from the data extraction / write control circuit 69 when the capture end signal CE is input in the capture memory 70. _# ) After the next address (after the first address when CRA is M), the index information is written to the index memory 90 earliest and the analysis progress data is analyzed for the primary item. Packet (reference character PC in FIG. 12) _{# 2} Storage area PF in which index information is written _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0100]
As a result, the capture memory 70 stores the node device 2. ₁ The information of a series of all packets transmitted over the high-speed serial bus 1 within a predetermined time until a desired operation command is given to is stored in the index memory 90, and each packet stored in the capture memory 70 is stored in the index memory 90. Since the index information of the node device 2 is stored later, ₁ The operating characteristics can be inspected accurately and quickly.
Here, for convenience of explanation, it is assumed that the correspondence between the storage contents of the capture memory 70 and the storage contents of the index memory 90 is as shown in FIG.
[0101]
(8) Analysis of secondary items and display of analysis information in reference packet stop mode
The controller 30 that has input the capture end signal CE under the reference packet stop mode. _n First, a work area is secured in the memory 10. Then, the AD of the management information storage area RF of the index memory 90 _S The address AD of the index memory 90 is referred to _S Storage area PF starting from _k Address A _(k) Is the serial number stored in bs, address A _(k) Add packet capture memory address stored at +7 to ad ₀ In the work area, and further, AD in the management information storage area RF _E The address AD of the index memory 90 is referred to _E Storage area PF starting from _j Address A _(j) Is stored in the work area as bE.
[0102]
First, a set of 100 serial numbers (bE-99) to bE immediately before bE is defined as the 0th group. Then, a group of 100 {(bE-199) to (bE-100)} immediately before the 0th group is represented by the 100th group (-1) and the 100 immediately before the (-1) group {(bE-299). ˜ (bE−200)} is divided into the (−2) th group and the (−r) th group {bs− (bE−r × 100)}.
[0103]
Then, in the same manner as in the case of the reference packet start mode, all the storage areas (PFs) corresponding to the 0th group in the index memory 90 are displayed. _a ~ PF _k And all the stored contents are transferred to the work area secured in the memory 10. The code and address of each storage area transferred to the work area of the memory 10 is the code (PF) on the index memory 90. _a ~ PF _k ) And address. First, the storage area PF corresponding to the first serial number bs of the 0th group in the work area _a Therefore, it is checked whether the analysis progress data has been analyzed for the secondary items. If it has been analyzed, the storage area PF _a The packet data of the serial number (bE-99) is read from the capture memory 70 and transferred to the work area with reference to the packet start capture memory address and the packet end capture memory address stored in the packet, and the packet configuration data (or packet configuration data) And control signal data of CLT0, CLT1, and LReq) Index information of the primary item, presence / absence and time stamp of various errors of the secondary item, and if there is annotation information, the annotation information is initialized to the display device 11 in a predetermined format. Display. However, since the analysis of the secondary item is not yet performed here, first, the serial number (b _E -99) packet data is read out and moved to the work area.
[0104]
Then, the storage area PF of the work area of the memory 10 _a When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, whether there is an error separately for the header CRC error and the data CRC error, the storage area PF of the working area of the memory 10 _a Write to. Subsequently, in the capture memory 70, the storage area PF _a Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _a Write to (ad ₀ When written earlier, the time stamp has a negative sign, and when written later, the time stamp has a positive sign. ₀ The time stamp is 0). Finally, storage area PF _a The analysis of the secondary item is added to the analysis progress data of. Then, packet configuration data (or packet configuration data and CLT0, CLT1, and LReq control signal data), primary item index information, presence / absence of various secondary item errors, time stamp, and annotation information are combined together. Thus, the data is initially displayed on the display device 11 as analysis information in a predetermined format.
[0105]
Next, the controller 30 _n Is the storage area PF corresponding to the second serial number (bE-98) of the 0th group in the work area. _{a + 1} Therefore, it is checked whether the analysis progress status data has been analyzed for the secondary items. Since it is not yet, referring to the packet head capture memory address and the packet end capture memory address, the data of the packet with the serial number (bE-98) is read from the capture memory 70 and moved to the work area. And storage area PF _{a + 1} When the packet type stored in the header indicates a packet including a header, the CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the header CRC value added to the end of the header is calculated. To determine whether there is a header CRC error. Further, when the packet type indicates a packet including a data block, CRC is calculated from each byte data in the data block portion of the data read from the capture memory 70, and the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing with the value. Then, whether there is an error separately for the header CRC error and the data CRC error, the storage area PF of the work area of the memory 10 _{a + 1} Write to.
[0106]
Subsequently, the storage area PF of the work area of the memory 10 in the capture memory 70. _{a + 1} Data DATA stored in the packet head capture memory address stored in ₀ The time difference at the time of capture with the data DATA stored in is calculated, and the storage area PF is used as a time stamp. _{a + 1} Address A _{(a + 1)} Write to +10. Finally, storage area PF _{a + 1} The analysis of the secondary item is added to the analysis progress data of.
Similarly, for each packet corresponding to the third to 100th serial numbers (bE-97) to bE of the 0th group in the work area, the presence or absence of the header CRC error and the data CRC error, and the time stamp analysis are performed. Storage area PF in the work area _{a + 2} ~ PF _c Write to
[0107]
After the analysis information of the first packet of the 0th group is initially displayed on the display device 11, when the operator wants to display the analysis information regarding the second packet of the 0th group, the down cursor key is pressed on the operation panel 12. Press once. Then, the controller 30 _n Is a storage area PF corresponding to the second packet of the 0th group in the work area in parallel with the analysis processing of the secondary item of each packet of the 0th group described above. _{a + 1} The packet data of the serial number (bE-98) is read from the capture memory 70 with reference to the packet start capture memory address and the packet end capture memory address, and moved to the work area. Then, referring to the analysis progress data, it is checked whether the secondary item has been analyzed. If it has been analyzed, packet configuration data (or packet configuration data and control signal data of CLT0, CLT1, LReq), primary item Index information, the presence / absence of various errors in secondary items, time stamps, and annotation information, if any, are displayed on the display device 11 in a predetermined format as packet analysis information. If the secondary item is still unanalyzed, the secondary item is removed and displayed, and then added to the display when it has been analyzed.
[0108]
Similarly, when the down cursor key is pressed once in the state where the analysis information of the f-th group (where 1 ≦ i <100) packet of the 0th group is displayed, the controller 30 _n Displays the analysis information on the packet next to the currently displayed packet in the 0th group. On the other hand, when the up cursor key is pressed once in the state where the analysis information of the fth group (where 1 <i ≦ 100) of the 0th group is displayed, the controller 30 _n Displays analysis information on the packet immediately before the packet currently being displayed in the 0th group. Pressing the down cursor key with the analysis information of the last packet of the 0th group displayed is ignored, and pressing the up cursor key with the analysis information of the first packet of the 0th group displayed is also ignored. Is done.
[0109]
The 100th packet of the 0th group is the node device 2 to be tested ₁ Therefore, by checking the analysis information of 100 packets of the 0th group, the node device 2 ₁ The node device 2 immediately before giving a desired operation command to ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet of the 0th group has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0110]
When the operator wants to check the analysis information of the packet of the (−1) group in front of the 0th group, the operator presses the front group key once on the operation panel 12. Controller 30 _n When the analysis of the secondary items of all the packets of the 0th group is not yet completed when the front group key is pressed, the pressing of the front group key is ignored. 0th group storage area PF _a ~ PF _c Are all saved in the corresponding storage area of the index memory 90. Then, in the index memory 90, all the storage areas (PF) corresponding to the (−1) th group _d ~ PF _e Are stored in the work area secured in the memory 10, and analysis of secondary items of each packet and display of analysis information of desired packets of the operator are performed.
Since the primary item of each packet of the (−1) -th group has also been analyzed during the capture, the controller 30 after the capture _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0111]
Similarly, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the controller 30 is pressed. _n Is a storage area PF corresponding to all packets in the h-th group in the work area on condition that −r <h ≦ 0. _u ~ PF _v Are saved in the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h-1) th group from the index memory 90 is saved. _w ~ PF _t Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed.
On the other hand, when the analysis information of the h-th group packet is displayed and the analysis of the secondary item is completed for all the packets of the h-th group, the next group key is pressed, the controller 30 _n Is a storage area PF corresponding to all packets in the h-th group in the work area on condition that −r ≦ h <0. _u ~ PF _v Are saved to the corresponding storage area of the index memory 90, and the storage area PF corresponding to all packets of the (h + 1) th group from the index memory 90 is saved. _p ~ PF _q Are moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the user desired packet is displayed.
[0112]
(9) Capture in trigger signal step over mode (see Fig. 13)
Unlike this, for example, the node device 2 ₁ When the operator wants to capture and analyze a packet transmitted on the high-speed serial bus 1 within a certain time before and after a certain desired timing when the packet starts to be transmitted, the operator first uses the operation panel 12. Trigger signal step over mode setting operation, controller 30 _n Thus, the data extraction / write control circuit 69 and the index information analysis circuit 91 are set to the trigger signal step over mode. Subsequently, the node device 2 is displayed on the operation panel 12. ₁ When an instruction to send a desired operation command is sent to the controller 30, the controller 30 _n Is node equipment 2 ₁ An asynchronous packet for a desired operation command is transmitted to start the desired operation.
Thereafter, when the operator performs a trigger operation with the operation panel 12 at a desired timing, the controller 30 _n Outputs a trigger signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.
[0113]
The data extraction / write control circuit 69 set to the trigger signal step over mode continues writing data DATA to the capture memory 70 even after the trigger signal is input. When the writing of the data DATA has progressed by a half amount, the writing to the capture memory 70 is stopped and the capture end signal CE is output. On the other hand, the index information analysis circuit 91 set in the trigger signal step-over mode discriminates packets and analyzes and indexes the primary items until the capture end signal CE is input from the data extraction / write control circuit 69 even after the trigger signal is input. The packet is written into the memory 90, but includes the data DATA being input at the time when the trigger signal is input (reference character PC in FIG. 13). ₀ The storage area for writing the primary item analyzed for _i When it becomes, storage area PF _i Start address A _(i) AD _Z Is written in the management information storage area RF. When receiving the capture end signal CE, the index information analysis circuit 91 receives the packet being analyzed at that time (the code PC in FIG. 13). _{# 0} ) Is not written to the index memory 90 and the analysis operation is finished (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed immediately before the capture end signal CE is input (the code PC in FIG. 13). _{# 1} ) Storage area PF in which index information is written _j Start address A _(j) AD _E As a write address CRA (reference numeral ad in FIG. 13) being input from the data extraction / write control circuit 69 when the capture end signal CE is input. _# ) After the next address (after the first address when CRA is M), the index information is written to the index memory 90 earliest and the analysis progress data is analyzed for the primary item. Packet (code PC in FIG. 13) _{# 2} Storage area PF in which index information is written _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0114]
As a result, the capture memory 70 stores the node device 2. ₁ Information of a series of all packets transmitted over the high-speed serial bus 1 within a predetermined time centering on the timing at which a trigger is applied at an arbitrary time after starting a desired operation is stored in the index memory. 90 stores the index information of each packet stored in the capture memory 70. ₁ The operating characteristics can be inspected accurately and quickly.
[0115]
(10) Analysis of secondary items and display of analysis information in trigger signal step over mode
The controller 30 that has input the capture end signal CE under the trigger signal step over mode. _n Performs the same processing as that in the reference packet step over mode, so that the node equipment 2 ₁ In a state where a desired operation is started, the node device 2 before and after the worker triggers at a desired timing. ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0116]
(11) Capture in trigger signal start mode (see Fig. 14)
Unlike this, for example, the node device 2 ₁ When the operator wants to capture and analyze a packet transmitted on the high-speed serial bus 1 within a certain time from a certain desired timing while starting the desired operation and transmitting the packet, the operator first uses the operation panel 12 to generate a trigger signal. Start mode setting operation, controller 30 _n Thus, the data extraction / write control circuit 69 and the index information analysis circuit 91 are set to the trigger signal start mode. Subsequently, the node device 2 is displayed on the operation panel 12. ₁ When an instruction to send a desired operation command is sent to the controller 30, the controller 30 _n Is node equipment 2 ₁ An asynchronous packet for a desired operation command is transmitted to start the desired operation.
Thereafter, when the operator performs a trigger operation with the operation panel 12 at a desired timing, the controller 30 _n Outputs a trigger signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.
[0117]
The data extraction / write control circuit 69 set to the trigger signal start mode stops writing to the capture memory 70 when the data DATA has been written by 90% of the total number of addresses of the capture memory 70 from the time when the trigger signal is input. The capture end signal CE is output. On the other hand, the index information analysis circuit 91 set to the trigger signal start mode includes a packet including the data DATA being input including the data DATA being input at the time when the trigger signal is input (reference character PC in FIG. 14). ₀ The storage area for writing the primary item analyzed for _i When it becomes, storage area PF _i Start address A _(i) AD _Z And AD _S When the capture end signal CE is input to the management information storage area RF, the packet being analyzed at that time (the symbol PC in FIG. _{# 0} For reference), the analysis operation is finished without writing to the index memory 90 (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed immediately before the capture end signal CE is input (the symbol PC in FIG. 14). _{# 1} Storage area PF in which index information is written) _j Start address A _(j) AD _E Is written in the management information storage area RF.
[0118]
As a result, the capture memory 70 stores the node device 2. ₁ After a desired operation is started, information of a series of all packets transmitted on the high-speed serial bus 1 within a predetermined time is stored after the operator triggers, and the index memory 90 stores the information. Since the index information of each packet stored in the capture memory 70 is stored, the node device 2 will be described later. ₁ The operating characteristics can be inspected accurately and quickly.
[0119]
(12) Analysis of secondary items and display of analysis information in trigger signal start mode
The controller 30 that has input the capture end signal CE under the trigger signal start mode. _n Performs the same processing as that in the reference packet start mode, so that the node device 2 ₁ In the state where the desired operation is started, the node device 2 immediately before the operator triggers at the desired timing. ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0120]
(13) Capture in trigger signal stop mode (see Fig. 15)
Unlike this, for example, the node device 2 ₁ When the operator wants to capture and analyze a packet transmitted on the high-speed serial bus 1 within a certain time before a certain desired timing during which a desired operation is started and a packet is being transmitted, the operator first triggers on the operation panel 12 The signal stop mode is set and the controller 30 _n Thus, the data extraction / write control circuit 69 and the index information analysis circuit 91 are set to the trigger signal stop mode. Subsequently, the node device 2 is displayed on the operation panel 12. ₁ When an instruction to send a desired operation command is sent to the controller 30, the controller 30 _n Is node equipment 2 ₁ An asynchronous packet for a desired operation command is transmitted to start the desired operation.
Thereafter, when the operator performs a trigger operation with the operation panel 12 at a desired timing, the controller 30 _n Outputs a trigger signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.
[0121]
The data extraction / write control circuit 69 set to the trigger signal stop mode stops writing to the capture memory 70 when the trigger signal is input, and outputs a capture end signal CE. On the other hand, the index information analysis circuit 91 set in the trigger signal stop mode receives the packet being analyzed at the time when the capture end signal CE is input (the code PC in FIG. 15). _{# 0} For reference), the analysis operation is finished without writing to the index memory 90 (packet PC). _{# 0} Some items are already stored in the storage area PF _{j + 1} Storage area PF _{j + 1} Write primary item not analyzed to analysis progress data for. Then, the packet that has been analyzed immediately before the capture end signal CE is input (the code PC in FIG. 15). _{# 1} Storage area PF in which index information is written) _j Start address A _(j) AD _E As a write address CRA (reference numeral ad in FIG. 15) being input from the data extraction / write control circuit 69 when the capture end signal CE is input. _# ) After the next address (after the first address when CRA is M), the index information is written to the index memory 90 earliest and the analysis progress data is analyzed for the primary item. Packet (code PC in FIG. 15) _{# 2} Storage area PF in which index information is written _k Start address A _(k) AD _S Is stored in the management information storage area RF.
[0122]
As a result, the capture memory 70 stores the node device 2. ₁ After a desired operation is started, information on a series of all packets transmitted within a predetermined time on the high-speed serial bus 1 immediately before the operator triggers is stored, and the index memory 90 stores the information. Since the index information of each packet stored in the capture memory 70 is stored, the node device 2 will be described later. ₁ The operating characteristics can be inspected accurately and quickly.
[0123]
(14) Analysis of secondary items and display of analysis information in trigger signal stop mode
The controller 30 that has input the capture end signal CE under the trigger signal stop mode. _n Performs the same processing as that in the reference packet stop mode, so that the node device 2 ₁ In the state where the desired operation is started, the node device 2 immediately before the operator triggers at the desired timing. ₁ It is possible to analyze in detail what kind of operation is performed at what timing. Moreover, since the primary item of each packet has been analyzed during capture, the controller 30 after capture is completed. _n Since it is only necessary to analyze the secondary items, the analysis processing of each packet can be proceeded quickly, and the operator can quickly check complete analysis information of the desired packet.
[0124]
In any capture mode, the link layer circuit 5 _n When the operator instructs display on the operation panel 12 for the received packet that is input from and stored in the memory 10, the controller 30. _n Reads from the memory 10 and causes the display device 11 to display all configuration data.
A received packet can be set as the reference packet.
[0125]
According to this embodiment, the serial bus tester 20 _n The serial bus test controller 30 for a series of packets transmitted on the high-speed serial bus 1 including the packets transmitted from _n Since it can be taken into the capture memory 70 through a separate path and read out from the capture memory 70 later and desired processing such as display can be performed, the controller 30 _n Even without increasing the processing speed of the serial bus tester 20 _n Can capture a large number of packets transmitted on the high-speed serial bus 1 and transmit desired packets to other node devices in parallel.
[0126]
And serial bus tester 20 _n Data extraction / write circuit 60 of the physical layer circuit 4 _n And link layer circuit 5 _n In parallel with extracting the various data transmitted and received between them and writing to the capture memory 70, the index information analysis circuit 91 discriminates the packet from the extracted various data, and the packet on the capture memory 70 is classified by packet. Are stored in the index memory 90. Therefore, after the data is taken into the capture memory 70, the controller 30 for serial bus test _n Can quickly retrieve and retrieve the data of the desired packet in the capture memory 70 with reference to the index memory 90, so that the desired process for testing including the display of all configuration data can be quickly performed on the desired packet. Can be done. In addition, the index information analysis circuit 91 also analyzes the packet type, transfer speed, packet length, transmission destination ID, transmission source ID, and channel number during capture, and stores them in the index memory 90. , Controller 30 _n However, when it is desired to analyze various items for a desired packet in the capture memory 70, only the items that are not analyzed by the index information analysis circuit 91 need to be analyzed, and the entire analysis process can be quickly performed. Packet analysis results can be obtained quickly.
[0127]
In addition, the data extraction / write circuit 60 includes the physical layer circuit 4 after the desired reference timing, before the reference timing, or before and after the reference timing. _n And link layer circuit 5 _n Since various data transmitted and received between the two are extracted and stored in the capture memory 70, immediately after starting the desired operation on the node device to be tested, immediately before starting the desired operation, or starting the desired operation A test for a desired time range such as before and after the test can be easily performed.
At this time, since the timing at which the desired reference packet set and input by the operator is transmitted onto the high-speed serial bus 1 can be used as the reference timing, the reference timing for testing the desired time range is accurately determined. You can also.
[0128]
In the above-described embodiment, the header CRC error and data CRC error of the captured packet are analyzed by the controller of the serial bus tester after capture. When analyzing the index information of each packet based on the data DATA input from the data extraction / write control circuit and the write address CRA, and simultaneously indicating that the packet type is a packet including a header, The header CRC is calculated from the byte data, and it is determined whether or not there is a header CRC error by comparing whether or not it matches the value of the header CRC added at the end of the header. Indicates that each byte in the data block The data CRC is calculated from the data and compared with the value of the data CRC added at the end of the data block to determine whether or not there is a data CRC error. The header CRC error and the data CRC error Separately, data indicating the presence or absence of an error may be included in the index information and stored in the index memory.
In this case, the header CRC error and data CRC error determination circuit may be incorporated in the index information analysis circuit, but the serial bus tester link layer circuit also includes a header CRC error and data CRC error determination circuit. Therefore, the determination circuit incorporated in the link layer circuit may also be used.
[0129]
In addition, one or more items among the transfer rate, the packet length, the channel number, the transmission source ID, and the transmission destination ID as the primary items may be analysis items of the controller of the serial bus tester.
[0130]
In addition, the serial bus tester according to the above-described embodiment can be implemented using a general-purpose personal computer. For example, as shown in FIG. 16, the serial bus test expansion board 20 is added to a personal computer 120 including a CPU 101, a memory 102, a hard disk 103, a display device 104, and a keyboard 105 connected to the internal bus 100. Serial bus tester controller, memory, operation panel, display device (reference numeral 30 in FIG. 1) _n 10, 12, and 11) are implemented by the CPU 101, the memory 102 (providing a work area, etc.), the hard disk 103 (eg, storing test programs and test data), the keyboard 105, and the display device 104. The serial bus test expansion board 20 includes the physical layer circuit 4 _n , Link layer circuit 5 _n A data extraction / write circuit 60, a capture memory 70, a reference packet setting circuit 80, an index memory 90, an index information analysis circuit 91, and an I / F (interface) circuit 201 for connection to the internal bus 100. The CPU 101 performs link layer circuit 5 via the I / F circuit 21. _n The data extraction / write circuit 60, the capture memory 70, the reference packet setting circuit 80, the index memory 90, and the index information analysis circuit 91 are controlled and exchanged with various data.
[0131]
In the above-described embodiment, an example in which a controller is built in the serial bus tester has been described. However, the controller may be provided outside the serial bus tester body. For example, as shown in FIG. 17, for example, a personal computer 121 that implements the function of the controller may be provided outside the serial bus tester body 22. The personal computer 121 includes a CPU 123 connected to an internal bus 122, a memory 124, a hard disk 125, a display device 126, a keyboard 127, and an I / F (interface) circuit 128 for connecting to the serial bus tester body 22. Tester controller, memory, operation panel, display device (reference numeral 30 in FIG. 1) _n 10, 12, and 11) are implemented by the CPU 123, the memory 124, the hard disk 125, the keyboard 127, and the display device 124. The serial bus tester main body 22 includes the physical layer circuit _n , Link layer circuit 5 _n A data extraction / write circuit 60, a capture memory 70, a reference packet setting circuit 80, an index memory 90, an index information analysis circuit 91, and an I / F circuit 23 for connecting to a personal computer 121. The circuits 128 and 23 are connected by a cable 200. The CPU 123 is connected to the link layer circuit 5 via the I / F circuits 128 and 23. _n The data extraction / write circuit 60, the capture memory 70, the reference packet setting circuit 80, the index memory 90, and the index information analysis circuit 91 are controlled and exchanged with various data.
[0132]
【The invention's effect】
According to the present invention, when the data acquisition into the capture memory is completed, the index information has already been analyzed, so the serial bus test controller refers to the index memory and retrieves and reads the data of the desired packet in the capture memory. As a result, the desired processing for the test can be quickly performed on the desired packet. In particular, when it is desired to perform analysis processing on a desired packet in the capture memory, it is sufficient to analyze only items that are not analyzed by the index information analysis circuit, and the entire analysis processing can be performed quickly.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a serial bus test system including a serial bus tester according to an embodiment of the present invention.
FIG. 2 is a specific configuration diagram of a data extraction / write circuit in FIG. 1;
FIG. 3 is an explanatory diagram of reference packet designation data set in the reference packet setting circuit in FIG. 1;
4 is an explanatory diagram of the contents stored in the index memory in FIG. 1. FIG.
FIG. 5 is an explanatory diagram of the contents stored in the capture memory in FIG. 1;
6 is an explanatory diagram of storage contents of a capture memory in FIG. 1. FIG.
7 is an explanatory diagram of storage contents of a capture memory in FIG. 1; FIG.
FIG. 8 is an explanatory diagram of the contents stored in the index memory in FIG. 1;
FIG. 9 is an explanatory diagram of the contents stored in the index memory in FIG. 1;
FIG. 10 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the reference packet step over mode.
FIG. 11 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the reference packet start mode.
FIG. 12 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the reference packet stop mode.
FIG. 13 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the trigger signal step over mode.
FIG. 14 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the trigger signal start mode.
FIG. 15 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the trigger signal stop mode.
16 is a configuration diagram showing a modification of the serial bus tester of FIG. 1. FIG.
17 is a configuration diagram showing another modification of the serial bus tester of FIG. 1. FIG.
FIG. 18 is an explanatory diagram showing a connection example of a conventional high-speed serial bus.
FIG. 19 is an explanatory diagram showing an example of an isochronous packet format used in the high-speed serial bus.
FIG. 20 is an explanatory diagram showing an example of the format of an asynchronous packet used on the high-speed serial bus.
FIG. 21 is an explanatory diagram showing a connection example of a high-speed serial bus test system using a conventional serial bus tester.
[Explanation of symbols]
1 High-speed serial bus
1 ₁ 1 ₂ 1 _n-1 High speed serial bus cable
2 ₁ 2 ₂ 2 _n-1 Node equipment
10 Memory 11, 104, 126 Display device
12 Operation panel 105, 127 Keyboard
20 _n Serial bus tester 20 Expansion board for serial bus test
22 Serial bus tester body
30 _n controller
120, 121 Personal computer
4 _n Physical layer circuit 5 _n Link layer circuit
60 Data extraction / write circuit 70 Capture memory
80 Reference packet setting circuit 90 Index memory
91 Index information analysis circuit

Claims (14)

Connected to the serial bus, receives packet transmission signals from other node devices transmitted over the serial bus, converts them into received data, converts transmission data into transmission signals, and outputs them to the serial bus And a physical layer circuit connected to the physical layer circuit to generate a transmission packet addressed to another node device in accordance with an instruction from the controller for serial bus test, and transmit data constituting the transmission packet together with control signal data for handshake A link layer circuit that outputs to a physical layer circuit, inputs received data from the physical layer circuit together with control signal data for handshaking, extracts a predetermined received packet, and outputs it to a controller for serial bus testing; and a physical layer circuit Capture memory that temporarily stores data sent and received between the device and the link layer circuit A data extraction / write circuit connected to a signal line connecting the physical layer circuit and the link layer circuit, extracting data transmitted / received between the physical layer circuit and the link layer circuit, and writing the data to a capture memory. The bus test controller is a serial bus tester that performs a desired test process on a packet written in the capture memory, an index memory that temporarily stores index information of the packet temporarily stored in the capture memory, and
From the data extraction / write circuit, the packet is discriminated while inputting the data extracted by the data extraction / write circuit and the write position to the capture memory, and the index information including the packet type and the storage position on the capture memory is analyzed. An index information analysis circuit for storing the index information in the index memory for each packet;
With
When the controller for the serial bus test performs the desired test processing for the packet written in the capture memory, it first searches for the desired packet using the index information for each packet stored in the index memory. To obtain the index information and determine the storage position of the desired packet on the capture memory, and to read the data of the desired packet from the capture memory,
Serial bus tester characterized by. The data extraction / write circuit extracts the data transmitted / received between the physical layer circuit and the link layer circuit after the desired reference timing, before the reference timing, or before and after the reference timing, and writes the data to the capture memory.
The serial bus tester according to claim 1. The data extraction / write circuit
A reference packet specifying data setting circuit for setting data specifying a packet for reference timing; and
A comparison circuit for comparing data transmitted and received between the physical layer circuit and the link layer circuit with reference packet designation data;
When the extracted data matches the reference packet specification data, the data sent and received between the physical layer circuit and the link layer circuit is extracted after the reference timing, before the reference timing, or before and after the reference timing, and stored in the capture memory To write,
The serial bus tester according to claim 1. The index information includes part or all of the packet header information in addition to the packet type and the storage location on the capture memory.
The serial bus tester according to claim 1, 2 or 3. The serial bus tester according to claim 1, 2, 3, or 4, wherein the index information includes a packet transfer rate. The index information should include the presence or absence of packet errors,
The serial bus tester according to claim 1, 2, 3 or 4. The controller for the serial bus test is configured to add the analysis result for an arbitrary packet stored in the capture memory to the index memory as index information of the packet,
The serial bus tester according to claim 1, 2, 3, 4, 5, or 6. Connected to the serial bus, receives packet transmission signals from other node devices transmitted over the serial bus, converts them into received data, converts transmission data into transmission signals, and outputs them to the serial bus A physical layer circuit that is connected to the physical layer circuit and generates a transmission packet addressed to another node device in accordance with an instruction from an external controller for serial bus testing, and a control signal for handshaking the transmission data string constituting the transmission packet A link layer circuit that outputs data to the physical layer circuit, inputs a received data string from the physical layer circuit together with control signal data for handshaking, takes out a predetermined received packet, and outputs it to an external controller for serial bus testing; , Capture memory for temporarily storing data, physical layer circuit and link layer circuit A data extraction / write circuit connected to the connecting signal line to extract data sent and received between the physical layer circuit and the link layer circuit and write it to the capture memory. In the serial bus tester that enables the processing for the desired test to be performed on the packet written in
An index memory for temporarily storing index information of packets temporarily stored in the capture memory;
From the data extraction circuit, the packet is determined while inputting the data extracted by the data extraction circuit and the write position to the capture memory, and the index information including the packet type and the storage position on the capture memory is analyzed, and the packet is analyzed. Separately, an index information analysis circuit for storing index information in the index memory;
With
The external controller for serial bus test can read the index information of the packet stored in the index memory,
Serial bus tester characterized by. The data extraction / write circuit extracts the data transmitted / received between the physical layer circuit and the link layer circuit after the desired reference timing, before the reference timing, or before and after the reference timing, and writes the data to the capture memory.
The serial bus tester according to claim 8. The data extraction / write circuit
A reference packet specifying data setting circuit for setting data specifying a packet for reference timing; and
The data sent and received between the physical layer circuit and the link layer circuit is compared with the reference packet designation data, and the physical layer circuit and the link layer circuit after the reference timing, before the reference timing, or before and after the reference timing, with the coincidence as the reference timing To extract the data sent and received between and write to the capture memory,
The serial bus tester according to claim 8. The index information includes part or all of the packet header information in addition to the packet type and the storage location on the capture memory.
The serial bus tester according to claim 8, 9, or 10. 12. The serial bus tester according to claim 8, 9 or 10 or 11, wherein the index information includes a packet transfer rate. The index information should include the presence or absence of packet errors,
12. The serial bus tester according to claim 8, 9 or 10 or 11. In the index memory, the result of analyzing an arbitrary packet stored in the capture memory by an external controller for serial bus test can be added to the index memory as index information of the packet,
The serial bus tester according to claim 8, 9, 10, 11, 12, or 13.

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