JP3790653B2 - Shared memory access management device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shared memory access management apparatus that controls access to a shared memory shared by a plurality of processes.
[0002]
[Prior art]
Conventionally, when a plurality of processes being executed in parallel on a computer cooperate to perform some processing, information necessary for executing the processing is exchanged via a shared memory.
For example, when the process A passes data to the process B, the process A writes the data in the shared memory, and then the process B reads the data. However, in order for this procedure to proceed correctly, it is necessary for each process to control the other party's operation according to the progress of its own processing. The process A needs to notify the process B of the completion of the data writing, and if the process B side does not notify the process A of the completion of the data reading, new data to the shared memory by the process A thereafter Cannot write.
[0003]
A flag is used to perform such control. In the above example, the process A starts writing data from a state where the flag is OFF, and sets the flag to ON when the writing is completed. The process B does not access the shared memory while the flag is OFF, starts reading data from the shared memory when the flag is ON, and sets the flag to OFF when the reading is completed. Then, the process A can recognize that the next data can be written.
[0004]
Since such a flag is set / referenced by a plurality of processes as in the above example, it is also provided in the shared memory. That is, when a plurality of processes perform processing while exchanging data using a shared memory, the shared memory controls an area for writing / reading data (hereinafter referred to as “data area”) and the progress of the process. Area for which a flag is provided (hereinafter referred to as “control flag area”).
[0005]
Processes A and B operate according to their values while periodically referring to the control flag area (hereinafter referred to as “polling”).
However, if the shared memory is a dual port type having a plurality of ports that accept access from the process, in order to guarantee the correct operation of the process for processing using the shared memory, access from multiple processes (write : Data write and control flag update, read: data read and control flag reference) must be prevented from colliding. The collision means that a plurality of processes simultaneously access an area of the same address in the memory, and it does not occur unless it is a dual port type memory.
[0006]
The following pattern occurs when process access to shared memory conflicts:
Pattern 1: write and write (data write or flag update) collide. A state in which multiple processes attempt to write or update at the same location in the memory at the same time. The memory cell may be destroyed.
Pattern 2: write and read (data writing and reading or flag update and reference) collide. The content read by the process on the Read side may become indefinite, and the result of the operation performed based on the read content may be invalid.
[0007]
In the case of the above example, the pattern 1 does not occur in the data area and the control flag area from the contents of the operation procedures of the processes A and B. Pattern 2 does not occur as far as the data area is concerned, unless there is an error in the result of reading the control flag. However, the occurrence of pattern 2 cannot be prevented for the control flag area. If the update of the flag and the reference collide and the content of the flag becomes indefinite, the read flag can be recognized as either “0” or “1”.
[0008]
If the value of the read control flag becomes undefined as a result of the occurrence of pattern 2, the process may malfunction. An example of malfunction is given below.
The process A causes the process B to process the data after passing the data through the data area. Consider a process in which there are two processing patterns, and process A indicates one of them by a flag. In the control flag area, a flag indicating a machining pattern is provided in addition to the above-described flag indicating completion of data writing.
[0009]
The value of the control flag area and the operation of both processes according to the value are shown below. The upper 1 bit is a flag indicating a processing pattern (0: first processing pattern, 1: second processing pattern), and the lower 1 bit is a flag indicating completion of data writing.
(1) 00: Process A is writing data to the data area.
(2) 01: Process A completes data writing. Process B reads the data and processes it with the first processing pattern.
(3) 11: Process A completes data writing. Process B reads the data and processes it with the second processing pattern.
[0010]
Here, when the process A completes the data writing to the data area, the process A rewrites the value of the control bit area with 2 bits in order to instruct the process B to process the data with the second processing pattern. Change from “00” to “11”. When the control bit area is referred to by the process B at the moment of the change, both of the updated 2-bit flags are undefined. Therefore, the process B can recognize the value of the bit string as any of “00”, “01”, “10”, and “11”.
[0011]
Of course, there is no problem when correctly reading “11”, and when reading “00”, the process B repeats polling, and the value is correctly recognized as “11” at the next reference, so there is no problem. However, if it is determined as “01”, the process B performs a malfunction of data processing in the first processing process. Furthermore, if the pattern is recognized as “10”, it may be determined that an abnormal situation has occurred and the process may be stopped.
[0012]
Although not applicable to the above example, if a situation occurs in which write access to the data area collides due to misreading of the value of the control flag, serious consequences such as destruction of data in the data area will occur. It is also possible.
In order to surely prevent such a malfunction, it is only necessary to prevent an access conflict that may cause a malfunction, and the means for that is exclusive control over the shared memory.
[0013]
A typical exclusive control method is a semaphore management method that allows access to only one process using a signal. As a specific method thereof, there is a method using hardware, and as a general example of exclusive control by hardware, there is a method in which a memory device as an entity of shared memory generates an exclusive control signal. . A memory device generates a busy signal while one process is accessing the memory, limiting access to the memory by other processes. The busy signal is transmitted to the process via a WAIT signal line of a device (CPU or the like) that is the subject of the process execution, and the process does not access the shared memory while the busy signal is input from the WAIT signal line. Therefore, access conflicts that cause malfunctions do not occur.
[0014]
Although there is a method of using a control flag for exclusive control of the shared memory, the control flag itself is provided in the shared memory, and access conflict cannot be reliably eliminated for the flag. Hardware must be used as a means for reliable exclusive control.
[0015]
[Problems to be solved by the invention]
However, for exclusive control by hardware, a memory device that generates a busy signal is required as dedicated hardware, and the device that performs the process is equipped with a function that supports exclusive control by such a busy signal. If not, exclusive control cannot be realized unless a circuit for exclusive control is separately provided outside the device. An abnormal situation may also occur depending on the specifications related to exclusive control of devices to be combined. For example, when a process execution device stops a process that is executing access, it is a specification that stops without instructing the memory to release exclusive control (stop the busy signal). If the function corresponding to the situation is not provided, other processes that are kept waiting by the busy signal will stop due to timeout after continuing the waiting.
[0016]
In view of the above problems, the present invention does not perform exclusive control by hardware for the shared memory provided with the control flag, and as a result, even if the value of the control flag read by the process becomes indefinite, the process operates correctly. An object of the present invention is to provide a shared memory access management device that can be made to operate.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, the shared memory access management device of the present invention is configured such that each process is a self-process in an environment in which a plurality of processes sharing a dual-port memory perform processing in cooperation using the memory. A shared memory access management device provided for managing access to the memory, wherein the memory is composed of a plurality of bits, and a value is updated in accordance with a progress of processing performed in cooperation with the plurality of processes. Control information is included, and the shared memory access management device includes: a detection unit that detects a value of the control information; an update unit that updates the value of the control information; and a value of the control information detected by the detection unit. The detection means repeats the operation of detecting the value of the control information until it is updated by another process and changes to a predetermined value. When the processed value changes to the predetermined value, the process is instructed to perform an operation related to the process, and when the operation by the process is completed, the update unit is instructed to relate to the operation of the control information. And instructing means for updating one bit.
[0018]
As a result, when updating the control information, only one bit is updated at a time, and when the control information is read, the control information is used until the value of the control information reaches a predetermined value (updated). Since only the information is read out, the control information value is recognized as either the correct updated value or the pre-update value even if the control information value read due to an access conflict becomes indefinite. Is done. Of course, there is no problem if it is correctly detected as a value after update. Even if it is detected as a value before update, the control information reference is executed again, and this reference is recognized as the value after update correctly. Does not occur. Therefore, it is possible to prevent the process from malfunctioning due to an access conflict without performing hardware exclusive control on the shared memory control information.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the shared memory access management apparatus of the present invention will be described with reference to the drawings. The shared memory in the present embodiment is divided into a data area and a control flag area, and is used for data transfer between two processes and setting / referencing of control information.
[0020]
FIG. 1 is a schematic diagram showing the contents of processing performed by two processes using a shared memory in the present embodiment. The process A is a data transfer process in which data to be transferred is generated and passed to the process B, and the process B processes this data and outputs it to the data transfer destination. However, the timing at which the process B outputs the data to the transfer destination is determined by the process A in response to an instruction from a higher-level process (not shown), and the process B is instructed.
[0021]
The transfer data and the output timing instruction are exchanged between the two processes via the shared memory 10. The transfer data is written in the data area 12 in the shared memory, and the output timing instruction is written in the control flag area 12. The control flag area 11 is provided with a flag for both processes to inform the other party of the progress of each process, and the output timing is also indicated by such a flag.
[0022]
Both processes A and B are divided into a management unit and a data processing unit based on the contents of the operation.
The data processing unit A1 on the process A side generates and writes data to be transferred, determines an output timing, and initializes the shared memory 12 after the transfer is completed.
The data processing unit B1 on the process B side reads transfer data, processes data, and transfers data.
[0023]
Each of the management unit A2 on the process A side and the management unit B2 on the process B side updates / references the flag in the control flag area 11 as the processing proceeds.
This data transfer process can be divided into the following four stages.
First stage: Until data writing to the shared memory 12 by the process A is completed.
Second stage: From the end of data writing by the process A until the process A instructs the process B to start data transfer.
Third stage: Until process B finishes data transfer.
Fourth stage: Until the process A finishes the post-processing (returns the shared memory 12 to the initial state).
[0024]
FIG. 2 is a schematic diagram showing the configuration of the shared memory 10.
The shared memory 10 includes a control flag area 11 and a data area 12, and the actual hardware is a dual port type memory device.
Data to be transferred is written in the data area 12. Writing is performed by the writing process A, and reading by the reading process B.
[0025]
The control flag area 11 is an area in which flags for controlling the content and timing of the operation of each process are provided, and here, it is composed of two types of flags.
Of these two types of flags, one is the “valid flag 111” and the other is the “change flag 112”.
The valid flag 111 is used by the process A to instruct the process B to read data in the data area 12 and transfer it to the transfer destination. Setting is performed by the process A for both ON setting and OFF setting. The process A determines the timing at which the process B starts data transfer based on an instruction from the host process, and sets the valid flag 111 to ON. When the process B detects that the written transfer data has been read / transferred, the valid flag 111 is set to OFF. (Detection of completion of reading is performed by the change flag 112. Details of the change flag 112 will be described below.)
The change flag 112 indicates the presence / absence of transfer target data in the data area 12. It is set ON by the process A when the process A on the data writing side completes the data writing to the information part, and is set OFF by the process B when the transfer data written by the process B is completed. In other words, the change flag 112 is an “exclusive control” flag for the data area 12 so that the data writing by the process A and the data reading by the process B do not collide with each other in the data area 12.
[0026]
Both the process A and the process B periodically access the control flag area 11 and refer to the value (polling). Then, it operates according to the value of the control flag area 11.
By the combination of the above two types of flags, the value of the control flag area 11 becomes the following four patterns. These patterns change as follows corresponding to the four stages of the transfer process described above.
[0027]
00 → 01 → 11 → 10 → 00
At any stage of the transition, of the 2-bit flags in the control flag area 11, only one flag changes (the values of both of the two flags do not change at the same time). Such a transition is said to transition when the intersymbol distance is 1. This indicates that only one flag (bit) is indeterminate even when the flag update and reference collide and the value of the control flag area 11 becomes indefinite.
(Transfer processing sequence)
Hereinafter, the progress of the data transfer process, the operation performed by the process A and the process B according to the progress of the process, and the state transition of the control flag area 11 accompanying the progress of the process will be described with reference to the sequence diagram.
[0028]
FIG. 3 is a sequence diagram showing the progress of the data transfer process and the change in the contents of the shared memory 10 accompanying this.
Both process A and process B periodically poll the control flag area 11 of the shared memory 10 to read the value of the control flag area 11 and operate according to the read flag value.
[0029]
First, although the value of the control flag area 11 is “00”, this is a state in which writing of transfer data to the data area 12 by the process A has not been completed (before starting writing or in the middle of writing). is there. In this state, the process A writes the transfer data to the data area 12 and the process B only polls the control flag area 11.
[0030]
In this state, transfer data is generated on the process A side. Then, as a result of polling, the process A accesses the data area 12 and starts writing the transfer data 120 at the timing when the value of the control flag area 11 is detected as “00” ((1) in the figure) ( (2) in the figure). If the value of the control flag area 11 is other than “00”, the process A does not access the data area 12 and repeats polling until the value of the control flag area 11 is detected as “00”.
[0031]
Then, the process A continues to write the transfer data 120 to the data area 12, and when the writing is completed, the change flag 112 is set to ON (the value of the control flag area 11 is changed to “01” ((3) in the figure)). ▼)).
Next, the value of the control flag area 11 is “01”. This is because the transfer data is written to the data area 12 by the process A, but the transfer data is read / transferred by the process B. The start timing has not been reached. In this state, the process A measures the timing for allowing the process B to read and transfer the transfer data, and the process B only polls the control flag area 11.
[0032]
Thereafter, the process A measures the data transfer start timing in accordance with an instruction from the upper process, and if it determines that the transfer start timing has been reached, the process A sets the valid flag 111 ON to instruct the process B to read / transfer the transfer data. (The value in the control flag area 11 is changed to “11” (4) in the figure).
Then, the value of the control flag area 11 is “11”, which is a state in which reading / transfer of transfer data by the process B is permitted. Until this state is reached (between (1) to (4) above), the process B is only polling the control flag area 11, but as a result of polling, the value of the control flag area 11 is "11". Is detected (<5> in the figure), the process B accesses the data area 12, reads the transfer data 120, processes it, and transfers it to the transfer destination process (see FIG. 1) (see FIG. 1). Middle (6)). On the other hand, the process A performs only polling to the control flag area 11.
[0033]
When the process B completes reading / transfer of the transfer data 120, the change flag 112 is set to OFF (the value of the control flag area 11 is changed to “10” (7) in the figure).
Then, the value of the control flag area 11 is “10”, which is a state in which reading / transfer of the transfer data from the data area 12 by the process B is completed.
[0034]
On the other hand, when the value of the control flag area 11 is detected as “10” by polling ((8) in the figure), the process A recognizes that the data transfer by the process B is completed, and sets the data area 12 After initialization, the value of the control flag area 11 is returned to the initial value “00” (the valid flag 111 is set to OFF ((9) in the figure)). Thereby, a series of data transfer processing is completed. In this state, the process B is only polling the control flag area 11.
[0035]
In this way, both processes operate in the above order according to the state of the control flag area 11, and data transfer processing is performed.
(Process behavior)
Next, the operation of each of the processes A and B in the data transfer processing according to the present embodiment will be described with reference to the drawings centering on the management units A2 and B2.
[0036]
FIG. 4 is a flowchart showing the operation of the process A.
First, in accordance with the activation of the process A, the management unit A2 starts polling to the control flag area 11, and repeats the polling until the value of the control flag area 11 is detected as “00” (S401: Yes). Then, the data processing unit A1 is instructed to generate transfer data and write it to the data area 12 (S402), wait for the writing completion notification from the data processing unit A1 (S403: Yes), and change flag 112 is set to ON (“00” → “01”) (S404).
[0037]
Next, the management unit A2 waits for an output timing determination notification from the data processing unit A1 (S405: Yes), and sets the valid flag 111 to ON ("01" → "11") (S406).
Thereafter, the management unit A2 restarts polling of the control flag area 11 and repeats until it detects “10” (S407). And then. When “10” is detected, the data processing unit A1 is instructed to initialize the data area 12 (S408), and a notification of completion of initialization from the data processing unit A1 is waited (S409: Yes). 111 is set to OFF (“10” → “00”) (S410).
[0038]
FIG. 5 is a flowchart showing the operation of the process B.
First, in accordance with the activation of the process B, the management unit B2 starts polling the control flag area 11, and repeats the polling until the value of the control flag area 11 is detected as “11” (S501: Yes). Then, the data processing unit B1 is instructed to perform a series of processes of reading transfer data from the data area 12, processing, and transfer to the transfer destination (S502), and notification of completion from the data processing unit B1 to the transfer is performed. (S503: Yes), the change flag 112 is set to OFF ("11" → "10") (S504).
[0039]
The processes A and B realize the data transfer process by performing the above operation, but here, the exclusive control by the hardware busy signal or the like is not performed for the access to the shared memory 10 of both processes. For this reason, the update of the control flag area 11 and the reference (polling) collide, resulting in a situation where the referenced value becomes indefinite. In order for the data transfer processing to be performed correctly, even if the control bit section 12 is updated and the reference conflicts and the value of the control bit referred to is indefinite, the data transfer processing procedure is caused by this. It is a precondition that there is no malfunction such as going wrong (for example, data reading by process B starts when data writing by process A is not finished).
(Verification of operation)
In the present embodiment, the process progress status and the value of the control flag area 11 are associated with each other so that the value of the control flag area 11 transitions at “inter-code distance = 1” according to the process progress status. Thus, even if the value of the referenced control bit becomes indefinite, no malfunction occurs.
[0040]
Hereinafter, at each timing when the value of the control flag area 11 is updated, the operations of both processes when the flag update and the flag reference collide are verified, and the value of the referenced control flag area 11 becomes indefinite. Confirm that no malfunction occurs. Since the value of the control flag area 11 is updated at four locations, the verification is sequentially performed.
(1) Timing from “00” to “01”
FIG. 6 shows that when the process A sets the change flag 112 to ON at the start of writing the transfer data to the data area 12 ((2) in FIG. 3), the control flag area 11 is referred to by polling of the process B. Indicates the case of a collision.
[0041]
In this case, since only the value of the change flag 112 to be updated in the control flag area 11 becomes indefinite, the process B recognizes the value of the control flag area 11 as “00” or “01”.
Since the process B can access the data area 12 only when the valid flag 111 is ON, the process B only repeats polling to the control flag area 11 regardless of which pattern is read. It is. Therefore, no malfunction occurs.
[0042]
(2) Timing from “01” to “11”
FIG. 7 shows a case where the reference of the control flag area 11 by the process B collides when the process A sets the valid flag 111 ON when the transfer data writing to the data area 12 is completed.
[0043]
In this case, since only the value of the valid flag 111 to be updated in the control flag area 11 is indefinite, the process B recognizes the value of the control flag area 11 as “01” or “11”.
When it is recognized as “11”, since the valid flag 111 is ON, the process B accesses the data area 12 according to the procedure and starts reading / transferring data. At this point, since the transfer data is actually written to the data area 12, the transfer data can be read correctly, and no malfunction occurs.
[0044]
On the contrary, when “01” is recognized, the process B returns to the state before the access collision, but since the valid flag 111 is OFF, the reference of the control flag area 11 is repeated after a certain time interval. At the next polling, the value of the control flag area 11 is no longer indefinite, and the process B correctly reads “11” as the value of the control flag area 11 and starts reading / transferring the transfer data according to the procedure. As a result, no malfunction occurs.
[0045]
(3) Timing from “11” to “10”
FIG. 8 shows a case where the reference process of the control flag area 11 by polling of the process A collides when the process B completes the reading of the transfer data from the data area 12 and sets the change flag 112 to OFF. .
[0046]
In this case, since only the value of the change flag 112 to be updated in the control flag area 11 is indefinite, the process A recognizes the value of the control flag area 11 as “11” or “10”.
If it is recognized as “10”, since the change flag 112 is OFF, the process A determines that the transfer data read / transfer by the process B is completed, and initializes the shared memory 10 (clear and valid flag of the data area 11). 111 is set to OFF), and the data transfer process is terminated. At this point, since the read / transfer of the transfer data has actually been completed, there is no problem even if the shared memory 10 is initialized and the process is terminated.
[0047]
Conversely, if it is recognized as “11”, the process A returns to the state before the access collision, determines that the transfer data read / transfer by the process B has not yet been completed, and thereafter the control flag by polling The reference of the area 11 is repeated, and the process waits until the value of the control flag area 11 becomes “10”. At the next polling, the value of the control flag area 11 is no longer indefinite, and the process A correctly recognizes the value of the control flag area 11 as “10” and initializes the shared memory 10 according to the procedure. Therefore, no malfunction occurs.
[0048]
(4) Timing from “10” to “00”
FIG. 9 illustrates a case where the process A, which has determined that the data read / transfer by the process B has been completed, collides with the reference to the control flag area 11 by the process B when the valid flag 111 is set to OFF.
[0049]
In this case, only the value of the valid flag 111 to be updated in the control flag area 11 becomes indefinite, and the process B recognizes the value of the control flag area 11 as “10” or “00”.
In any case, since the process B only polls the control flag area 11 as already described with reference to FIG. 3, no malfunction occurs.
(Summary)
As described above, in this embodiment, even if the value of the control flag area 11 referred to by the access conflict becomes indefinite, both processes, particularly the management in the processes, are prevented so as not to cause a malfunction. Since the operations of the units A2 and B2 are defined, the data transfer process is performed correctly even without exclusive control by hardware. The contents and meanings of the rules will be described below with reference to the drawings.
[0050]
FIG. 10 is a diagram showing the contents of access to the shared memory 10 of both processes in the present embodiment in a table format along the transition of the control flag area 11.
FIG. 11 is a diagram showing state transition of the control flag area 11 in the present modification.
As can be seen from the above description and FIGS. 10 and 11, in this embodiment, two processes jointly perform data transfer processing. In both processes, the value of the control flag area 11 is also changed at “inter-code distance = 1” in accordance with the progress of the transfer process in four stages. Therefore, a state of “01” (only data writing is completed, reading / processing is not permitted) which is not necessarily provided in view of the progress of the transfer process is provided. As a result, the value of the control flag area 11 is updated from “00” to “11” to prevent the 2-bit value from becoming indefinite.
[0051]
By setting the rule that the value of the control flag area 11 is changed when “inter-code distance = 1”, the control flag area 11 update operation by one process is changed to the control flag area 11 update operation by the other process. If the references collide, only the 1-bit value is undefined. For this reason, the reference process always recognizes the value of the control flag area 11 in one of two patterns. One is a correct value (value after update as intended by the flag update process), and the other is a value before the flag update process is updated.
[0052]
However, as shown in FIG. 10, the process on the side that refers to the control flag area 11 at each stage refers to the control flag area 11 (polling) until it detects the value of the control flag area 11 as a predetermined value. ) Only, and the operation related to the progress of the transfer process is not performed. On the other hand, the process on the side of updating the control flag area 11 completes the operation related to the progress of the transfer process, and then the control flag area The value of 11 is updated by 1 bit.
[0053]
As a result, when the correct value is recognized, the referencing process naturally performs the subsequent operations according to the procedure. On the other hand, when the value before the update is recognized, the reading side process returns to the state before the flag reference operation in which the collision has occurred, and the control flag area 11 is referred again. In the next reference, the value in the control flag area 11 is correctly recognized as the updated value, and the next operation is performed according to the procedure.
[0054]
The malfunction is that the process on the reference side erroneously recognizes the value of the control flag, and as a result, performs an operation different from the intention of the process that updated the flag, or performs an operation different from the procedure. However, in the case of the present embodiment, as described above, even if the referencing process mistakenly recognizes the flag as the pre-update value, the flag reference operation (polling) is performed only once. Since the intention of the updating process is correctly recognized and the operation is performed according to the procedure, no malfunction occurs.
[0055]
In the present embodiment, the shared memory 10 further includes an area (data area 12) for setting information other than the control information. However, some control flags are included in this area. (Change flag 112) prevents access conflicts that cause malfunctions. That is, for the data area 12 of the shared memory 10, the access conflict is prevented by the information set in the control flag area 11, and the value of the control flag area 11 is read as a result of the access conflict as described above. Even if the value becomes indefinite, no malfunction occurs.
[0056]
According to the present embodiment, the hardware to the shared memory can be used not only when there is only a control flag area in the shared memory but also when an area other than the control flag is set. This shows that the process can be executed without malfunction without the exclusive control.
In this embodiment, each bit included in the control information is used as a flag. However, even when the control information is referred to as a bit pattern of multiple bits instead of as a collection of flags, the processing is performed. As long as the transition of the bit pattern with the progress of the code follows the rule “distance between codes = 1”, it is possible to obtain the same effect as in the present embodiment.
[0057]
Further, although the control flag area in the above embodiment is 2 bits, the present invention can also be applied to the case where a control flag area of 3 bits or more is used. For example, in the above embodiment, the effective flag 111 that is an instruction of the “data transfer” execution timing is a transfer instruction bit string (2 bits, 01: pattern) that is an instruction to “transfer after processing with the processing pattern A or processing pattern B”. Consider the case where A is changed to processing / transfer and 10: processing / transfer is performed with pattern B).
[0058]
The flow of the data transfer process in this modification will be described together with the change in the value of the control flag area. Description of the same parts as those in the embodiment is omitted.
(1) 000: Indicates that writing of transfer data to the data area 12 by the process A is not completed. Same as “00” in the embodiment (see FIG. 3).
{Circle around (2)} 001: Indicates that the process A has completed writing the transfer data to the data area 12, but the process B cannot read or transfer the transfer data. Same as “01” (see FIG. 3) in the embodiment.
{Circle around (3)} 011 or 101: State in which transfer / reading of transfer data by process B is permitted. This corresponds to “11” in the embodiment (see FIG. 3). Process B reads the transfer data, processes it with pattern A if it is “011”, and processes it with pattern B if it is “101”, and transfers it to the transfer destination.
{Circle around (4)} 010 or 100: State in which reading / transfer of transfer data from the data area 12 by the process B is completed. This corresponds to “10” (see FIG. 3) in the embodiment. From here, the process A initializes the shared memory and returns to (1).
[0059]
FIG. 12 is a diagram showing state transition of the control flag area in the present modification.
As shown in the figure, also in this modification, the value of the control flag area is as follows: (1) “000” → (2) “001” → (3) “101” → (4) “100” → (1) ▼ “000” or ▲ 1 ▼ “000” → ▲ 2 ▼ “001” → ▲ 3 ▼ “011” → ▲ 4 ▼ “010” → ▲ 1 ▼ “000” To do. Further, the process on the reference side of the control flag area 11 only refers to the control flag area until it detects the value of the control flag area as a predetermined value, and does not perform an operation related to the progress of the work. The point is the same as the above embodiment. Therefore, as described in the embodiment, no malfunction occurs without performing exclusive control on the shared memory.
[0060]
In the above-described embodiment and modification, the data transfer process has been described as a process performed by a plurality of processes. However, this is given as an example, and the scope of the present invention is limited to the data transfer process. is not. For example, a process in which a certain process passes data to another process, performs some processing on the data, and returns the data is also conceivable. In this case, the control information is used to instruct the timing of data transfer before and after processing, the type of processing, and the like. However, any processing content is applicable as long as the content can be managed in association with the control information that transitions with “distance between codes = 1”.
[0061]
【The invention's effect】
As described above, in the shared memory access management device of the present invention, in an environment where a plurality of processes sharing a dual port type memory perform processing in cooperation using the memory, each process has the memory of its own process. A shared memory access management device provided for managing access to the memory, wherein the memory includes control information that is composed of a plurality of bits and whose values are updated according to the progress of processing performed in cooperation with the plurality of processes. The shared memory access management device includes: a detecting unit that detects the value of the control information; an updating unit that updates the value of the control information; and a value of the control information detected by the detecting unit is determined by another process. A value detected by the detection unit by causing the detection unit to repeat the operation of detecting the value of the control information until it is updated and changes to a predetermined value. When the value changes to the predetermined value, the process is instructed to perform an operation related to the process, and when the operation by the process is completed, the update unit is instructed to transmit one bit related to the operation in the control information. Therefore, the control information consisting of a plurality of bits in the shared memory can be processed by the plurality of processes using the control information without performing exclusive control by hardware. No malfunction occurs in the process to be executed.
[0062]
Further, the shared memory includes a data part used by the plurality of processes to exchange data other than the control information, and the control information includes one or more exclusive control flags for exclusive control with respect to the data part. Including the process performed by the plurality of processes in cooperation with each other is a data transfer performed through the data unit, and the instruction unit is based on the value of the exclusive control flag detected by the detection unit, It is also possible to cause the process to perform an operation related to the data transfer, and to instruct the updating means to update the 1 bit of the exclusive control flag when the operation is completed. As a result, if there is a mixture of control information and other data in the shared memory, the area for storing data other than the control information is for exclusive control that is set as part of the control information. For areas where exclusive control is realized by information and control information is set, malfunction does not occur even without exclusive control, so there is no need to perform exclusive control by hardware for the entire shared memory. No malfunction occurs in processing executed by a plurality of processes.
[0063]
In order to reliably obtain the above-described effect, when the plurality of bits of the control information are inverted after the operation performed by the instruction unit in the process is completed, the update is sequentially performed for each of the plurality of bits. It is also possible to instruct and reverse the means.
A data communication method in which a plurality of processes sharing a dual port type memory perform data communication using the memory, and the memory includes a plurality of values whose values are updated by the plurality of processes as data communication progresses. A flag comprising bits, and the data communication method includes a writing step in which one process writes data to the memory, and the one process having completed the writing step inverts one bit included in the flag. A first inversion step, a second inversion step in which the one process that has completed the first inversion step inverts another one bit included in the flag, and another one process, A detecting step for detecting inversion of the one bit and the other one bit, and the other one having finished the detecting step. Process, if the data communication method characterized by comprising the steps of: reading the data written in the memory, without performing exclusive control of the shared memory by the hardware, can perform data communication without erroneous operation
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an outline of a transfer process performed by a plurality of processes using a shared memory in an embodiment of a shared memory access management apparatus according to the present invention.
FIG. 2 is a diagram showing a configuration of a shared memory in the same embodiment.
FIG. 3 is a schematic diagram showing the progress of transfer processing and the accompanying transition of the contents of the shared memory in the embodiment;
FIG. 4 is a flowchart showing an operation of a process A in the same embodiment.
FIG. 5 is a flowchart showing an operation of a process B in the same embodiment.
FIG. 6 is a schematic diagram showing a result of access collision to a control flag area in the same embodiment;
FIG. 7 is a schematic diagram showing a result of collision of access to a control flag area in the same embodiment;
FIG. 8 is a schematic diagram showing a result of collision of access to a control flag area in the same embodiment;
FIG. 9 is a schematic diagram showing a result of collision of access to a control flag area in the same embodiment;
FIG. 10 is a diagram showing, in a tabular form, the relationship between the value of a control flag area and the contents of shared memory access by a plurality of processes in the embodiment.
FIG. 11 is a state transition diagram showing a transition of a value of a control flag area in the same embodiment.
FIG. 12 is a state transition diagram showing a transition of a value of a control flag area in a modification of the embodiment.
[Explanation of symbols]
1 Shared memory
11 Flag area for control
111 Valid flag
112 Change flag
12 Data area
120 data
A, B process
A1, B1 Data processing part
A2, B2 Management Department

Claims (3)

In an environment in which a plurality of processes sharing a dual port type memory cooperate to perform processing using the memory, each process is a shared memory access management device provided for managing access to the memory of its own process. And
The memory includes control information that consists of a plurality of bits and whose value is updated according to the progress of processing performed in cooperation with the plurality of processes.
The shared memory access management device includes:
Detecting means for detecting a value of the control information;
Updating means for updating the value of the control information;
Until the value of the control information detected by the detection means is updated by another process and changes to a predetermined value, the detection means repeats the operation of detecting the value of the control information, and the value detected by the detection means When changing to a predetermined value, instructing the own process to perform an operation related to the processing, and when inverting a plurality of bits of the control information after the operation by the own process is completed, for each of the plurality of bits, Instructing means for sequentially instructing and inverting the updating means and transmitting the progress of the processing to the other process
A shared memory access management device comprising: The shared memory includes a data part used by the plurality of processes to pass data other than the control information,
The control information includes one or more exclusive control flags for exclusive control with respect to the data part,
The processing performed by the plurality of processes in cooperation is data delivery performed through the data portion,
The instructing unit causes the self process to perform an operation related to the data transfer based on the value of the exclusive control flag detected by the detecting unit , and after the operation is completed , a plurality of the exclusive control flags The shared memory access management device according to claim 1 , wherein when the bit is inverted, each of the plurality of bits is sequentially instructed to the update unit and inverted . A data communication method in which a plurality of processes sharing a dual port memory perform data communication using the memory,
The memory includes a flag composed of a plurality of bits whose values are updated by the plurality of processes according to the progress of data communication, and the data communication method includes:
A writing step in which one process writes data to the memory;
A first inversion step in which the one process that has finished the writing step inverts one bit included in the flag;
A second inversion step in which the one process that has finished the first inversion step inverts another one bit included in the flag;
A sensing step in which another process detects the inversion of the one bit and the other one bit;
The data communication method characterized in that the other process that has finished the detecting step includes a reading step of reading data written in the memory.

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