JP3792082B2 - Signal processing circuit device for magnetic disk drive and magnetic disk drive - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic disk drive device for recording and reproducing signals on a magnetic disk, and more particularly to a signal processing circuit device thereof.
[0002]
[Prior art]
FIG. 3 shows a block diagram of an FDD (floppy disk drive) device which is one of magnetic disk drive devices. In the figure, 1 is an interface drive circuit, 2 is a control circuit, 3 is a read / write circuit, 4 is a stepping motor drive circuit, 5 is a spindle motor drive circuit, 6 is a read / write head, 7 is an erase head, and 8 is a stepping motor. , 9 is a spindle motor, 10 is an index sensor, 11 is a track sensor, and 100 is an external host device such as a personal computer.
[0003]
The interface drive circuit 1, the control circuit 2, the read / write circuit 3, and the stepping motor drive circuit 4 collectively constitute one integrated circuit device (hereinafter referred to as “signal processing circuit device for FDD device”) 60. ing.
[0004]
The operation of each part will be described. The interface drive circuit 1 is a magnetic recording medium (not shown) that is a magnetic recording medium that exchanges data between the host device 100 and the control circuit 2 and exchanges between the host device 100 and the read / write circuit 3. The format of data written to the disk and the data read from the magnetic disk and the transfer method are matched.
[0005]
The control circuit 2 controls writing and reading of data with respect to the magnetic disk in accordance with data input from the host device 100 via the interface drive circuit 1, and also displays data indicating the operating state of the FDD device, etc. 1 to the host device 100.
[0006]
Under the control of the control circuit 2, the read / write circuit 3 writes and reads data to and from the magnetic disk in accordance with data input from the host device 100 via the interface drive circuit 1 when data is written. The data is written to the magnetic disk by passing a current through the coils constituting the read / write head 6 for erasing and the erase head 7 for erasing the data recorded on the magnetic disk. On the other hand, at the time of data reading, data is read from the magnetic disk by a voltage generated in a coil constituting the read / write head 6 in accordance with the data recorded on the magnetic disk, and the read data is sent to the host device via the interface drive circuit 1. Output to 100.
[0007]
The stepping motor drive circuit 4 drives a stepping motor 8 that moves the read / write head 6 and the erase head 7 in the radial direction of the magnetic disk under the control of the control circuit 2. The spindle motor drive circuit 5 drives a spindle motor 9 that rotates the magnetic disk under the control of the control circuit 2.
[0008]
The index sensor 10 determines whether the magnetic disk is rotating normally, and the track sensor 11 determines whether the read / write head 6 and the erase head 7 are located on the outermost periphery of the magnetic disk. It is for detection.
[0009]
[Problems to be solved by the invention]
In the conventional signal processing circuit device for the FDD device, when a power supply voltage higher than the maximum rated value is applied due to an erroneous insertion of a power connector, the output circuit or the like is turned on, and an overcurrent ( Otherwise, the circuit element may be destroyed by overvoltage).
[0010]
For this reason, the yield has been reduced by products that are defective due to human error (such as incorrect insertion of a power connector) in the manufacturing process. In addition, there are many replacement operations of circuit devices for relieving defective products, and productivity has also been reduced.
[0011]
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing circuit device for a magnetic disk drive device in which a problem that a circuit element is destroyed due to an abnormality in a power supply voltage is reduced.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a read / write circuit for recording and reproducing signals to and from a magnetic disk, which is a disk-shaped magnetic recording medium, via a magnetic head, and a radial direction of the magnetic disk In a signal processing circuit device for a magnetic disk drive device, comprising: a stepping motor drive circuit that drives a stepping motor that transports the magnetic head; and a control circuit that controls operations of the read / write circuit and the stepping motor drive circuit. An overvoltage detection circuit that outputs an overvoltage detection signal indicating that the power supply voltage to be applied is higher than a predetermined value; and a circuit that receives the overvoltage detection signal and places a predetermined circuit among the circuits in a standby state. In addition, the overvoltage detection circuit corrects the predetermined value so as not to change due to a temperature change. It and a portion having a portion with negative temperature characteristic having a temperature characteristic, and the predetermined value is selected higher than the maximum rated value of the predetermined circuit.
[0013]
With this configuration, in a state where a power supply voltage higher than a predetermined value is applied, the predetermined circuit does not conduct, so if the predetermined value is appropriately set, an abnormally high power supply voltage is applied. It is possible to prevent a situation in which a circuit element of a predetermined circuit is destroyed due to conduction and a large current flowing.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an FDD apparatus according to an embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part as the FDD apparatus shown as a prior art, and description is abbreviate | omitted. Reference numeral 12 denotes an overvoltage detection circuit. The interface drive circuit 1, the control circuit 2, the read / write circuit 3, the stepping motor drive circuit 4 and the overvoltage detection circuit 12 are combined into one integrated circuit device (hereinafter referred to as "FDD device use"). "Signal processing circuit device").
[0015]
The overvoltage detection circuit 12 outputs an overvoltage detection signal to the control circuit 2 when the power supply voltage applied to the signal processing circuit device 50 for the FDD device becomes higher than a predetermined value (hereinafter referred to as “overvoltage threshold”). . While the overvoltage detection signal is output from the overvoltage detection circuit 12, the control circuit 2 sets the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 in a standby state.
[0016]
In the signal processing circuit device 50 for the FDD device of the present embodiment, the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 have a normal value (recommended value) of about 5 [V In contrast, the control circuit 2 has a normal power supply voltage specification of 3 [V]. In order to use a single power supply, the control circuit 2 is not shown in the figure. A power supply voltage is applied via a regulator. In other words, even if the control circuit 2 operates in a state where a power supply voltage higher than a normal value is applied to the signal processing circuit device 50 for the FDD device, the circuit elements are not destroyed. Yes.
[0017]
The maximum rated value of the power supply voltage of the overvoltage detection circuit 12 is sufficiently higher than the maximum rated value of the power supply voltage of the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4.
[0018]
With the above configuration, the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 do not conduct in a state where a power supply voltage higher than the overvoltage threshold is applied, so the overvoltage threshold is set appropriately. If this is done, the circuit elements of the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 are destroyed by conducting a large current when an abnormally high power supply voltage is applied. Therefore, the problem that the circuit element is destroyed due to the abnormality of the power supply voltage can be reduced.
[0019]
Along with this, there are almost no defective products in the manufacturing process due to human error (such as incorrect insertion of a power connector), so the yield is improved and circuit device replacement work to relieve defective products is also required. Reduces productivity.
[0020]
In the FDD device of the present embodiment, when the applied power supply voltage is equal to or lower than the overvoltage threshold, the overvoltage detection circuit 12 cancels the output of the overvoltage detection signal. The interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 become operational again. Therefore, in order to resume the operation after applying a power supply voltage higher than the overvoltage threshold value to enter a standby state, it is only necessary to apply a normal power supply voltage, and the recovery process is simple.
[0021]
One configuration example of the overvoltage detection circuit 12 is shown in FIG. In the same figure, R11, R12, R2, R31, R32, R33, R5B, and R5C are resistors, Q11, Q12, and Q2 are PNP type bipolar transistors, Q31, Q32, Q33, Q41, Q42, Q43, Q44, Q45, and Q5 are NPN bipolar transistors, C1 and C2 are capacitors, and INV is an inverter circuit.
[0022]
A power supply voltage V _CC applied to the signal processing circuit device 50 for the FDD device is applied to one end of the resistor R2. The other end of the resistor R2 is connected to the emitter of the transistor Q1 through the resistor R11, the emitter of the transistor Q12 through the resistor R12, and the emitter of the transistor Q2. The bases of the transistors Q11, Q12, and Q2 are connected to the collector of the transistor Q2. The collectors of the transistors Q11 and Q12 are connected to the collector of the transistor Q31.
[0023]
The emitter of the transistor Q31 is grounded via the resistor R31, the emitter of the transistor Q32 is grounded via the resistor R32, and the emitter of the transistor Q33 is grounded via the resistor R33. The bases of the transistors Q31, Q32, and Q33 are connected to the collector of the transistor Q31. The collectors of the transistors Q32 and Q33 are connected in common. The transistors Q41, Q42, Q43, Q44, and Q45 are diode-connected, and are connected in series between the collector of the transistor Q2 and the collectors of the transistors Q32 and Q33 in series.
[0024]
The collectors of the transistors Q32 and Q33 are connected to the base of the transistor Q5 via the resistor R5B, and are connected to one end of the capacitor C1. The base of the transistor Q5 is connected to one end of the capacitor C2. The other ends of the capacitors C1 and C2 are grounded, and are used to prevent an oscillating operation.
[0025]
The emitter of transistor Q5 is grounded. The power supply voltage V _CC applied to the signal processing circuit device 50 for the FDD device is applied to the collector of the transistor Q5 via the resistor R5C. The input side of the inverter INV is connected to the collector of the transistor Q5. The output of the inverter INV is output from the terminal T _OUT .
[0026]
Assuming that the resistors R31, R32, and R33 have the same resistance value with the above configuration, the relationship between the current I ₁ that flows through the collector of the transistor Q31 and the sum I _{2 of the} current that flows through the collectors of the transistors Q32 and Q33 Is
2 · I ₁ = I ₂ (Formula 1)
It becomes.
[0027]
Next, the base of the transistor Q11 and Q12 - emitter voltage V _BE1, the base of the transistor Q2 - voltage V _BE2 between emitter
V _BE1 = (kT / q) · ln {I ₁ / (2 · I _S )} (Formula 2)
V _BE2 = (kT / q) · ln (I ₂ / I _S ) (Formula 3)
(Where I _S is the saturation current of the transistor, q is the charge amount of electrons, k is the Boltzmann constant, and T is the absolute temperature).
[0028]
Further, the resistance values of the resistors R11 and R12 When R _1,
I ₁ = 2 · (V _BE2 −V _BE1 ) / R ₁
Therefore, using the above (Formula 2) and (Formula 3),
I ₁ = 2 · (1 / R ₁ ) · (kT / q) · ln 4 (Formula 4)
It becomes.
[0029]
Accordingly, the resistance value R ₂ of the resistor R2, transistor Q2, Q41, Q42, Q43, Q44, Q45, and the base of Q5 - When a forward voltage between the emitter and V _F, condition the transistor Q5 is turned ON, The power supply voltage V _CC applied to the signal processing circuit device 50 for the FDD device is:
V _CC > (I ₁ + I ₂ ) · R ₂ + 7V _F
From (Equation 1) and (Equation 4),
V _CC > 6 · (R ₂ / R ₁ ) · (kT / q) · ln 4 + 7V _F (Formula 5)
It becomes.
[0030]
With the above configuration, in the overvoltage detection circuit, the specific values of each element are R ₁ = 4 [kΩ], R ₂ = 68 [kΩ], and the resistance values of the resistors R31, R32, and R33 are 1 [kΩ]. When the resistance values of the resistors R5B and R5C are 50 [kΩ], the capacitance values of the capacitors C1 and C2 are 5 [pF], kT / q = 26 [mV], and V _F = 0.7 [V], When a power supply voltage of 8.6 [V] or higher is applied, the transistor Q5 is turned on, and the voltage at the collector of the transistor Q5 drops to almost the ground level, so that a high level voltage is output from the inverter INV. That is, in this overvoltage detection circuit, a high level voltage becomes an overvoltage detection signal.
[0031]
Note that the number of diode-connected transistors is five. Regarding the right side of (Equation 5), the first term indicates a positive temperature characteristic and the second term indicates a negative temperature characteristic. Therefore, it is determined so that the fluctuation of each term accompanying the temperature change cancels each other.
[0032]
Further, in the signal processing circuit device 50 for the FDD device of the present embodiment, the maximum rated value of the power supply voltage of the interface drive circuit 1, the read / write circuit 3, and the stepping motor drive circuit 4 is about 7 [V]. Yes. On the other hand, the overvoltage threshold by the overvoltage detection circuit is 8.6 [mV]. Ideally, the overvoltage threshold is set to the maximum rated value. The reason why the overvoltage threshold is set to a value higher than the maximum rated value is as follows.
[0033]
If the threshold value of the overvoltage is set to the maximum rated value of the power supply voltage, the overvoltage detection signal is generated even when a normal power supply voltage is applied due to variations in the forward voltage between the base and emitter of the transistor. This is because there is a possibility of being output and falling into a standby state.
[0034]
In the signal processing circuit device of the FDD device of the above embodiment, the control circuit sets each circuit in a standby state based on the overvoltage detection signal output from the overvoltage detection circuit. Each circuit including the control circuit may be in a standby state. By doing so, it is possible to cope with the case where the power supply voltage is not applied to the control circuit via the regulator as in the above embodiment.
[0035]
Further, the spindle motor drive circuit 5 may be put into a standby state by an overvoltage detection signal. The same applies when the spindle motor drive circuit 5 is built in the signal processing circuit device 50 for the FDD device.
[0036]
Further, in the signal processing circuit device of the FDD device of the above embodiment, each circuit is set in a standby state when the power supply voltage becomes too high, but in addition to this, the power supply voltage becomes too low. Even in such a case, if each circuit is set in a standby state, unstable operation may not be obtained. Further, although the present invention has been described by taking the FDD device as an example, the present invention is not limited to the FDD device, and may be another magnetic disk drive device such as an HDD device.
[0037]
【The invention's effect】
As described above, according to the signal processing circuit device for a magnetic disk drive device of the present invention, each circuit does not conduct when a power supply voltage higher than the overvoltage threshold is applied. If it is set, it is possible to prevent a situation in which elements of each circuit are destroyed due to a large current flowing through each circuit when an abnormally high power supply voltage is applied. It is possible to reduce the problem that the circuit element is destroyed due to the abnormality of the power supply voltage.
[0038]
Along with this, since there are almost no defective products in the manufacturing process due to human error (such as incorrect insertion of a power connector), the yield is improved and circuit device replacement work to relieve the defective products is performed. Reduces productivity.
[Brief description of the drawings]
FIG. 1 is a block diagram of an FDD apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of an overvoltage detection circuit.
FIG. 3 is a block diagram of a conventional FDD device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Interface drive circuit 2 Control circuit 3 Read / write circuit 4 Stepping motor drive circuit 5 Spindle motor drive circuit 6 Read / write head 7 Erase head 8 Stepping motor 9 Spindle motor 10 Index sensor 11 Track sensor 12 Overvoltage detection circuit 50 One execution of this invention Signal processing circuit device 60 for FDD device which is a form Signal processing circuit device 100 for FDD device of conventional example Host device R11 Resistor R12 Resistor R2 Resistor R31 Resistor R32 Resistor R33 Resistor R5B Resistor R5C Resistor Q11 PNP type bipolar transistor Q12 PNP Type bipolar transistor Q2 PNP type bipolar transistor Q31 NPN type bipolar transistor Q32 NPN type bipolar transistor Q33 NPN type bipolar transistor Q41 NPN type bipolar transistor Q42 NPN type bipolar transistor Q43 NPN type bipolar transistor Q44 NPN type bipolar transistor Q45 NPN type bipolar transistor Q5 NPN type bipolar transistor C1, C2 Capacitor INV Inverter circuit

Claims (3)

A read / write circuit that records and reproduces signals to and from a magnetic disk, which is a disk-shaped magnetic recording medium, and a stepping motor that drives a stepping motor that moves the magnetic head in the radial direction of the magnetic disk In a signal processing circuit device for a magnetic disk drive device having a drive circuit and a control circuit for controlling operations of the read / write circuit and the stepping motor drive circuit,
An overvoltage detection circuit that outputs an overvoltage detection signal indicating that the applied power supply voltage is higher than a predetermined value, and a circuit that receives the overvoltage detection signal and places a predetermined circuit among the circuits in a standby state are provided. together and, to have a portion having a portion and a negative temperature characteristic with a positive temperature characteristic such that the overvoltage detection circuit does not produce a variation of the predetermined value due to the temperature change, and the predetermined value is the A signal processing circuit device characterized by being selected to be higher than a maximum rated value of a predetermined circuit . A magnetic head, a spindle motor that rotates a magnetic disk that is a disk-shaped magnetic recording medium, a stepping motor that moves the magnetic head in the radial direction of the magnetic disk, and a spindle motor drive circuit that drives the spindle motor; A stepping motor drive circuit for driving the stepping motor, a read / write circuit for recording and reproducing signals to and from the magnetic disk via the magnetic head, the spindle motor drive circuit, the stepping motor drive circuit, and a control circuit for controlling the operation of the read-write circuit, the signal processing circuit unit in the magnetic disk drive system including an interface drive circuit is an interface with an external device, a power supply voltage applied than a predetermined value An overvoltage detection circuit for outputting an overvoltage detection signal indicating that no, together with a circuit for the standby state a predetermined circuit of said circuit receives the overvoltage detection signal is provided, said overvoltage detection circuit is temperature A portion having a positive temperature characteristic and a portion having a negative temperature characteristic so as not to cause a change in the predetermined value due to a change, and the predetermined value is higher than a maximum rated value of the predetermined circuit. A signal processing circuit device characterized by being selected. The overvoltage detection circuit is
A first resistor to which a power supply voltage is applied at one end;
A PNP-type first transistor having an emitter connected to the other end of the first resistor;
A PNP type second transistor having an emitter connected to the other end of the first resistor via a second resistor;
A PNP type third transistor having an emitter connected to the other end of the first resistor via a third resistor;
An NPN-type fourth transistor having a base and a collector connected to each collector of the second and third transistors;
An NPN-type fifth transistor whose base is connected to the base of the fourth transistor;
An NPN-type sixth transistor whose base is connected to the base of the fifth transistor;
Third, fourth, and fifth resistors connected between the emitters of the fourth, fifth, and sixth transistors and the ground;
A transistor array circuit having one end connected to each base of the first, second, and third transistors and the collector of the first transistor, and the other end connected to the collectors of the PNP-type fifth and sixth transistors. And a transistor array composed of a plurality of diode-connected transistors connected in series,
A first capacitor for preventing oscillation connected between the collector of the sixth transistor and the ground;
A sixth resistor having one end connected to the collector of the sixth transistor and the other end connected to the base of an NPN-type seventh transistor;
A second capacitor for preventing oscillation connected between the base of the seventh transistor and the ground;
A seventh resistor connected between the collector of the seventh transistor whose emitter is connected to the ground and the power supply voltage;
An inverter that outputs an overvoltage detection signal based on the collector voltage of the seventh transistor;
The signal processing circuit device according to claim 1 or 2, characterized by comprising:

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