JP3799147B2 - Fully differential sample / hold comparison circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fully differential configuration sample / hold comparison circuit, and more particularly to a fully differential configuration sample / hold comparison circuit that is stronger against digital noise and charge injection associated with opening / closing of a switch.
[0002]
[Prior art]
Conventionally, an A / D (analog / digital) converter (ADC) based on CMOS technology has been developed for the purpose of integration in a digital signal processing LSI. This type of ADC is required to be resistant to power supply noise and digital noise. Similarly, a comparator that is a key circuit of this ADC circuit is also required to have noise resistance.
[0003]
A comparator with a differential configuration is available as a comparator for improving the noise resistance. However, this configuration has a problem that an offset due to variations in MOS transistors increases, and this may be reduced in terms of LSI performance. Required. In consideration of integration, since a serial-parallel type is mainly used for the A / D conversion method, it is desired to have an S / H (sample / hold) function.
[0004]
As a comparator satisfying such a requirement, for example, there is a circuit disclosed in pp 17 to 24 of ICD (Integrated Circuit and Device) 89-114 which is a research report (integrated circuit) published by the Institute of Electronics, Information and Communication Engineers in 1989. In this circuit, a differential amplifier having an offset cancel function is provided in the input stage to reduce an input conversion offset and to be a comparator having an S / H function in consideration of incorporation in an ADC. This circuit configuration is shown in FIG.
[0005]
Referring to FIG. 3, a differential amplifier 4 is provided in the input stage, and an analog input signal Vin is supplied to a positive phase input among the differential inputs of the differential amplifier 4 via a switch SW1. The reference voltage Vref is supplied to the negative phase input. A switch SW 2 is provided between the differential inputs of the differential amplifier 4.
[0006]
The differential output of the differential amplifier 4 is introduced into the S / H circuit 2. The S / H circuit 2 is inserted between the differential output lines in series and switches SW3a and SW3b for turning on and off the differential outputs, and between the outputs of the switches SW3a and SW3b and the reference potential point VB1. Hold capacitors C1 and C2 are connected to hold these differential outputs.
[0007]
Further, the pair of hold outputs are differential inputs of the comparator 3 through capacitors C3 and C4 for removing the offset of the differential amplifier 4, respectively. The capacitors C3 and C4 are connected to the reference potential point VB2 via switches SW4a and SW4b, respectively.
[0008]
In such a configuration, the operation thereof will be described below. Here, the switches SW3a and SW3b and the switches SW4a and SW4b are described as SW3 and SW4 in the following description in order to perform the same operation.
[0009]
There is an auto-zero operation as a stage before the sampling operation. That is, the switch SW2, SW3, SW4 is turned on and the offset of the differential amplifier 4 is stored in the capacitors C3, C4. This is called auto-zero operation, and therefore the capacitors C3, C4 have auto-zero capacitance. Called.
[0010]
Thereafter, the switches SW2 and SW4 are turned off and at the same time the switch SW1 is turned on, and the analog input signal Vin is sampled. At this time, voltages at the time of auto-zero operation are stored in the capacitors C3 and C4, and thereby the offset of the differential amplifier 4 is cancelled.
[0011]
Thereafter, the switch SW3 is turned off, and the capacitors C1 and C2 hold the output voltage of the differential amplifier 4, that is, the difference voltage from the reference voltage Vref which is information of the input voltage Vin at that time. The differential comparator 3 at the next stage amplifies the difference voltage between the input voltage Vin and the reference voltage Vref by the differential amplifier 4 at the input stage, whereby the S / H circuit 2 and the differential comparator 3 All the offset voltages are reduced to 1 / gain of the differential amplifier 4 in terms of input. Further, the offset of the differential amplifier 4 is canceled by the switches SW1 to SW4 and the capacitors C3 and C4.
[0012]
[Problems to be solved by the invention]
Since this type of conventional fully differential S / H comparison circuit is configured to compare one reference voltage and one input voltage, noise generated from the digital circuit section and charge accompanying switching of the switch There is a problem that a comparison error is likely to occur due to injection or the like.
[0013]
An object of the present invention is to provide a fully differential S / H comparison circuit that reduces comparison errors as a stronger configuration against digital noise and charge injection associated with opening and closing of a switch.
[0014]
[Means for Solving the Problems]
According to the present invention, a differential amplifier for amplifying an input signal, sample / hold means for sampling / holding the differential output of the differential amplifier, and a pair of outputs of the sample / hold means as differential inputs. A fully differential configuration sample / hold comparison circuit including a differential comparator,
The differential amplifier includes a first differential amplifying unit having a positive phase input signal and a positive phase reference voltage as a pair of differential inputs, and a negative phase input signal and a negative phase reference voltage as a pair of differential inputs. Second differential amplification means to
The positive phase input signal and the negative phase input signal are respectively input via a first switch,
The pair of differential inputs of the first differential amplifying means and the pair of differential inputs of the second differential amplifying means are each short-circuited via a second switch,
The first switch to which the positive phase input signal is input and the first switch to which the negative phase input signal is input perform the same operation.
The second switch of the first differential amplifying means and the second switch of the second differential amplifying means perform the same operation,
The differential outputs of the first and second differential amplifying means are commonly connected to each other to be a pair of differential outputs that are led to the sample / hold means,
The sample / hold means includes a third switch inserted in series between the differential amplifier and the differential comparator to turn on and off a differential output of the differential amplifier, and each of the third switches. A fully differential sample / hold comparison circuit having a hold capacitor connected between the output and the reference potential point is obtained.
[0015]
The first differential amplifying means includes a first differential transistor having a source connected in common to each other, the gate supplied with the positive phase input signal, and a gate supplied with the positive phase reference voltage. The second differential amplifying means includes a third differential transistor whose source is commonly connected to each other, the negative phase input signal supplied to the gate, and the negative phase reference voltage to the gate. And the drains of the first and fourth differential transistors are commonly connected, and the drains of the second and third differential transistors are commonly connected. It is characterized by. Further, according to the present invention, during the sampling operation, the first switch to which the positive phase input signal is input and the first switch to which the negative phase input signal is input are simultaneously turned on, and the first switch The second switch of the differential amplifying means and the second switch of the second differential amplifying means are simultaneously turned off, and the third switch is turned off during the hold operation.
[0017]
The operation of the present invention will be described. A circuit that is resistant to common-mode noise from digital circuits, etc., by adopting a differential amplifier of the input stage that has two pairs of differential inputs that receive a pair of positive and negative phase input signals and a pair of positive and negative phase reference voltages. It becomes. In addition, by supplying the positive and negative phase input signals to the differential amplifier at the same time during the sample operation, and controlling the switch so as to be disconnected from the differential amplifier at the same time during the hold operation, it is possible to charge injection caused by the on / off operation of the switch. Strong characteristics can be obtained.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same parts as those in FIG. 3 are denoted by the same reference numerals. Referring to FIG. 1, a differential amplifier 4 in an input stage includes a pair of positive and negative phase inputs Vin and inverted Vin (shown by the upper bar), and a pair of positive and negative phase reference voltages Vref and inverted Vref (shown by the upper bar). Are input.
[0020]
A pair of positive and negative phase inputs Vin and inverted Vin are input to the differential amplifier 4 through the switches SW1b and SW1a, respectively, and a pair of positive and negative phase reference voltages Vref and inverted Vref are directly input to the differential amplifier 4. The positive phase input signal Vin and the positive phase reference voltage Vref are a first pair of differential inputs, and the negative phase input signal Vin bar and the negative phase reference voltage Vref bar are a second pair of differential inputs. It has become.
[0021]
The switch SW2a is connected to turn on and off the short circuit between the first pair of differential inputs (Vin and Verf), and the switch SW2b is connected to the second pair of differential inputs (Vin bar). And Verf bar) are connected to turn on and off.
[0022]
The first and second pair of differential inputs are differentially amplified in the differential amplifier 4 and the differential outputs are connected in common to form a pair of differential outputs. / H circuit 2 is supplied. The configuration after this S / H circuit 2 is the same as that of the conventional example of FIG. 3, and the description thereof is omitted.
[0023]
FIG. 2 is an overall circuit diagram showing a specific example of the differential amplifier 4 of FIG. 1, and parts equivalent to those in FIG. Referring to FIG. 2 , in the differential amplifier 4, the positive phase input signal Vin and the positive phase reference voltage Vref via the switch SW1b are supplied to the gates, respectively, and the sources are connected in common to each other. has an N-channel MOS transistors N1, N4 that is, the first differential by the constant current source I 2 and the transistor N1, N4 provided between the source common connecting point and a reference potential point (ground) An amplification unit is configured.
[0024]
Further, the negative-phase input signal Vin bar and the negative-phase reference voltage Vref bar via the switch SW1a are respectively supplied to the gates, and the sources are connected in common and the N-channel MOS transistors N3 and N2 are connected in a differential manner. a second differential amplifier by a constant current source I 1 and the transistor N2, N3 provided between the source common connecting point and a reference potential point (ground) is constructed.
[0025]
The differential outputs of the first and second differential amplifiers are derived by P-channel MOS transistors P1 and P2 that are common active loads and input to the S / H circuit 2. The subsequent steps are the same as the conventional example of FIG.
[0026]
The switches SW1a and SW1b perform an on / off operation at the same time, and the switches SW2a and SW2b perform an on / off operation at the same time, and have the same functions as the switches SW1 and SW2 of the conventional circuit of FIG.
[0027]
Since the differential amplifier 4 in the input stage has a pair of differential inputs Vin and Vin bars and a pair of reference voltages Vref and Vref bars, it has a strong characteristic against noise from the digital circuit. Further, since the switches SW1a and SW1b between the input and the reference voltage perform the same operation, and the switches SW2a and SW2b perform the same operation, the influence of the charge injection due to the on / off of the switch is very small.
[0028]
The differential amplifier 4 having the circuit configuration shown in FIG. 2 has the same gain as the difference between the reference voltage and the differential voltage of the input in the single-ended configuration. In addition, since the signal path from the input to the output including the switch is the same for both signal paths, the differential signal is balanced, and the structure is strong against in-phase noise.
[0029]
An example of the relationship between the pair of differential input signals Vin and Vin bar and the pair of reference voltages VREF and VREF bar is shown in FIG. In FIG. 4, the input signal is a sine wave. Assume that the negative phase signal Vin bar with respect to the positive phase signal Vin is as shown in FIG. 4A, and that the reference voltage VREF corresponding to the positive phase signal Vin is as shown in FIG. The reference voltage VREF bar corresponding to the Vin bar is as shown in FIG.
[0030]
That is, a pair of reference potential manifold pressures is the voltage of a symmetrical relationship with each other with respect to the center voltage. Each difference voltage in this case is indicated by ΔV in the time of the maximum value of the input signal Vin, and the absolute values of both ΔV are equal to each other, and this relationship is the same at any time. Is obvious.
[0031]
【The invention's effect】
As described above, according to the present invention, the digital circuit includes the differential amplifier having the pair of differential inputs and the pair of reference voltages, the S / H circuit, and the differential comparator. Therefore, there is an effect that an accurate comparison result with less comparison error can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific example of FIG. 1;
FIG. 3 is a diagram showing an example of a conventional fully differential S / H comparison circuit;
FIG. 4 is a diagram illustrating an example of a relationship between a pair of differential inputs and a pair of reference voltages.
[Explanation of symbols]
2 S / H circuit 3 Differential comparator 4 Differential amplifier C1, C2 Hold capacitors C3, C4 Auto-zero capacitors SW1-SW4 switches

Claims (3)

A differential amplifier for amplifying an input signal; sample / hold means for sampling / holding the differential output of the differential amplifier; and a differential comparator having a pair of outputs of the sample / hold means as differential inputs A fully differential configuration sample / hold comparison circuit including:
The differential amplifier includes a first differential amplifying unit having a positive phase input signal and a positive phase reference voltage as a pair of differential inputs, and a negative phase input signal and a negative phase reference voltage as a pair of differential inputs. Second differential amplification means to
The positive phase input signal and the negative phase input signal are respectively input via a first switch,
The pair of differential inputs of the first differential amplification means and the pair of differential inputs of the second differential amplification means are each short-circuited via a second switch,
The first switch to which the normal phase input signal is input and the first switch to which the negative phase input signal is input perform the same operation,
The second switch of the first differential amplifying means and the second switch of the second differential amplifying means perform the same operation,
The differential outputs of the first and second differential amplifying means are commonly connected to each other to be a pair of differential outputs that are led to the sample / hold means,
The sample / hold means includes a third switch inserted in series between the differential amplifier and the differential comparator to turn on and off a differential output of the differential amplifier, and each of the third switches. A fully differential sample / hold comparison circuit comprising a hold capacitor connected between the output and a reference potential point. The first differential amplifying means includes a first differential transistor having a source connected in common to each other, the gate supplied with the positive phase input signal, and a gate supplied with the positive phase reference voltage. The second differential amplifier means has a common source connected to each other, the third differential transistor having the negative phase input signal supplied to the gate, and the negative phase reference voltage to the gate; And the drains of the first and fourth differential transistors are commonly connected, and the drains of the second and third differential transistors are commonly connected. The fully differential sample / hold comparison circuit according to claim 1. Full differential configuration sample according to claim 1 or claim 2. / A hold comparison circuit,
During the sample operation, the first switch to which the positive phase input signal is input and the first switch to which the negative phase input signal is input are simultaneously turned on, and the pair of the first differential amplification means Simultaneously turning off the second switch between the differential inputs and the second switch between the pair of differential inputs of the second differential amplifying means;
Fully differential configuration sample characterized by turning off the third switch during hold operation / Hold comparison circuit.

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