JP3800522B2 - Video signal processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing apparatus that expands or reduces a video signal, and more particularly, to a video signal processing apparatus that has a small circuit scale and can be easily switched between expansion and reduction.
[0002]
[Prior art]
2. Description of the Related Art In recent years, television receivers and display devices that display video signals such as television signals and personal computer signals have widespread display screens with an aspect ratio of 16: 9. An image display device having a horizontally long display screen must have an aspect conversion function such as converting an image having an aspect ratio of 4: 3 into an image having an aspect ratio of 16: 9. In order to realize the aspect conversion function, a video signal processing device for enlarging and reducing the video image is necessary, and its importance is increasing.
[0003]
FIG. 17 is a block diagram showing a general reduction device. Reduction of the video signal is realized by generating interpolation data using input data necessary for reduction (interpolation), selectively writing the data to the memory, and continuously reading the written data. . In FIG. 17, input data is input to the interpolation filter 1. The coefficient generator 2 supplies an interpolation coefficient to the interpolation filter 1 according to the input phase data. The interpolation filter 1 generates interpolation data using input data and an interpolation coefficient.
[0004]
As an interpolation method in the interpolation filter 1, when two-point linear interpolation is performed, the input current data is Dn, the previous data delayed by one clock is Dn-1, the interpolation coefficient is k, and as an example, the following (1) Interpolation data Dn ′ is generated by the equation.
Dn ′ = Dn × (k / 32) + Dn−1 × ((32−k) / 32) (1)
Note that 32 in the equation (1) means that two points of input data are divided into 32, and interpolation data is generated at intervals of 1/32 between the two points of the input data.
[0005]
The interpolation data (Dn ′) obtained by the interpolation filter 1 is supplied to the memory 3. Since it is necessary to select and write only necessary data in the memory 3, data is written to the memory 3 while performing data write control by write enable. And the reduced data is output by reading the written data continuously.
[0006]
FIG. 18 is a block diagram showing a general enlargement apparatus. Video signal expansion is performed by sequentially writing input data into the memory, reading out the written data from the memory, reading out the data necessary for expansion (interpolation) from the memory, and holding the readout as necessary to store the interpolation data. This is realized by generating and continuously outputting the interpolation data.
[0007]
In FIG. 18, input data is sequentially written in the memory 4. By performing the data read control by the read enable, the written data is read while holding the read corresponding to the interpolation phase. The coefficient generator 6 supplies an interpolation coefficient to the interpolation filter 5 according to the input phase data. The interpolation filter 5 generates interpolation data using the input data and the interpolation coefficient.
[0008]
In the case of an enlargement / reduction apparatus, the reduction apparatus shown in FIG. 17 and the enlargement apparatus shown in FIG. 18 are combined. In this case, the memory 3 and the memory 4 can be shared.
[0009]
[Problems to be solved by the invention]
As one aspect conversion for converting an image with an aspect ratio of 4: 3 into an image with an aspect ratio of 16: 9, the image is set to a substantially constant display size at the horizontal center of the screen, and the image is There is a non-linear mode that gradually expands as it approaches the part (see Japanese Patent No. 2759727). In this mode, it is necessary to reduce the image at the center in the horizontal direction and to enlarge the image at the left and right portions, and reduction and enlargement are mixed in one screen.
[0010]
When the above-described non-linear mode is implemented using the conventional enlargement / reduction apparatus in which the reduction apparatus shown in FIG. 17 and the enlargement apparatus shown in FIG. 18 are combined, the following problems occur.
(1) The circuit scale is large, and the interpolation by the reduction device and the interpolation by the enlargement device must be switched.
(2) When switching between the interpolation by the reduction device and the interpolation by the enlargement device, the control becomes very complicated at the boundary between reduction and enlargement.
(3) Since the generation of the interpolation (reduction) data by the reduction device depends on the time of the input data, and the generation of the interpolation (enlargement) data by the enlargement device depends on the generation time of the interpolation data, the reduction device and the enlargement device are Time alignment when combined is difficult.
[0011]
The present invention has been made in view of such problems, and has a small circuit scale, can cope with both enlargement and reduction of an image, and can easily switch between enlargement and reduction. The purpose is to provide.
[0012]
[Means for Solving the Problems]
The present invention provides the following configuration in order to solve the problems of the conventional technology described above.
(A) One pixel data or one line data constituting a video signal is set as one unit of data, and output data is generated by expanding or reducing the input data in which the one unit of data is sequentially input in time series. In the video signal processing apparatus to Each has multiple addresses to write data First to Nth N (N is an integer of 2 or more) memories (10 to 13, 20 to 27) and the first to Nth memories for each unit of the input data Each address Write control means (15, 150) for controlling to sequentially write to the memory, and data for determining which of the first to Nth memories to start reading data from, A start memory determination data that is set in accordance with the enlargement / reduction ratio and changes as the timing of generating data of each unit of the output data progresses, and an address for reading the data in the memory that starts the reading Address determination data that is set in accordance with the enlargement / reduction ratio and changes as the timing of generating data for each unit of the output data, and from the first to Nth memories, Control to read N units of continuous data in time series from 1 unit of data read from memory that starts reading Read control means (16, 160) and data indicating in what phase each unit of output data is generated with respect to each unit of input data, depending on the enlargement / reduction ratio Coefficient generating means (17, 170) for generating N interpolation coefficients in accordance with the phase data set in accordance with the progress of the timing for generating the unit data of each of the output data, and the start memory The interpolation coefficient rearranging means for rearranging the N interpolation coefficients according to the determined data, and the N unit data read from the first to Nth memories and the interpolation coefficient rearranging means. And an N-tap interpolation filter (14, 140) for generating the output data using the N interpolation coefficients obtained. Signal processor.
(B) Serial data in which pixel data or line data constituting M types of video signals (M is an integer of 2 or more) is sequentially input in time series is input as input data, and the input data is expanded by interpolation. Alternatively, in a video signal processing apparatus that generates output data by reducing, Each has multiple addresses to write data First to Nth N (N is an integer of 2 or more) memories (10 to 13) and one pixel data or one line data in the input data as one unit of data, the M types of video The first to Nth memories for each M units of data sets Each address Write control means (15) for controlling to sequentially write to the memory, and data for deciding which of the first to Nth memories to start reading data from The start memory determination data that is set according to the rate and changes with the progress of the timing of generating the data of each unit of the output data, and data for determining the address for reading the data in the memory that starts the reading Yes, using the address determination data set according to the enlargement / reduction ratio and changing with the progress of the timing of generating the data of each unit of the output data, and reading out from the first to Nth memories N readings for reading N units of data that are continuous in time series from 1 unit of data read from the starting memory The address selection control unit (16) that generates an address and the N units based on a predetermined first conversion condition so that the M unit data is interpolated with the same interpolation phase. An address conversion unit (36) for converting the read addresses and supplying the read data to the first to Nth memories, and what kind of data each unit of the output data is relative to each unit of the input data This is data indicating whether to generate in the phase, and is set according to the enlargement / reduction ratio, and N interpolation coefficients are set according to the phase data that changes with the progress of the timing for generating the data of each unit of the output data A coefficient generation unit (17) for generating N, an interpolation coefficient rearrangement unit (18) for rearranging the N interpolation coefficients in accordance with the start memory determination data, and the M units of data. On the other hand, a coefficient conversion unit (38) that converts the N interpolation coefficients based on a predetermined second conversion condition so that the interpolation calculation is performed with the same coefficients, and the first to first An N-tap interpolation filter (14) for generating the output data using the N units of data read from the N memories and the N interpolation coefficients converted by the coefficient conversion unit. A video signal processing apparatus characterized by comprising.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The video signal processing apparatus of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of a video signal processing apparatus of the present invention, FIG. 2 is a diagram for explaining a data write operation to the memories 10 to 13 in FIG. 1, and FIG. 4 is a diagram showing an example of the relationship between data pixels and output data pixels, FIG. 4 is a diagram for explaining a data read operation from the memories 10 to 13 in FIG. 1, and FIG. 5 is an interpolation filter in FIG. FIG. 6 is a diagram illustrating an example of a table of interpolation coefficients, FIG. 7 is a block diagram illustrating a specific configuration example of the interpolation filter 14 in FIG. 1, and FIG. FIG. 9 is a diagram for explaining an operation of generating interpolation data in the interpolation filter 14 in FIG. 1, FIG. 9 is a block diagram showing a second embodiment of the video signal processing apparatus of the present invention, and FIG. 10 is a video signal processing apparatus of the present invention. The block showing the third embodiment of 11 is a diagram for explaining a data write operation to the memories 10 to 13 in FIG. 10, and FIG. 12 is a diagram for explaining a data read operation from the memories 10 to 13 in FIG. 13 is a diagram for explaining an operation of supplying an interpolation coefficient to the interpolation filter 14 in FIG. 10, FIG. 14 is a diagram for explaining an operation of generating interpolation data in the interpolation filter 14 in FIG. 10, and FIG. FIG. 16 is a block diagram illustrating a specific configuration example of the coefficient conversion unit 38 in FIG. 10.
[0014]
<First Embodiment>
First, the configuration of the first embodiment shown in FIG. 1 will be described. In FIG. 1, input data of a video signal to be enlarged or reduced is input to the memories 10 to 13. The memories 10 to 13 are random access memories (RAM). With the configuration shown in FIG. 1, when the video signal is scaled in the horizontal direction, the memories 10 to 13 need only store data of a plurality of pixels as input data. With the configuration shown in FIG. 1, when the video signal is enlarged or reduced in the vertical direction, the memories 10 to 13 need only store a plurality of lines of data as input data. If the configuration of FIG. 1 performs only enlargement processing, it may not be RAM but may be FIFO memory.
[0015]
The input data is one pixel data or one line data constituting a video signal as one unit of data, and the one unit of data is sequentially input in time series to form a plurality of units of data. In the following description, a horizontal enlargement / reduction process (mainly a reduction process), that is, a case where one unit of data is one pixel data will be described.
[0016]
How the input data is written to the memories 10 to 13 is controlled by the data write control unit 15 (write control means). How the data written in the memories 10 to 13 is read from the memories 10 to 13 is controlled by the address selection control unit 16 (reading control means). Data output from the memories 10 to 13 is input to the interpolation filter 14. In the embodiment shown in FIG. 1, the interpolation filter 14 is a 4-tap filter.
[0017]
The coefficient generator 17 generates an interpolation coefficient necessary for enlargement or reduction interpolation in the interpolation filter 14. The coefficient generation unit 17 may be a table such as a ROM that stores interpolation coefficients, or may generate and output interpolation coefficients by calculation. The coefficient selection control unit 18 controls how the interpolation coefficient output from the coefficient generation unit 17 is supplied to each of the four taps. The interpolation filter 14 generates interpolation data using the data input from the memories 10 to 13 and the interpolation coefficient output from the coefficient generation unit 17 and controlled to be supplied to each tap by the coefficient selection control unit 18. And output.
[0018]
Hereinafter, the specific operation of the video signal processing apparatus shown in FIG. 1 will be described in detail with reference to FIG. 2 and subsequent drawings. 2, (A) shows input data to the memories 10 to 13, and 0, 1, 2, 3,... Are pixel numbers. The data write control unit 15 supplies write enables a to d as shown in FIGS. 2B to 2E to the memories 10 to 13, respectively. When the write enable (a to d) is high, the input data shown in FIG. 2 (A) is written, so that the memories 10 to 13 are respectively shown in FIGS. 2 (F) to (I). Data (write data a to d) is written. For example, pixel data of pixel numbers 0, 4, 8, 12,.
[0019]
That is, the input data shown in FIG. 2 (A) is cyclically sequentially written for each pixel in the memories 10 to 13, and the data of a plurality of pixels constituting the input data is developed into a four-phase data string. Will be.
[0020]
Here, an outline of the reduction process will be described with reference to FIG. In the reduction process shown in FIG. 3, the input data having the data interval “32” shown in FIG. 3A is interpolated to be thinned out, and the output data having the data interval “44” shown in FIG. 3B is generated. The data interval “32” in the input data means that adjacent pixels are divided into 32 and output data is generated at every 1/32 position. The data interval in the output data is determined by the reduction rate. In FIG. 3, for the sake of simplification, the second, third, and fifth pixels from the left in the input data are shown as being the second, third, and fourth pixels from the left in the output data. Actually, output data is generated from four adjacent pixels in the input data.
[0021]
Returning to FIG. 1, the address selection control unit 16 has a plurality of bits of address control data that are set according to the enlargement / reduction ratio and that sequentially change as the timing of generating the pixel data of the output data progresses. Entered. More specifically, in the address selection control unit 16 as start memory determination data for determining which memory in the memories 10 to 13 starts reading data in the lower 2 bits of the address control data of a plurality of bits. The higher bits excluding the lower 2 bits are supplied to the address selection control unit 16 as address determination data for determining the address from which data is read in the memory that starts reading. Of course, a plurality of bits of address control data may be supplied to the address selection control unit 16, and the lower 2 bits and the remaining upper bits may be divided therein.
[0022]
If the multi-bit address control data is, for example, 8 bits, the lower 2 bits are start memory determination data, and the upper 6 bits are address determination data. The reason why the lower 2 bits are used as the start memory determination data is that there are four memories in this embodiment, and there are four types of memories that start reading data. When more memories are provided, a larger number of bits is required as start memory determination data. The number of bits of address determination data depends on the number of pixels of input data.
[0023]
In the address control data, when the input data interval “32” shown in FIG. 3A is set to “1 interval”, each pixel of the output data shown in FIG. It shows how many intervals away from the pixel (the leftmost pixel in FIG. 3).
[0024]
The coefficient generator 17 receives 5-bit phase data. The phase data is data indicating where each pixel of the output data shown in FIG. 3B is located within the input data interval “32”. The phase data is also set according to the enlargement / reduction ratio, and sequentially changes with the progress of the timing for generating the respective pixel data of the output data. The number of bits in the phase data depends on the interpolation interval of the output data. That is, the position of the output data shown in FIG. 3B is how many intervals away from the first pixel of the input data by the address control data, and further, between the two pixels by the phase data indicating the remainder less than one interval. It depends on where you are located.
[0025]
In FIG. 4, (A) shows address control data, and (B) shows phase data. Since the first pixel of the output data shown in FIG. 3B is at the same position as the first pixel of the input data, the address control data for generating the first pixel of the output data is shown in FIG. The phase data is 0 as shown in FIG. 4B. Next, the second pixel of the output data is generated between the second pixel and the third pixel of the input data, the address control data is 1, and the phase data is 12. The fourth pixel of the output data is generated between the fifth pixel and the sixth pixel of the input data. The address control data is 4 and the phase data is 4.
[0026]
Specific numerical values of the address control data and the phase data depend on how the input data is enlarged or reduced to generate the output data. Actually, the address control data shown in FIG. 4A is represented as multi-bit data as described above, and the phase data shown in FIG. 4B is represented as 5-bit data as described above. .
[0027]
FIG. 4C shows address determination data which is higher bits excluding the lower 2 bits of the address control data shown in FIG. 4A. FIG. 4D shows the address control data shown in FIG. Start memory determination data which is the lower 2 bits of the. 4E to 4H show addresses (read addresses a to d) at which data is read from the memories 10 to 13, respectively.
[0028]
First, in order to generate the first pixel of the output data shown in FIG. 3B, since the start memory determination data is 0 as shown in FIG. 4D, the memory from which reading is started is the memory 10 Since the address determination data in the memory 10 is 0 as shown in FIG. 4C, the address for reading data in the memory 10 is 0. Therefore, data is read from address 0 of all the memories 10 to 13 in the order of the memories 10, 11, 12, and 13.
[0029]
Next, in order to generate the second pixel of the output data shown in FIG. 3B, since the start memory determination data is 1 and the address determination data is 0, the memory to start reading is the memory 11, The address for reading data in the memory 11 is 0. Therefore, data is read in the order of the memories 11, 12, 13, and 10. When data at address 0 is read from the memory 11 to the memory 13, the pixel data next to the data at address 0 in the memory 13 is data written at address 1 in the memory 10, as can be seen from FIG. Data is read from 10 address 1. Therefore, the addresses for reading data from the memories 10 to 13 are 1, 0, 0, 0 as shown in FIGS.
[0030]
That is, when reading out the four pixel data from the memories 10 to 13, assuming that the address of the memory to start reading is k, the pattern for reading data from the memories 10 to 13 is (k, k, k, k), (K + 1, k, k, k), (k + 1, k + 1, k, k), or (k + 1, k + 1, k + 1, k). The starting memory decision data will indicate which of these four patterns is selected. Since the addresses for reading data in the memories 10 to 13 are as shown in FIGS. 4E to 4H, the data (read data a to d) read from the memories 10 to 13 are the same as those shown in FIGS. L).
[0031]
Thus, it can be seen that the address selection control unit 16 controls the memory 10 to 13 to read out four pixel data that are continuous in time series from the pixel data read from the memory from which reading has started. By the data read control from the memories 10 to 13 by the address selection control unit 16 described above, the interpolation filter 14 is adjacent to each other necessary for generating the respective output data (interpolation data) shown in FIG. Four pieces of pixel data are input.
[0032]
Next, operations in the coefficient generation unit 17 and the coefficient selection control unit 18 will be described with reference to FIG. FIGS. 5A and 5B show the address control data and phase data shown in FIGS. 4A and 4B, respectively. The coefficient generator 17 holds a set of interpolation coefficients (coefficients a to d) corresponding to each of the 32 types of phase data shown in FIG. Alternatively, the coefficient generator 17 generates a set of interpolation coefficients corresponding to each phase data. The coefficient generator 17 generates a set of interpolation coefficients from the table shown in FIG. 6, as shown in FIGS. 5C to 5F, according to the input phase data shown in FIG. 5B. . The set of interpolation coefficients is input to the coefficient selection control unit 18.
[0033]
The coefficient selection control unit 18 receives start memory determination data that is input to the address selection control unit 16. FIG. 5G shows the start memory determination data shown in FIG. As illustrated in FIG. 7, the interpolation filter 14 multiplies the data (read data a to d) output from the memories 10 to 13 by the multipliers 141 to 144 and the interpolation coefficient generated by the coefficient generator 17, respectively. These outputs are added by an adder 145. As will be described later, the read data a may not be multiplied by the coefficient a, the read data b may be multiplied by the coefficient b, the read data c may be multiplied by the coefficient c, and the read data d may not be multiplied by the coefficient d. Therefore, in FIG. 7, coefficients α to δ are supplied to the multipliers 141 to 144.
[0034]
Coefficients a to d generated by the coefficient generation unit 17 must be multiplied by the coefficients a, b, c, and d in order from the first pixel to the adjacent four pixel data. As described above, there are four types of patterns for reading data from the memories 10 to 13, and how the four pixel data (read data a to d) supplied to the interpolation filter 14 are arranged in time series. It depends on the pattern.
[0035]
More specifically, when the pattern for reading data from the memories 10 to 13 is (k, k, k, k), the pixel data output from the memories 10 to 13 are arranged in time series in order from the first pixel. The memories 10, 11, 12, and 13 are used. When the pattern is (k + 1, k, k, k), in the order of the memories 11, 12, 13, 10, and when the pattern is (k + 1, k + 1, k, k), the memory 12, In the order of 13, 10, 11, and when the pattern is (k + 1, k + 1, k + 1, k), the memory is in the order of memories 13, 10, 11, 12.
[0036]
The coefficient selection control unit 18 is for replacing the coefficients a to d supplied to the multipliers 141 to 144 of the interpolation filter 14 in accordance with these four patterns. The coefficient selection control unit 18 is an interpolation coefficient rearranging unit that rearranges the order of supply of the coefficients a to d to the multipliers 141 to 144. By rearranging the coefficients a to d according to the four patterns, the four adjacent pixel data are multiplied by the coefficients a to d in the order of the coefficients a, b, c, and d in order from the first pixel. be able to.
[0037]
5H to 5K show the coefficients α to δ actually supplied to the multipliers 141 to 144 of the interpolation filter 14. 5 (H) to (K), the coefficients a to d shown in FIGS. 5 (C) to 5 (F) are applied to the pixel data output from the memory that starts reading according to the start memory determination data. It can be seen that the coefficients a to d are shifted so that the coefficient a is multiplied. For example, if the start memory determination data is 0, the coefficient α is the coefficient a, and if the start memory determination data is 1, the coefficient β is the coefficient a.
[0038]
8A to 8D show read pixel data from the memories 10 to 13 shown in FIGS. FIGS. 8E to 8H are coefficients shown in FIGS. 5H to 5K. The interpolation data output from the interpolation filter 14 is shown in FIG. This interpolation data is the output data shown in FIG.
[0039]
With the above configuration, the video signal processing apparatus of the present invention shown in FIG. 1 can reduce the input data. In exactly the same manner, the video signal processing apparatus of the present invention can expand the input data. Whether the video signal processing apparatus of the present invention performs the enlargement process or the reduction process depends on the address control data supplied to the address selection control unit 16. That is, if the address control data is appropriately set, the video signal processing apparatus of the present invention can be both an enlargement apparatus and a reduction apparatus. Since the same control operation is performed for both the enlargement process and the reduction process, even if switching between the enlargement process and the reduction process is performed in the middle of the process, or when the enlargement process and the reduction process are mixed, a conventional problem occurs. There is nothing.
[0040]
Second Embodiment
The video signal processing apparatus of the present invention is not limited to the embodiment shown in FIG. In the embodiment shown in FIG. 1, the interpolation filter 14 has 4 taps, but the second embodiment shown in FIG. 9 shows a configuration in which the interpolation filter has 8 taps. Since the interpolation filter 140 has 8 taps, 8 memories 20 to 27 are provided. In FIG. 9, the data write control unit 150 performs the same operation as the data write control unit 15 in FIG. 1, and the address selection control unit 160 performs the same operation as the address selection control unit 16 in FIG. Since there are 8 memories, the start memory decision data is 3 bits.
[0041]
The coefficient generator 170 operates in the same manner as the coefficient generator 17 in FIG. 1, and the coefficient selection controller 180 operates in the same manner as the coefficient selection controller 18 in FIG. In this embodiment, since the interpolation filter 140 has 8 taps, the coefficient generation unit 170 generates 8 interpolation coefficients, and the coefficient selection control unit 180 arranges the 8 interpolation coefficients according to the start memory determination data. Change.
[0042]
In the first and second embodiments described above, as an example, the luminance signal Y in the image data (4: 2: 2 format) composed of the luminance signal Y and the two color difference signals Cb and Cr can be used as input data. . Of course, the color difference signals Cb and Cr can be used as input data. However, when the serial data in which the color difference signals Cb and Cr are alternately arranged is used as input data, the first and second embodiments are developed. Thus, by configuring as in the following third embodiment, it is possible to correspond to serial data arranged alternately.
[0043]
<Third Embodiment>
The third embodiment shown in FIG. 10 is an example using a 4-tap interpolation filter, as in the first embodiment shown in FIG. 10, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof will be omitted as appropriate. In FIG. 10, serial data in which color difference signals Cb and Cr are alternately arranged is input to the memories 10 to 13 as input data of a video signal to be enlarged or reduced.
[0044]
A specific operation of the third embodiment shown in FIG. 10 will be described in detail with reference to FIG. 11 and subsequent drawings. 11, (A) shows input data to the memories 10 to 13, and 0, 1, 2, 3,... Are pixel numbers. If the color difference signals Cb and Cr are expressed as B and C for simplification, the input data B and C are alternately arranged, so that 0, 0, 1, 1, 2, 2, 3, 3. Become. The data write control unit 15 supplies write enables a to d as shown in FIGS. 11B to 11E to the memories 10 to 13, respectively. The write enables a to d here are different from the write enables a to d in FIG. 2 and have a high period of two pixels.
[0045]
When the write enable (a to d) is high, the input data shown in FIG. 11 (A) is written, so that the memories 10 to 13 are respectively shown in FIGS. 11 (F) to (I). Data (write data a to d) is written. For example, pixel data of pixel numbers 0, 0, 4, 4, 8, 8, 12, 12. As described above, in the third embodiment, the color difference signals Cb and Cr arranged alternately are sequentially written in the memories 10 to 13 as a pair.
[0046]
The address selection control unit 16 operates in the same manner as in FIG. 12A to 12H are the same as FIGS. 4A to 4H. The address selection control unit 16 generates read addresses a to d shown in FIGS. 12E to 12H as in FIG. In the third embodiment shown in FIG. 10, the read addresses a to d are not input to the memories 10 to 13 as they are, but the read addresses a to d are converted based on predetermined conversion conditions by the address conversion unit 36. Input to memories 10-13. This is because the color difference signals Cb and Cr are written as a set in the memories 10 to 13 and it is necessary to perform an interpolation operation on the set data with the same interpolation phase.
[0047]
The address conversion unit 36 converts the input read addresses a to d into read addresses a ′ to d ′ shown in FIGS. 12I to 12L and supplies them to the memories 10 to 13. As the conversion condition, the address conversion unit 36 doubles the input read addresses a to d (value n) (2n), adds 1 to it (2n + 1), and delays one clock. Select and output alternately. As can be seen from FIG. 12, the address conversion unit 36 does not generate the read addresses a ′ to d ′ based on the read addresses a to d at all timings, but only the read address a at one timing every two timings. ˜d are used to generate read addresses a ′ to d ′.
[0048]
FIG. 15 is a specific configuration example of the address conversion unit 36. In FIG. 15, input addresses (read addresses a to d) are doubled by a multiplier 361. The output of the multiplier 361 is input to the adder 362 and one terminal of the switch 364. The adder 362 adds 1 to the output of the multiplier 361. The output of the adder 362 is delayed by one clock by the delay unit 363 and input to the other terminal of the switch 364. A switch signal is input to the switch 364, and the switch 364 alternately selects the output of the multiplier 361 and the output of the delay unit 363. The conversion process shown in FIG. 15 is performed for all the read addresses a to d.
[0049]
With the above configuration, the address conversion unit 36 reads the read address a based on the conversion condition that the read addresses a to d are doubled and the one added to the read address a to d is alternately selected. 'To d' are generated. The conversion condition in the address conversion unit 36 is determined by how data is written to the memories 10 to 13, that is, how many data (pixels) are written into the memories 10 to 13. .
[0050]
Since the addresses for reading data in the memories 10 to 13 are as shown in FIGS. 12I to 12L, the data (read data a to d) read from the memories 10 to 13 are the same as those shown in FIGS. P).
[0051]
Next, returning to FIG. 10, the coefficient generator 17 and the coefficient selection controller 18 operate in exactly the same way as in FIG. FIGS. 13A to 13G are the same as FIGS. 5A to 5G. The coefficient selection control unit 18 generates the coefficients α to δ shown in FIGS. 13H to 13K as in FIG. In the third embodiment shown in FIG. 10, the coefficients α to δ are not input to the interpolation filter 14 as they are, but the coefficients α to δ are converted based on a predetermined conversion condition by the coefficient conversion unit 38 to be used for the interpolation filter 14. To enter. This is because the read data a to d from the memories 10 to 13 are as shown in FIGS. 12 (M) to (P), and it is necessary to perform an interpolation operation using the same coefficient for the paired data. Because.
[0052]
As shown in FIGS. 13L to 13O, the coefficient conversion unit 38 holds and outputs the input coefficients α to δ for each clock as conversion conditions, and outputs the multiplier 141 of the interpolation filter 14 as shown in FIGS. The coefficients α to δ actually supplied to ˜144 are generated.
[0053]
FIG. 16 is a specific configuration example of the coefficient conversion unit 38. In FIG. 16, input coefficients (coefficients α to δ) are input to the delay unit 381. An enable signal is input to the delay unit 381, and the delay unit 381 validates the hold every clock. Accordingly, as shown in FIG. 13, the coefficients α to δ generated by the coefficient selection control unit 18 are used as input coefficients to the interpolation filter 14 at only one timing every two timings, and the same coefficients α to δ are used for two timing periods. δ is supplied to the interpolation filter 14. The conversion condition in the coefficient conversion unit 38 is determined by how data is written in the memories 10 to 13, that is, how many data (pixels) are written in the memories 10 to 13. .
[0054]
14A to 14D show read pixel data from the memories 10 to 13 shown in FIGS. FIGS. 14E to 14H show the coefficients shown in FIGS. 13L to 13O. The interpolation data output from the interpolation filter 14 is as shown in FIG.
[0055]
In the third embodiment described above, the case where two data (2 pixels) are written to the memories 10 to 13 as a set has been described. However, the present invention sets three or more data (3 pixels or more) as a set. It can also be used when writing to the memories 10-13. For example, when serial data in which the three primary color signals R, G, B are regularly arranged is used as input data, the three data (3 pixels) of R, G, B are combined into the memories 10-13. Write.
[0056]
As described above, the conversion condition in the address conversion unit 36 and the conversion condition in the coefficient conversion unit 38 may be appropriately changed depending on how many sets of data are written into the memories 10 to 13. As an example, when three pixels are used as a group, when the readout address is n, 3n, 3n + 1, and 3n + 2 are sequentially switched. In addition, the coefficients α to δ are the same for three timings in succession.
[0057]
In the case of serial data in which M types of video signals (M is an integer of 2 or more) are arranged in order, M pixels are used as a set. Therefore, the conversion condition in the address conversion unit 36 is Mn, Mn + 1,. -1). The conversion condition in the coefficient conversion unit 38 is that the coefficients α to δ are used for only one timing at the M timing, and the coefficients α to δ are used continuously for the M timing.
[0058]
Also in the third embodiment shown in FIG. 10, the video signal can be scaled in the vertical direction by writing a plurality of lines of data into the memories 10-13. Furthermore, the number of memories and the number of taps of the interpolation filter are not limited to four. Similarly to the first and second embodiments, the number of memories (N) and the number of interpolation filter taps (N) may be integers of 2 or more.
[0059]
【The invention's effect】
As described above in detail, the video signal processing apparatus of the present invention uses one pixel data or one line data constituting a video signal as one unit of data, and one unit of data is sequentially input in time series. The output data is generated by enlarging or reducing the input data.
[0060]
The first to Nth N memories and the first plurality of units of input data are expanded into an N-phase data string so that the input data is first to Nth for each unit of data. Write control means for controlling to sequentially and sequentially write to the memory.
[0061]
Also, this is data for deciding which memory to start reading data from among the first to Nth memories, set according to the enlargement / reduction ratio, and generates data for each unit of output data Start memory determination data that changes with the progress of the timing to be read and data for determining an address for reading data in the memory to start reading, which is set in accordance with the enlargement / reduction ratio, and for each unit of output data Address determination data that changes with the progress of the data generation timing, and from the first to Nth memories, N units that are continuous in time series from one unit of data read from the memory that starts reading. Read control means for controlling to read data is provided.
[0062]
Furthermore, it is data indicating in what phase the data of each unit of the output data is generated with respect to the data of each unit of the input data, and is set according to the enlargement / reduction ratio. Coefficient generating means for generating N interpolation coefficients according to the phase data that changes with the progress of the timing of generating the unit data, and interpolation for rearranging the N interpolation coefficients according to the start memory determination data Coefficient rearranging means. An N-tap interpolation filter that generates output data using N units of data read from the first to N-th memories and N interpolation coefficients rearranged by the interpolation coefficient rearranging means; It was configured with.
[0063]
With the above configuration, the video signal processing apparatus of the present invention has a small circuit scale, can cope with both enlargement and reduction of video, and can easily switch between enlargement and reduction. Therefore, the video signal processing apparatus according to the present invention has a substantially constant display size in the horizontal central portion of the screen, and a non-linear mode in which the video is sequentially enlarged as it approaches the left and right end portions in the left and right portions. It is very suitable for use in aspect conversion in which reduction and enlargement are mixed in one screen.
[0064]
Further, serial data in which pixel data or line data constituting M types of video signals are sequentially arranged in time series is input as input data, and the input data is enlarged or reduced by interpolation calculation to generate output data. In such a case, each M unit data is cyclically written sequentially into the first to Nth memories, and the M unit data is preliminarily interpolated with the same interpolation phase. Based on the predetermined first conversion condition, N read addresses are converted, and the predetermined second conversion condition is set so that interpolation calculation is performed on the data in M units with the same coefficient. Based on this, N interpolation coefficients are converted.
[0065]
With this configuration, the video signal processing apparatus of the present invention can scale up and down serial data in which a plurality of types of video signals are arranged in order.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a data write operation to memories 10 to 13 in FIG. 1;
FIG. 3 is a diagram illustrating an example of a relationship between input data pixels and output data pixels in a reduction process;
4 is a diagram for explaining a data read operation from memories 10 to 13 in FIG. 1; FIG.
FIG. 5 is a diagram for explaining an operation of supplying an interpolation coefficient to the interpolation filter 14 in FIG. 1;
FIG. 6 is a diagram illustrating an example of a table of interpolation coefficients.
7 is a block diagram showing a specific configuration example of the interpolation filter 14 in FIG. 1. FIG.
8 is a diagram for explaining an operation of generating interpolation data in the interpolation filter 14 in FIG. 1. FIG.
FIG. 9 is a block diagram showing a second embodiment of the present invention.
FIG. 10 is a block diagram showing a third embodiment of the present invention.
11 is a diagram for explaining a data write operation to memories 10 to 13 in FIG. 10; FIG.
12 is a diagram for explaining a data read operation from memories 10 to 13 in FIG. 10;
13 is a diagram for explaining an operation of supplying an interpolation coefficient to the interpolation filter 14 in FIG. 10;
14 is a diagram for explaining an operation of generating interpolation data in the interpolation filter 14 in FIG. 10;
15 is a block diagram illustrating a specific configuration example of an address conversion unit 36 in FIG. 10;
16 is a block diagram illustrating a specific configuration example of a coefficient conversion unit 38 in FIG.
FIG. 17 is a block diagram showing a general reduction device.
FIG. 18 is a block diagram showing a general enlargement apparatus.
[Explanation of symbols]
10-13, 20-27 Random access memory
14,140 Interpolation filter
15,150 Data write control unit (write control means)
16,160 Address selection control unit (reading control means)
17,170 Coefficient generator (coefficient generator)
18, 180 Coefficient selection control section (interpolation coefficient rearranging means, interpolation coefficient rearranging section)
36 Address converter
38 Coefficient converter

Claims (4)

Video signal for generating output data by enlarging or reducing input data to which one pixel data or one line data constituting a video signal is set as one unit of data, and the one unit of data is sequentially input in time series In the processing device,
First to Nth N (N is an integer of 2 or more) memories each having a plurality of addresses for writing data ;
Write control means for controlling the input data to be cyclically sequentially written to each address of the first to Nth memories for each unit of data;
Among the first to Nth memories, data for determining which memory to start reading data, is set according to the enlargement / reduction ratio, and generates data for each unit of the output data Start memory determination data that changes with the progress of timing, and data for determining an address for reading data in the memory to start reading, which is set according to the enlargement / reduction ratio, and is set for each unit of the output data The address determination data that changes with the progress of the data generation timing, and the time-sequential N from one unit of data read from the first to Nth memories from the memory that starts reading. Read control means for controlling to read out unit data;
It is data indicating in what phase the data of each unit of the output data is generated with respect to the data of each unit of the input data, is set according to the enlargement / reduction ratio, and the unit of each unit of the output data Coefficient generating means for generating N interpolation coefficients in accordance with the phase data that changes as the data generation timing progresses;
Interpolation coefficient rearranging means for rearranging the N interpolation coefficients according to the start memory determination data;
N tap interpolation for generating the output data using the N units of data read from the first to Nth memories and the N interpolation coefficients rearranged by the interpolation coefficient rearranging means. A video signal processing apparatus comprising a filter. Serial data in which pixel data or line data constituting M types of video signals (M is an integer of 2 or more) is sequentially input is input as input data, and the input data is enlarged or reduced by interpolation calculation. In the video signal processing device that generates output data by
First to Nth N (N is an integer of 2 or more) memories each having a plurality of addresses for writing data ;
One pixel data or one line data in the input data is used as one unit of data, and the M-type data including the M kinds of video signals is rotated for each address of the first to Nth memories. Write control means for controlling to write sequentially,
Among the first to Nth memories, data for determining which memory to start reading data, is set according to the enlargement / reduction ratio, and generates data for each unit of the output data Start memory determination data that changes with the progress of timing, and data for determining an address for reading data in the memory to start reading, which is set according to the enlargement / reduction ratio, and is set for each unit of the output data The address determination data that changes with the progress of the data generation timing, and the time-sequential N from one unit of data read from the first to Nth memories from the memory that starts reading. An address selection control unit for generating N read addresses for reading unit data;
The N read addresses are converted based on a predetermined first conversion condition so that the M units of data are interpolated with the same interpolation phase. An address converter to be supplied to the memory of
It is data indicating in what phase the data of each unit of the output data is generated with respect to the data of each unit of the input data, is set according to the enlargement / reduction ratio, and the unit of each unit of the output data A coefficient generator for generating N interpolation coefficients in accordance with the phase data that changes with the progress of the data generation timing;
An interpolation coefficient rearranging unit for rearranging the N interpolation coefficients according to the start memory determination data;
A coefficient conversion unit that converts the N interpolation coefficients based on a predetermined second conversion condition so that the M units of data are interpolated with the same coefficient;
An N-tap interpolation filter that generates the output data using the N units of data read from the first to Nth memories and the N interpolation coefficients converted by the coefficient conversion unit. A video signal processing apparatus characterized by comprising.   The video signal processing apparatus according to claim 1, wherein the N is four.   3. The video signal processing apparatus according to claim 2, wherein M is 2, and the two types of video signals are first and second color difference signals.

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