JP3807182B2 - Control device for automatic transmission for automobile - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an improvement in a control device for an automatic transmission for automobiles.
[0002]
[Prior art]
In vehicles equipped with automatic transmissions with 4 or more speeds, there is an overdrive kill switch to limit the selection of overdrive in order to meet the demands of rapid acceleration combined with engine braking on long downhills and downshifts. Usually deployed.
[0003]
In most automatic vehicles, this overdrive kill switch consists of an alternate switch.
[0004]
However, when the alternate switch is used, if the ignition is turned off with the overdrive kill switch turned on, the switch remains on even after the vehicle is restarted and the overdrive is not selected. The state continues. As a result, if the driver forgets that the switch was turned on at the time of parking and stopping and restarted driving, overdrive was not selected at any time, and fuel consumption was reduced. It was.
[0005]
There is known a method for solving the above problem by configuring an overdrive kill switch with a momentary switch and enabling overdrive by a process on the control device side when the ignition is started.
[0006]
In this case, the overdrive stage can be used or not switched during driving by detecting the operation signal from the overdrive kill switch constituted by a momentary switch, more specifically, the rising signal thereof by the control device, and overdrive. This is achieved by cyclically switching the use of the.
[0007]
In other words, the overdrive stage can be used at the start of travel, the next time the momentary switch is operated, the overdrive stage cannot be used and overdrive selection is prohibited, and if the momentary switch is operated again, The overdrive stage can be used and the selection of overdrive is permitted.
[0008]
However, sometimes an erroneous operation occurs such that the overdrive kill switch is pressed twice due to the vibration of the vehicle when traveling on a rough road or a simple operation error by the driver.
[0009]
As described above, since the overdrive stage can be used or not can be switched immediately by detecting the rising signal of the switch operation, when the overdrive kill switch is pressed twice, for example, FIG. The phenomenon shown in b) occurs.
[0010]
FIG. 7B is a timing chart illustrating a shift operation when the switch is pushed twice in an automatic vehicle having a four-speed automatic transmission and an overdrive kill switch composed of a momentary switch. In the downhill section X where the engine load is lighter, when the 4th speed (overdrive) can be selected, the use of the overdrive stage is prohibited and an engine brake with 3rd speed is obtained. It is.
[0011]
Therefore, it is the section of X in FIG. 7B that actually wants to use the third speed. For this reason, the driver operates the overdrive kill switch at the time of A1 to prohibit the use of overdrive and forcibly switches the automatic transmission to the 3rd speed. The rise of the operation signal is detected again at the time point A2, and the control device determines that this signal is a switching signal for enabling or disabling the overdrive stage, and immediately causes the use of the fourth speed. . For this reason, the engine brake by the third speed is actually effective only in the section X1 in the entire section X, and sufficient engine brake cannot be obtained in the section X2.
[0012]
Further, since the engine brake is not necessary after passing through the section of X, it is desirable to permit the use of overdrive to improve fuel consumption. Therefore, the driver tries to permit the use of the fourth speed again by operating the overdrive kill switch at the time of A3. However, in actuality, the overdrive kill switch is already at the time of A2 due to the erroneous operation of pressing twice as described above. It is turned off. Therefore, if the driver does not notice this and operates the overdrive kill switch again at the time of A3, the use of the overdrive is prohibited again, and the gear shifting work completely different from what the driver desires can be performed and used. A problem arises that the speed change stage is limited from the first speed to the third speed. If the driver continues driving with an illusion, the overdrive use prohibition state is maintained as it is, and the fuel consumption may be significantly reduced.
[0013]
In the above, an example of the inconvenience caused by pressing the overdrive kill switch twice has been described. However, repeated unnecessary upshifts and downshifts reduce fuel consumption and hinder smooth running. There are harmful effects such as.
[0014]
[Problems to be solved by the invention]
In order to solve such a problem, a delay may be provided for ON / OFF of the overdrive kill switch.
[0015]
However, when such a configuration is applied, a speed change operation that requires an emergency, for example, when it is desired to perform sudden acceleration by downshifting or when it is desired to quickly perform downshifting and perform deceleration by engine braking In some cases, you may be worried about delayed response.
[0016]
OBJECT OF THE INVENTION
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to improve the responsiveness, in particular, the responsiveness at the time of downshifting operation, and to prevent the driver's illusion and the reduction in fuel consumption with respect to the selected gear position. It is to provide a control device for an automatic transmission.
[0017]
[Means for Solving the Problems]
The present invention provides a momentary switch for manually setting whether or not overdrive can be used, shift limitation state storage means for storing whether or not overdrive can be used, and the shift limitation every time a rising signal of the momentary switch is detected. A vehicle-equipped vehicle comprising: a shift limitation state rewriting unit that rewrites the contents stored in the state storage unit cyclically; and an automatic transmission unit that selects a shift stage within a range of the shift limitation stored in the shift limitation state storage unit. In order to achieve the above object, the automatic transmission control device is provided with a delay means for turning on and off the momentary switch, and moreover, the delay time when turning from ON to OFF than when turning from OFF to ON is reduced. Characterized by lengthening.
[0018]
Here, the momentary switch that constitutes the overdrive kill switch is ON only while the switch is operated, for example, when it is pressed by hand, and when the switch is in a non-operating state, for example, the hand is released. Sometimes this switch is automatically turned off. Accordingly, a rising signal from OFF to ON is detected at the start of the switch operation, and a falling signal from ON to OFF is detected at the time of completion of the switch operation. That is, one operation of the switch is always divided by a pair of rising signal and falling signal, and it is impossible for the switch to be pressed twice between the rising signal and the falling signal.
When the driver operates the momentary switch, a rising signal of the momentary switch is detected, and it is determined whether or not the detection timing is within a delay time after the falling signal of the momentary switch is detected.
If the detection timing of the current rising signal is after the lapse of the delay time, the shift limit state rewriting unit causes the stored contents of the shift limit state storage unit to be rewritten cyclically.
In other words, the shift limit state storage means is a storage means that can store only one of the shift limit that can be used for overdrive and the shift limit that cannot be used for overdrive. If the limit is stored, the limit condition that disables overdrive is newly written by the detection of the rising signal described above, and if the shift limit that disables overdrive is stored before that, Thus, the detection of the rising signal described above newly writes a restriction condition for enabling overdrive.
However, if the detection timing of the current rising signal is within the delay time, the switch is still in the ON state even after detecting the falling signal, so even if the rising signal is detected, it is ignored. Therefore, even when the momentary switch is operated, the stored content of the speed limit state storage means is held in the same state as before.
Then, the automatic transmission means selects the gear position accurately within the range of the speed limit stored in the speed limit state storage means at the present time according to the engine load and other conditions, and executes the automatic speed change.
Therefore, when the momentary switch is continuously pressed twice, only the first operation is valid, and the second operation, that is, an erroneous operation is ignored by the action of the delay means. As a result, useless gear shifting operations and gear shifting operations not intended by the driver are prevented from occurring, and the driver's illusion regarding the reduction in fuel consumption and the gear selection state is eliminated. In addition, since the first operation before being pushed twice is accurately detected without a time delay, the gear shifting operation intended by the driver is performed reliably. Deceleration by engine braking can be carried out reliably without delay.
[0019]
Further, the shift restriction state rewriting means may be provided with an initial setting means for detecting the start of the ignition and writing a shift restriction that can be used for overdrive in the shift restriction state storage means.
[0020]
When this configuration is applied, the overdrive kill switch is automatically released when the ignition is started.Therefore, the overdrive is not It becomes possible to carry out driving with good fuel efficiency using the drive.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing the functions of a control device 1 (hereinafter simply referred to as a control device) for an automobile automatic transmission to which the present invention is applied.
[0022]
Of these, the momentary switch 2 constitutes an overdrive kill switch for manually setting whether or not the overdrive can be used, and is provided at the tip of the shift knob. Hereinafter, this momentary switch is referred to as ODS.
[0023]
Further, the shift restriction state storage means 3 is constituted by a memory built in or connected to the CPU 8 (see FIG. 2) provided in the control device 1, and is a shift restriction for overdrive use or a shift restriction for overdrive use. One of them is memorized.
[0024]
The delay means 4 is constituted by a predetermined arithmetic program executed by the CPU 8, and sends the rising information of ODS2 to the shift restriction state rewriting means 5 after the elapse of a predetermined time T1 after detecting the rising signal of ODS2, and after detecting the falling signal When the predetermined time T2 has elapsed, the falling information of ODS2 is sent to the shift restriction state rewriting means 5.
[0025]
The shift restriction state rewriting means 5 is constituted by a predetermined arithmetic program executed by the CPU 8, and whenever the rising information of the ODS 2 is sent from the delay means 4, the stored contents of the shift restriction state storage means 3 can be used from overdrive use. A function is provided for cyclically rewriting from overuse disabled or overdrive disabled to overdrive enabled.
[0026]
The shift limit state rewriting unit 5 includes an initial setting unit 6 that detects the start of the ignition and writes the overdrive-usable shift limit in the shift limit state storage unit 3.
[0027]
The automatic transmission means 7 is constituted by a predetermined calculation program executed by the CPU 8, receives signals from various sensors connected to the control device 1, calculates an operating condition such as an engine load, and changes the speed at that time. Within the range of the speed limit stored in the limit state storage means 3, the gear stage most suitable for the aforementioned driving situation is selected, and various signals are output to the automatic transmission 9 (see FIG. 2) to execute the speed change operation. Let
[0028]
In the present embodiment, an automatic vehicle including an automatic transmission 9 capable of four-speed gear shifting operation including overdrive is described as an example. Can be selected from the first speed to the fourth speed, and in the state in which the shift limitation that disables overdrive is stored in the shift limitation state storage means 3, overdrive is possible. Only the selection of the 4th speed is prohibited, and the shift speeds from the 1st speed to the 3rd speed can be selected.
[0029]
FIG. 2 is a block diagram specifically showing a connection relationship between the automatic transmission 9 and the engine 10 and the control device 1.
[0030]
The engine 10 includes a throttle opening sensor 11 for detecting the engine load, a water temperature sensor 12 for detecting the coolant temperature of the engine cooling water, and a rotation sensor 13 for detecting the crank rotational speed of the engine 10. Is provided. The automatic transmission 9 is also provided with an input shaft rotation sensor 14 for detecting the rotation speed of the input shaft connected to the engine 10 and a shift position detection sensor 15 for detecting the position of the travel range selection shift knob. Yes. Further, a vehicle speed sensor 17 for detecting the traveling speed of the vehicle is provided in the vicinity of the drive shaft 16 that rotates in synchronization with the drive wheels, and the brake operation system includes a brake operation for detecting the operating state of the brake. A detection sensor 18 is provided.
[0031]
Then, data detected by these sensors 11 to 15 and 17 and 18 is input to the CPU 8 of the control device 1, and the CPU 8 as the automatic transmission means 7 performs the current driving situation according to a predetermined calculation program as in the prior art. The shift stage most suitable for the automatic transmission 9 is obtained by calculation, and the shift solenoids SOL1, SOL2 and the lockup solenoid SOL3 of the automatic transmission 9 are driven and controlled to automatically switch the shift stage of the automatic transmission 9. However, when the speed limit that disables overdrive is stored in the memory that functions as the speed limit state storage means 3, the selection of the fourth speed corresponding to the overdrive is prohibited, and the third speed is changed to the fourth speed. A stage will be selected.
[0032]
In this embodiment, an automatic transmission 9 having a planetary gear mechanism is used, and shift solenoids SOL1 and SOL2 are used for performing a shifting operation by switching the hydraulic operation to various clutches and brake bands, The lockup solenoid SOL3 is used to turn on / off the lockup clutch.
[0033]
Hereinafter, with reference to the flowcharts of FIGS. 3 to 6 and the timing chart of FIG. 7A, the processing operation of the CPU 8 functioning as the shift limit state rewriting means 5 and the delay means 4, and the shift limit state storage. The rewrite operation of the shift restriction for the memory as means 3 will be described in detail. In the timing chart of FIG. 7A, in order to clarify the difference from the prior art, the case where ODS2 is pressed twice in the same situation as described in FIG. 7B is shown as an example. ing.
[0034]
As described above, in the present embodiment, the ODS2 falling information is sent to the shift restriction state rewriting means 5 after the elapse of the predetermined time T2 after the detection of the ODS2 falling signal. It is necessary to measure the elapsed time using. First, the timer T activation process will be described with reference to the flowchart of FIG.
[0035]
FIG. 4 is a flowchart showing an outline of a timer process repeatedly executed at predetermined intervals as one of the task processes of the CPU 8. This timer process is used not only for measuring the elapsed time t2 after detecting the falling signal of ODS2, but also for measuring the elapsed time t1 after detecting the rising signal.
[0036]
The CPU 8 that has started the timer process first determines whether or not the signal from the ODS 2 is ON (step b1). If the signal from the ODS 2 is OFF, the switch ON operation memory is further stored. It is determined whether or not the flag F1 is set, that is, whether or not ODS2 is ON in the previous cycle (step b5).
[0037]
The switch ON operation storage flag F1 is automatically reset at the start of operation by the process of step a1 in the initialization process of FIG. 3 that is performed only once when the ignition is started. The operation memory flag F1 is always in a reset state.
[0038]
Therefore, after the start of driving, as long as the driver does not operate ODS2, only the determination process of step b1 and step b5 is repeatedly executed every predetermined period, and the timer T does not operate at all.
[0039]
Here, when the driver operates the ODS2, the CPU 8 detects the ON state of the ODS2 in the determination process of step b1 in the timer process. Next, the CPU 8 determines whether or not the switch ON operation storage flag F1 has been reset, that is, whether or not the ODS2 has been turned OFF in the previous cycle (step b2). Since the switch ON operation storage flag F1 is held in the reset state, the determination result in step b2 is true.
[0040]
Therefore, the CPU 8 resets and restarts the timer t1, starts measuring the elapsed time after detecting the rising signal of ODS2 (step b3), sets the switch ON operation storage flag F1, and turns ODS2 ON. The fact of switching is stored (step b4).
[0041]
As a result of setting the switch ON operation storage flag F1 in this way, only the determination processing of step b1 and step b2 is repeatedly executed in the timer processing after the next cycle. During this time, the timer t1 is set to ODS2 Measurement of the elapsed time after detection of the rising signal is continued.
[0042]
In this way, for example, the elapsed time is measured based on the time point A1 or A3 in FIG. 7A.
[0043]
When the determination process of step b1 detects that the ODS2 is turned off while the determination process of step b1 and step b2 is repeatedly executed, the CPU 8 further sets the switch ON operation storage flag F1. It is determined whether or not ODS2 is ON in the previous cycle (step b5).
[0044]
As is apparent from the above description, the switch ON operation storage flag F1 is already set at this stage, so the determination result in step b5 is true. This means that ODS2 is switched from ON to OFF from the processing of the previous cycle to the processing of this cycle, and the falling of ODS2 is detected. Therefore, the CPU 8 resets and restarts the timer t2, starts measuring the elapsed time after the falling signal is detected (step b6), resets the switch ON operation storage flag F1, and switches ODS2 to OFF. (Step b7).
[0045]
As a result of resetting the switch ON operation storage flag F1 in this way, only the determination processing of step b1 and step b5 is repeatedly executed in the timer processing after the next period, and during this time, the timer t2 is the falling signal of ODS2. The measurement of the elapsed time after detection is continued.
[0046]
In this way, for example, the elapsed time is measured based on the time point B1, B2, or B3 in FIG. 7A.
[0047]
The above is the outline of the processing related to the start of the timer T.
[0048]
FIG. 5 is a flowchart showing an outline of the determination value setting process related to the ON / OFF switching of the determination value S sent from the delay means 4 to the shift restriction state rewriting means 5, and this process is also the same as the timer process described above. Similarly, it is repeatedly executed at predetermined intervals as one of the task processes of the CPU 8.
[0049]
The CPU 8 that has started the determination value setting process first determines whether or not the signal from the ODS2 is ON (step c1). If the signal from the ODS2 is OFF, the determination value is further determined. It is determined whether or not S is ON (step c5).
[0050]
Since the determination value S is automatically set to OFF at the start of operation by the process of step a3 in the initialization process of FIG. 3 that is performed only once when the ignition is started, at least in the stage immediately after the start of operation. S is always in an OFF state.
[0051]
Therefore, in the stage immediately after the start of operation, only the determination processing of step c1 and step c5 is only repeatedly executed every predetermined period.
[0052]
Here, when the driver operates ODS2, the CPU 8 detects the ON state of ODS2 in the determination process of step c1 in the determination value setting process. Also in the timer process described above, the ON state of ODS2 is detected, and the measurement of the elapsed time t1 after the rising signal detection of ODS2 is started according to the algorithm described above.
[0053]
Next, the CPU 8 determines whether or not the determination value S is ON (step c2). As described above, since the determination value S is held in the OFF state at this stage, the determination result in step c2 Becomes OFF.
[0054]
Therefore, the CPU 8 determines whether or not the measurement time of the timer t1 after detecting the rising signal of the ODS2 has reached a predetermined time T1 (for example, set in a range of about 0 to several tens of ms) (step c3). If the measurement time of the timer t1 does not reach the predetermined time T1, the CPU 8 is in a stage immediately after the operation of the ODS2, so the CPU 8 ignores the determination result of step c1, that is, the determination result that the ODS 2 is switched to ON. The process of step c4 is skipped, and the determination value setting process of the cycle is finished as it is.
[0055]
Thereafter, the CPU 8 repeatedly executes the determination processing of step c1, step c2, and step c3 for each predetermined period, and waits for the measurement time of the timer t1 to reach the predetermined time T1.
[0056]
Finally, when the measurement time of the timer t1 after detecting the rising signal of ODS2 reaches the predetermined time T1, and the determination result in step c3 is true and the operation of ODS2 is confirmed, the CPU 8 turns on the determination value S. (Step c4). An example of the timing at which the determination value S is switched ON is shown at the time C1 in FIG.
[0057]
As a result of the determination value S being turned on in this way, only the determination processing at step c1 and step c2 is repeatedly executed in the determination value setting processing after the next period.
[0058]
Then, when such a process is repeatedly executed and one operation of ODS2 is completed and the signal from ODS2 is switched from the ON state to the OFF state, this change is detected by the determination process in step c1. Also in the timer process described above, the OFF state of ODS2 is detected, and measurement of the elapsed time t2 after the falling signal detection of ODS2 is started according to the algorithm described above.
[0059]
Next, the CPU 8 determines whether or not the determination value S is ON (step c5). Since the determination value S is in an ON state at this stage, the determination result in step c5 is ON.
[0060]
Therefore, the CPU 8 determines whether or not the measurement time of the timer t2 after detecting the falling signal of the ODS2 has reached the predetermined time T2 (step c6), but the measurement time of the timer t2 has not reached the predetermined time T2. For example, the CPU 8 ignores the determination result of step c1, that is, the determination result that ODS2 has been switched off, skips the process of step c7, and ends the determination value setting process of the cycle as it is.
[0061]
Thereafter, the CPU 8 repeatedly executes the determination processing of step c1, step c5, and step c6 every predetermined period, waits for the measurement time of the timer t2 to reach the predetermined time T2, and holds the determination value S in the ON state during this time. . This standby period corresponds to, for example, a T2 width time zone with the time point B1 in FIG.
[0062]
During this time, if the ODS2 is pressed twice at the time of A2 due to an erroneous operation by the driver, the CPU 8 will again detect the change of ODS2 from OFF to ON in the determination process of step c1. Further, in the above-described timer processing, a change from OFF to ON of ODS2 is detected, but the timer t2 is not reset. As shown in FIG. 7A, the timer t2 indicates the elapsed time from the time point B1. The measurement will continue as it is.
[0063]
Next, the CPU 8 proceeds to the process of step C2 and determines whether or not the determination value S is ON (step c2). As described above, the determination value S is held in the ON state at this stage. Therefore, the determination result in step c2 is ON, and the CPU 8 ends the determination value setting process for the period while holding the determination value S in the ON state, and the determination process in step c1 and step c2 is performed in the process after the next period. Will be executed repeatedly.
[0064]
While such processing is repeatedly executed, for example, when the ODS 2 is switched from the ON state to the OFF state at time B2 in FIG. 7A, this change is detected by the determination processing in step c1. Also, in the timer processing described above, a change from ON to OFF of ODS2 is detected, and measurement of the elapsed time t2 after the detection of the falling signal of ODS2 is started according to the algorithm described above.
[0065]
Next, the CPU 8 determines whether or not the determination value S is ON (step c5). As described above, since the determination value S is maintained in the ON state at this stage, the determination result in step c5 Becomes ON.
[0066]
Accordingly, the CPU 8 determines whether or not the measurement time of the timer t2 after detecting the falling signal of the ODS2 has reached the predetermined time T2 (step c6), but the measurement time of the timer t2 has not reached the predetermined time T2. For example, the CPU 8 ignores the determination result of step c1, that is, the determination result that ODS2 has been switched off, skips the process of step c7, and ends the determination value setting process of the cycle as it is.
[0067]
Thereafter, the CPU 8 repeatedly executes the determination processing of step c1, step c5, and step c6 every predetermined period, waits for the measurement time of the timer t2 to reach the predetermined time T2, and holds the determination value S in the ON state during this time. . This period corresponds to, for example, a T2 width time zone with the time point B2 in FIG.
[0068]
If the operation of ODS2 is not detected during this time, the determination result of step c6 becomes true when the measurement time of the timer t2 reaches the predetermined time T2, and the CPU 8 turns the determination value S OFF (step c7).
[0069]
An example of the timing at which the determination value S is switched to OFF is shown at the point D1 in FIG. At this stage, both the ODS2 and the determination value S are turned off to return to the initial state, and the situation is the same as before the time point A1 in FIG.
[0070]
Of course, there is a possibility that the ODS2 is erroneously operated between the time point B2 and the time point D1, and the phenomenon of pushing three times may occur, but in this case, the same processing as the time point A2 described above is performed. Thus, the determination value S is held in the ON state.
[0071]
After a certain amount of time has elapsed after the determination value S is rewritten in this way, for example, when the ODS 2 is normally operated again at time A3 in FIG. The processing operation similar to that at the time point A1 is repeatedly executed. That is, the determination value S is reset to ON at the time point C2 after a delay of T1 from the time point A3 when the ON state of the ODS2 is detected.
[0072]
As is clear from the above description, the determination value S is set ON after a delay of T1 from the time when the rising signal of ODS2 is first detected, and after the falling signal corresponding to this rising signal is detected. Until the predetermined time T2 elapses, the determination value S is maintained as it is. When a new rising signal of ODS2 is detected within the time T2, the falling signal is detected until a falling signal corresponding to the rising signal detected at this time is detected. The determination value S is held in the ON state as it is from the detection until the predetermined time T2 elapses.
[0073]
That is, when ODS2 is operated continuously, no matter how many times the operation is performed, the continuous operation is repeated and between the end of the last operation and the elapse of time T2. That is, the ON state of the determination value S is maintained.
[0074]
Therefore, for example, when the rising signal and the falling signal of ODS2 are continuously detected by pressing the ODS2 twice or the third time as in the time points A1, B1 and A2, B2 in FIG. Even if there is, by using the judgment value S that is the speed limit state, these continuous ON / OFF without being confused by the rising signal and falling signal frequently generated by pressing twice or three times. The operation can be recognized as one integrated ON / OFF operation.
[0075]
Therefore, the rise of the judgment value S itself, that is, the change of the judgment value S from OFF to ON is detected, and at this detection timing, the content stored in the speed limit state storage means 3 is changed from overdrive usable to overdrive unavailable. Alternatively, it is possible to avoid a meaningless speed change operation caused by pressing the ODS 2 twice or three times by cyclically rewriting from overdrive unusable to overdrive usable.
[0076]
FIG. 6 is a flowchart showing an outline of the shift limit rewriting process for rewriting the stored contents of the shift limit state storage means 3 (see FIG. 1). This process also includes the timer process and the determination value setting process described above. Similarly, it is repeatedly executed at predetermined intervals as one of the task processes of the CPU 8.
[0077]
The CPU 8 that has started the shift restriction rewriting process first determines whether or not the determination value S is ON (step d1). If the determination value S is OFF, the switching completion flag is further determined. It is determined whether or not F2 is set, that is, whether or not the determination value S in the previous cycle is ON (step d7).
[0078]
Since the switch completion flag F2 is automatically reset at the start of operation by the process of step a2 in the initialization process of FIG. 3 that is performed only once when the ignition is started, at least immediately after the start of the operation, the switch completion flag F2 Is always reset.
[0079]
Therefore, in the initial stage after the start of operation, only the determination process of step d1 and step d7 is repeatedly executed at every predetermined cycle, and the rewrite of the stored contents of the speed limit state storage means 3 is not performed at all.
[0080]
Further, the shift limit state storage means 3 automatically permits the fourth speed at the start of operation (overload) by the process of step a4 in the initialization process of FIG. 3 which is performed only once by the initial setting means 6 of the CPU 8 when the ignition is started. In the initial stage of the start of operation, it is possible to select any one of the first to fourth gears according to the calculation result of the CPU 8 as the automatic transmission means 7. Thus, the deterioration of fuel consumption due to the limitation of the used gear stage, which has been a problem in the past, is solved.
[0081]
The CPU 8 as the automatic transmission means 7 (see FIG. 1) also performs processing for obtaining the gear position based on information from the various sensors 11 to 15 and 17 to 18 in another task. Since it is already known and does not have a direct relationship with the present invention, the description is omitted here.
[0082]
If it is detected that the determination value S is switched ON in the determination process of step d1 while the processes of step d1 and step d7 are repeatedly executed, the CPU 8 then resets the switching completion flag F2. It is determined whether or not the determination value S in the previous cycle is OFF (step d2), but as described above, the switching completion flag F2 is held in the reset state at this stage. The determination result at step d2 is true.
[0083]
Next, the CPU 8 determines whether or not a shift limitation prohibiting the 4th speed (unusable overdrive) is written in the shift limitation state storage means 3 (step d3). Therefore, the determination result at step d3 is false. Accordingly, the CPU 8 serving as the speed limit limiting state rewriting means 5 writes a speed limit prohibiting the fourth speed again in the speed limit limiting state storage means 3 to prohibit the use of the fourth speed which is an overdrive (step d6), and the switching completion flag. F2 is set, and the fact that the rewriting process of the shift restriction state storage means 3 accompanying the detection of the rising edge of the determination value S is completed is stored (step d5).
[0084]
As a result of setting the switch completion flag F2 in this way, only the determination process of step d1 and step d2 is repeatedly executed in the shift restriction rewriting process after the next cycle. Means 3 holds the speed limit prohibiting the fourth speed.
[0085]
In this way, for example, the use of the fourth speed, which is an overdrive, is prohibited from the point C1 in FIG. As described above, in the example of FIG. 7A, it is assumed that the vehicle enters a downhill and performs an operation for applying the engine brake. Therefore, the engine load is light, and according to the calculation result of the CPU 8 as the automatic transmission means 7 based on the information of the various sensors 11 to 15 and 17 to 18, the fourth speed can be used. Therefore, the CPU 8 selects the 3rd speed instead of the 4th speed, and the downhill engine brake works effectively. As shown in FIG. 7A, this speed change operation is performed with a delay of the required time T1 when viewed from the first operation start time A1 of the ODS2, but this time is sufficiently short and the driver feels uncomfortable. It ’s not like feeling.
[0086]
As shown in FIG. 7 (a), there is a case in which a double press due to an erroneous operation may occur immediately after execution of the speed change operation at the time A1, for example, at the time A2, but as described above, such a double press may occur. Even if it is performed, the judgment value S is not affected. Therefore, a wasteful speed change operation which has been a problem in the prior art, for example, a waste as seen at time A2 in FIG. 7B. No speed change operation is performed.
[0087]
After that, while the determination value S is held ON, that is, until the time point D1 shown in FIG. 7A is reached, only the determination processing of step d1 and step d2 is repeatedly executed as described above. During this time, the shift limitation state storage means 3 holds the shift limitation prohibiting the fourth speed.
[0088]
When the determination value S is switched from ON to OFF at the time point D1 shown in FIG. 7A, the CPU 8 detects this in the determination process of step d1, and whether or not the switch completion flag F2 is set. That is, it is determined whether or not the determination value S is ON in the previous cycle (step d7). As described above, since the switching completion flag F2 is already set at this stage, the determination result of step d7. Is true.
[0089]
Accordingly, the CPU 8 resets the switching completion flag F2 and stores that the determination value S has been switched from ON to OFF (step d8).
[0090]
As a result of resetting the switching completion flag F2 in this way, only the determination processing of step d1 and step d7 is repeatedly executed in the shift restriction rewriting process after the next cycle. The shift limitation prohibiting the fourth speed is maintained.
[0091]
Then, when it is detected that the determination value S is switched to ON again in the determination process in step d1 while such a process is repeatedly executed, the CPU 8 then checks whether the switching completion flag F2 is reset. Whether or not the determination value S was OFF in the previous cycle is determined (step d2), but as described above, the switching completion flag F2 is held in the reset state at this stage. The determination result at step d2 is true.
[0092]
Next, the CPU 8 determines whether or not a 4-speed prohibition shift restriction is written in the shift restriction state storage means 3 (step d3), but the shift restriction at this stage is prohibited to the 4-speed. The determination result at step d3 is true. Therefore, the CPU 8 serving as the speed limit limiting state rewriting means 5 writes the speed limit for permitting the fourth speed again in the speed limit limiting state storage means 3 and permits the use of the fourth speed that is the overdrive (step d4). F2 is set, and the fact that the rewriting process of the shift restriction state storage means 3 accompanying the detection of the rising edge of the determination value S is completed is stored (step d5).
[0093]
As a result of setting the switch completion flag F2 in this way, only the determination process of step d1 and step d2 is repeatedly executed in the shift restriction rewriting process after the next cycle. Means 3 holds the speed limit for allowing the fourth speed.
[0094]
In this way, for example, the use of the fourth speed, which is an overdrive, is permitted again from the time point C2 in FIG. As described above, in this example, the downhill finishes at the time of A3, the use of the engine brake becomes unnecessary, the shift restriction that the overdrive cannot be used is released, and the automatic based on the information of the various sensors 11 to 15 and 17 to 18 The most suitable gear position is automatically selected according to the calculation result of the CPU 8 as the speed change means 7. At this stage, since the engine load is light with the state immediately after the end of the downhill, as a result, the CPU 8 as the automatic transmission means 7 selects the 4-speed overdrive with the best fuel efficiency and performs the upshifting operation. become.
[0095]
As described above, the double pressing of ODS2 at the time points A1 and A2 is recognized as one operation by the CPU 8, and the restriction of prohibiting the fourth speed is applied from the time point C1 to the time point C2. 7 (a) and the section X shown in FIG. 7 (b), that is, the section where strong engine braking is required, the use of the fourth speed that is overdrive can be surely prohibited.
[0096]
In addition, as a result of the use restriction of the 4th speed prohibition being surely carried out in this section, the driver operates the ODS 2 at the time of A3 at the end of the downhill, thereby reliably releasing the restriction of the 4th speed prohibition, High fuel efficiency driving can be resumed. As a result, as shown in the example of FIG. 7B, the driver is in the 4th speed prohibited state without permission even though the 4th speed is already permitted from the time A2 to the time A3. By illusioning that, by operating ODS2 again at the time of A3, the use of the 4th speed is unintentionally prohibited, and the use of the 4th speed is restricted by itself on a flat road that does not require a strong engine brake. It is possible to reliably prevent the occurrence of operation mistakes / judgment mistakes.
[0097]
When the determination value S is switched from ON to OFF again at the time point D2 by the above-described determination value setting process while the determination process of step d1 and step d2 is repeatedly executed, the CPU 8 performs the determination process of step d1. This is detected, and it is determined whether or not the switching completion flag F2 is set, that is, whether or not the determination value S is ON immediately before the determination process of step d1 in this cycle is executed. (Step d7) As described above, since the set state of the switching completion flag F2 is held at this stage, the determination result in Step d7 is true.
[0098]
Accordingly, the CPU 8 resets the switching completion flag F2 and stores that the determination value S has been switched from ON to OFF (step d8).
[0099]
At this stage, both the determination value S and the switching completion flag F2 are turned off to return to the initial state, and the situation is the same as before the time point A1 in FIG. 7A, and the CPU 8 performs a new operation of the ODS2 and the determination value S. A standby process for detecting a new rising edge is started.
[0100]
As described above, as an embodiment, an example in which the rising of the determination value S from OFF to ON is directly detected in the shift limit rewriting process and the stored contents of the shift limit state storage unit 3 is rewritten cyclically has been described. Separately from this, when the rising of ODS2 from OFF to ON is detected, it is determined whether or not the determination value S is ON at that time, and only when the determination value S is OFF, the speed limit state is limited. It is good also as a structure which permits rewriting of the memory content of the memory | storage means 3. FIG.
[0101]
【The invention's effect】
The control device for an automatic transmission for an automobile according to the present invention employs a momentary switch as an overdrive kill switch, and every time a rising signal of the momentary switch is detected, the overdrive can be used or cannot be used. The speed limit is cyclically switched from the current state to the usable state, while a delay time is provided so that the falling of the momentary switch signal is larger, so overdrive kills can be caused by a driver's misoperation. Even when the switch is pressed twice or three times continuously, only the first operation is effective for rewriting the shift limit state, and the subsequent erroneous operation is performed. Does not affect the change of the speed limit state. Speed operation or the driver execution of unintended shifting operation is prevented.
In addition, as a result of the shifting operation not intended by the driver not being performed, the driver no longer has the illusion of the selection state of the shift stage, for example, in road conditions such as permitting the use of overdrive at the end of a downhill. Appropriate shift restrictions can be made accordingly, and the fuel efficiency of the vehicle is further improved.
In addition, since the first operation before being pushed twice is accurately detected without a time delay, the gear shifting operation intended by the driver is performed reliably. Deceleration by engine braking can be carried out reliably without delay.
[0102]
Furthermore, since the start of the ignition is detected and the shift limit indicating that overdrive can be used is written in the shift limit state storage means as the limit to be applied first, the shift limit at the time when the parking and stopping measures were performed last time Regardless of the state, at the start of the next operation, it is possible to implement a fuel-efficient operation using overdrive.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing the functions of a control device for an automatic transmission for an automobile to which the present invention is applied in a block form.
FIG. 2 is a block diagram showing a simplified connection relationship between an automatic transmission and an engine and a control device.
FIG. 3 is a flowchart showing an outline of initialization processing executed by the CPU of the control device;
FIG. 4 is a flowchart showing an outline of timer processing executed by the CPU of the control device.
FIG. 5 is a flowchart showing an outline of determination value setting processing executed by the CPU of the control device.
FIG. 6 is a flowchart showing an outline of a shift restriction rewriting process executed by a CPU of the control device.
FIG. 7 (a) is an example of a shift operation that occurs when an overdrive kill switch is pressed twice when the control device of this embodiment is applied to an automatic vehicle equipped with a 4-speed automatic transmission. The timing chart shown in FIG. 7 (b) shows the problem of the shifting operation that occurs when the overdrive kill switch is pressed twice when the control device of this embodiment is not applied to an automatic vehicle equipped with a 4-speed automatic transmission. 6 is a timing chart showing points.
[Explanation of symbols]
1 Automobile automatic transmission control device
2 Momentary switch (ODS)
3 Shift limit state storage means
4 Delay means
5 Shift limit state rewriting means
6 Initial setting means
7 Automatic transmission means
8 CPU
9 Automatic transmission
10 engine
11 Throttle opening sensor
12 Water temperature sensor
13 Rotation sensor
14 Input shaft rotation sensor
15 Shift position detection sensor
16 Drive shaft
17 Vehicle speed sensor
18 Brake operation detection sensor
SOL1 shift solenoid
SOL2 shift solenoid
SOL3 Lock-up solenoid

Claims (2)

A momentary switch for manually setting whether or not overdrive can be used; a shift limit state storing means for storing whether or not overdrive can be used; and An automatic transmission for an automobile, comprising: a shift limitation state rewriting unit that rewrites the stored contents cyclically; and an automatic transmission unit that selects a shift stage within a range of shift limitation stored in the shift limitation state storage unit A control device for an automatic transmission for an automobile, wherein a delay time is provided so that ON / OFF determination of the momentary switch is larger from ON to OFF than from OFF to ON. 2. An automobile setting device according to claim 1, wherein said shift restriction state rewriting means is provided with initial setting means for detecting activation of an ignition and writing a shift restriction for overdrive use in said shift restriction state storage means. Control device for automatic transmission.

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