JP3807470B2 - PLL circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL (Phase-Locked Loop) circuit applied to a disk device such as a CD-ROM.
[0002]
[Prior art]
The configuration of a conventional PLL circuit will be described with reference to FIG.
[0003]
In FIG. 5, 1 is a voltage-controlled oscillator, 2 is an EFM signal obtained by digitizing an analog signal read from a disk, 3 is a PCK signal that is an output clock of the voltage-controlled oscillator 1, 4 is a phase comparator, and 7 is a constant comparator. A current source, 9 is a filter circuit, 12 is a current correction circuit, and 13 is a switch. In this example, an example in which a charge pump is used as the constant current source 7 will be described.
[0004]
The EFM signal 2 and the PCK signal 3 are input to the phase comparator 4 for phase comparison of the signals. The phase comparator 4 outputs two signals, a signal for driving the Pch charge pump in the constant current source 7 and a signal for driving the Nch charge pump. If the Pch drive signal is L (Low), Pch is output. The charge pump is driven, and if the Nch drive signal is H (High), the Nch charge pump is driven. When the phase comparison is not performed, the Pch drive signal becomes H, the Nch drive signal becomes L, and the drive of the charge pump is stopped. The output current of the constant current source 7 driven by the phase comparison signal is converted into a voltage by using the filter circuit 9, and the voltage is input to the voltage controlled oscillator 1, whereby the PCK signal 3 synchronized with the EFM signal 2 is obtained. Is generated.
[0005]
The difference between the Pch charge pump current and the Nch charge pump current in the constant current source 7 is called an unbalance current, and the pull-in characteristics of the PLL deteriorate as the unbalance current amount increases. Therefore, in order to correct the unbalanced current, a current correction circuit 12 is provided, and a correction amount is set from the outside, and the switch 13 is turned on by the set value to perform correction.
[0006]
[Problems to be solved by the invention]
The PLL charge pump unbalance current amount is not necessarily the same, and is different for each LSI chip, for example. It also changes depending on the playback speed.
[0007]
However, since the conventional configuration can correct only a preset fixed amount of current correction, it cannot be completely corrected unless the amount of unbalanced current is within a certain range. For this reason, outside the correction range, the pull-in characteristics of the PLL are deteriorated, causing problems such as an error rate deterioration or an access failure.
[0008]
The present invention solves the above-described conventional problems, and provides a PLL circuit capable of automatically correcting a PLL unbalance current in order to always obtain optimum characteristics regardless of the value of the PLL unbalance current amount. The purpose is to do.
[0009]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a voltage controlled oscillator that generates an oscillation clock according to an input voltage, and a phase comparison that compares a phase difference between an input signal and the oscillation clock and outputs a phase comparison signal. Circuit, a constant current source driven by the phase comparison signal, and a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage controlled oscillator A counter for measuring the signal width of the phase comparison signal, and a current value control circuit for controlling the output current value of the constant current source according to the count value of the counter. The output current value of the constant current source is changed when the phase comparison signal is not output.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0011]
FIG. 1 is a block diagram of a PLL circuit for explaining an embodiment of the present invention. 1 is a voltage controlled oscillator, 2 is an EFM signal obtained by digitizing an analog signal read from a disk, and 3 is a voltage controlled oscillator 1. PCK signal, 4 is a phase comparator that compares the phases of the EFM signal and PCK signal and outputs a phase comparison signal, 5 is an offset addition circuit that adds an offset width to the phase comparison signal width, and 6 is an offset A counter for measuring the output signal width of the adder circuit 5; 7 a constant current source driven by the phase comparison signal; 8 a current value control circuit for controlling the output current of the constant current source 7 according to the count value of the counter 6; A filter circuit 9 converts the current output from the constant current source 7 into a voltage.
[0012]
The operation of the present embodiment having the above configuration will be described using an example in which a plurality of charge pumps (CP) are used as the constant current source 7 and an up / down counter is used as the counter 6.
[0013]
The EFM signal 2 and the PCK signal 3 are input to the phase comparator 4 for phase comparison of the signals. The phase comparator 4 outputs a Pch charge pump drive signal and an Nch charge pump drive signal as shown in FIG. The Pch charge pump drive signal is a signal that becomes L during the period from the detection of the edge of the EFM signal 2 to the rise of the second pulse of the PCK signal 3, and the Nch charge pump drive signal indicates the edge of the EFM signal 2. From the rising edge of the PCK signal 3 after detection to the rising edge of the next PCK signal 3, it is a signal that always becomes H during the interval of 1PCK.
[0014]
As for the charge pump current amount, the Nch charge pump current amount is set to 1.5 times the Pch charge pump current amount. Therefore, when there is no unbalanced current as shown in FIG. 2, the charge pump drive signal width is Pch: Nch = 1.5PCK: 1PCK, that is, the phases of the EFM signal 2 and the PCK signal 3 are matched. In the state, area A = area B, the current amount is balanced, and the PLL is locked.
[0015]
Next, the Pch charge pump drive signal and the Nch charge pump drive signal output from the phase comparator 4 are input to the offset addition circuit 5 and the constant current source 7. The offset addition circuit 5 adds a set value as an offset width to the Pch charge pump drive signal and the Nch charge pump drive signal in order to finely adjust the optimum position of the phase difference between the EFM signal and the PCK signal. The charge pump drive signal to which is added is output to the counter 6. When the offset width is not added, the same signal as the charge pump drive signal output from the phase comparator 4 is input to the counter 6.
[0016]
The counter 6 detects the difference between the Pch charge pump drive signal width and the Nch charge pump drive signal width, and counts up the width when both the Pch charge pump drive signal and the Nch charge pump drive signal are L. The width when the Nch charge pump drive signal is H is down-counted by 1/2 clock at the time of up-counting.
[0017]
As shown in FIG. 2, when Pch charge pump current: Nch charge pump current = 1: 1.5, that is, when there is no unbalance current, the Pch charge pump drive signal and the Nch charge pump drive signal are Since the ratio of the width when both are L and the width when the Nch charge pump drive signal is H is 1: 2, the value of the counter 6 becomes zero.
[0018]
As shown in FIG. 3, when the Pch charge pump current is larger than a desired value, assuming that the unbalance current is b, Pch charge pump current: Nch charge pump current = (1 + b): 1.5, and the PCK signal In a state where the phase of 3 has advanced, area A = area B and the PLL is locked. If the phase shift width at this time is a, the charge pump drive signal width is Pch: Nch = (1.5PCK−a): 1PCK, and the counter 6 takes a negative value.
[0019]
On the contrary, as shown in FIG. 4, when the Pch charge pump current is smaller than a desired value and Pch charge pump current: Nch charge pump current = (1-b): 1.5, the PCK signal 3 In a state where the phase is delayed, area A = area B and the PLL is locked. The charge pump drive signal width at this time is Pch: Nch = 1.5 (PCK + a): 1PCK, and the counter 6 takes a positive value.
[0020]
Then, each value of the counter 6 is input to the current value control circuit 8, and is output to the constant current source 7 at a timing when the phase comparison output is not output. The constant current source 7 is composed of a reference 100% charge pump and 1% and 2% charge pumps for current correction on the Pch side, and a combination of these can be used to correct current by 1 to 3%. It is. The Nch side is composed of a standard 150% charge pump and 1%, 2%, 4%, 8%, 16%, and 32% charge pumps for current correction. A current correction of 64% is possible.
[0021]
In both the Pch side and the Nch side, the reference charge pump is controlled only by the phase comparison signal. If the Pch drive signal is L, the Pch charge pump is driven, and if the Nch drive signal is H, Nch Drive the charge pump. When the phase comparison is not performed, the Pch drive signal becomes H, the Nch drive signal becomes L, and the drive of the charge pump is stopped. Other charge pumps for current correction are charge pumps that are turned on / off by the current value control circuit 8. The current correction charge pump has a current amount in units of 2n, and the current value control circuit 8 can obtain the current correction value by decoding the value of the counter 6.
[0022]
Thus, the output current amount of the constant current source 7 is determined by the value of the counter 6, this current is converted into a voltage by the filter circuit 9, and the PCK signal 3 is generated by using it as the input voltage of the voltage controlled oscillator 1. is doing. For example, when the counter 6 takes a negative value, the phase of the PCK signal 3 is advanced. Therefore, the Nch correction charge pump in the constant current source 7 is turned on, the Nch charge pump current is increased, and voltage control is performed. By lowering the input voltage of the type oscillator 1, the phase of the PCK signal 3 is delayed, and the EFM-PCK phase difference is controlled to the optimum position as shown in FIG. When the counter 6 takes a positive value, the phase of the PCK signal 3 is delayed. Therefore, the Pch correction charge pump in the constant current source 7 is turned on, the Pch charge pump current is increased, and voltage control is performed. By raising the input voltage of the type oscillator 1, the phase of the PCK signal 3 is advanced, and the phase difference between the EFM signal and the PCK signal is controlled to the optimum position as shown in FIG.
[0023]
In addition, when the PLL is disconnected due to access or the like, a normal EFM signal is not input, and thus phase comparison is not normally performed. In such a case, stop the count clock of the counter 6 and output the counter value before the PLL is released, or set the data of the counter 6 in advance and output the value to operate abnormally. prevent.
[0024]
In the present embodiment, when the PLL is disconnected, it has been described that the count value before the PLL is released or a preset value is output from the counter 6. However, instead of the counter 6, a value is supplied to the current value control circuit 8. Even if set and output, the same effect can be obtained.
[0025]
Further, the phase comparison method is not limited to the method used in this embodiment.
[0026]
【The invention's effect】
As described above, according to the present invention, it is not necessary to set a correction current value from the outside by automatically correcting the PLL charge pump unbalance current that is not necessarily the same, and the phase difference between the EFM signal and the PCK signal is reduced. Since it can be controlled to the optimum position, problems such as an error rate deterioration or an access failure can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a PLL circuit for explaining an embodiment of the present invention. FIG. 2 is a diagram showing a charge pump drive signal when a phase difference between an EFM signal and a PCK signal is an optimum position in the present embodiment. 3 is a diagram showing a charge pump drive signal when the phase difference between the EFM signal and the PCK signal is advanced in the present embodiment. FIG. 4 is a charge when the phase difference between the EFM signal and the PCK signal is delayed in the present embodiment. Diagram showing pump drive signal [Fig. 5] Configuration diagram of conventional PLL circuit [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Voltage-controlled oscillator 2 EFM signal 3 PCK signal 4 Phase comparator 5 Offset addition circuit 6 Counter 7 Constant current source 8 Current value control circuit 9 Filter circuit

Claims (3)

A voltage controlled oscillator that generates an oscillation clock according to an input voltage, a phase comparator that compares a phase difference between an input signal and the oscillation clock, and outputs a phase comparison signal, and a constant drive driven by the phase comparison signal A PLL circuit including a current source and a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage-controlled oscillator, wherein the signal width of the phase comparison signal is A counter for measuring, and a current value control circuit for controlling the output current value of the constant current source according to the count value of the counter . The current value control circuit outputs the constant current source when the phase comparison signal is not output. A PLL circuit characterized by changing a current value . 2. The PLL circuit according to claim 1 , wherein the counter stops measurement when the PLL is asynchronous . 2. The PLL circuit according to claim 1, wherein the counter or the current value control circuit outputs a preset value set in advance regardless of the count value when the PLL is asynchronous .

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