JP3807966B2 - Semiconductor device having self-alignment contact hole defect immediate detection function and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor defect detection mechanism, and more particularly, to a semiconductor device having a function of immediately detecting a defect of a self-aligned contact hole and a manufacturing method thereof.
[0002]
[Prior art]
What hinders the improvement of the integrated circuit packaging density and the reduction of the chip size is mainly the alignment error between the pattern layers. Therefore, a self-aligned contact (SAC) technique has been actively proposed as a measure for reducing the distance between elements and improving the integration density.
[0003]
However, while the size of the integrated circuit is reduced and the degree of integration is improved, the tolerance for defects may be reduced. Therefore, it is necessary to perform a process for improving defects in order to improve the yield rate in the manufacturing process.
[0004]
In general, the higher the yield rate, the lower the defect density. Therefore, it is common to perform a check at a predetermined stage in order to accurately grasp the defect state of the integrated circuit.
[0005]
In the self-aligned contact process, contact holes are formed by etching using sidewalls on both sides of the gate. As a result, when the contact holes are formed and the side walls on both sides of the gate are excessively etched to cause a short circuit, the reliability of the product may be greatly adversely affected and the yield rate may be reduced.
[0006]
However, since the reliability check of the semiconductor is usually performed after the metallization process, according to the conventional check method, it is impossible to detect a defect such as a circuit short circuit immediately after the formation of the defect of the self-aligned contact hole. Thus, even if the self-aligned contact hole defect is actually present, the subsequent manufacturing stage process continues. Therefore, there is a problem of wasting time and materials.
[0007]
[Problems to be solved by the invention]
In order to solve the above-described problems, a first object of the present invention is to detect a semiconductor device defect by an electrical characteristic check after forming a contact plug, that is, a self-aligned contact hole defect is detected. An object of the present invention is to provide a semiconductor device having a function that can be detected immediately.
[0008]
A second object of the present invention is to provide a manufacturing method for forming a semiconductor device having the above function in a normal manufacturing stage.
[0009]
Furthermore, a third object of the present invention is to provide a semiconductor device that has high sensitivity and quick detection, that is, a defect of a self-aligned contact hole / gate structure can be reliably detected.
[0010]
[Means for Solving the Problems]
The semiconductor device of the present invention for achieving the object, a semiconductor device formed on a semiconductor substrate, an active region formed on said semiconductor substrate, and at least two detection areas formed on the semiconductor substrate The active region includes a first gate distributed in a serpentine shape in the active region , a side wall formed on a side of the first serpentine gate, and the serpentine second gate. The region excluding the first gate in the active region is partitioned into two electrically insulated regions by one gate, and the semiconductor substrate in the two electrically isolated regions A contact region is formed, and an active region insulating layer is formed to cover the first gate, and the active region insulating layer has at least one first region on the first contact region. A contact hole is formed, a first contact plug is formed in the first contact hole, the first contact plug is connected to the first contact region, and the at least two detection regions include a plurality of contact holes. The semiconductor substrate in a region excluding the plurality of second gates in the at least two detection regions. A second contact region is formed, and a detection region insulating layer is formed in each of the detection regions so as to cover the plurality of second gates, and the detection region insulating layer includes the plurality of second contact regions. A second contact hole exposing the second gate is formed, a second contact plug is formed in the second contact hole, and the second contact plug is Connected to the second contact region, the second contact region in each of the detection regions, the two electrically respectively isolated regions electrically connected in the first contact region.
[0011]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: ( a ) providing a semiconductor substrate having an active region and two detection regions; and (b) distributing in a meandering manner in the active region. Forming a first gate, forming a sidewall on the side of the serpentine first gate, forming a plurality of second gates arranged in a matrix in each of the detection regions, Forming a sidewall on the side of the second gate, and (c) ion-implanting the entire surface of the semiconductor substrate in the active region and the detection region so that the first gate is formed in the active region. In the removed region, a first contact region including two electrically insulated regions partitioned by the serpentine first gate is formed, and a semiconductor substrate in each of the detection regions A second contact region electrically connected to each of the two electrically isolated regions in the first contact region in the region excluding the second gate; Forming an oxide layer entirely over the gate and the second gate; (d) in the active region, over the first contact region, over the first contact region; Forming at least one contact hole, and forming a second contact hole in the insulating layer to expose the second gate in the detection region; and ( e ) in the first contact hole. Forming a first contact plug, connecting to the first contact region, forming a second contact plug in the second contact hole, and connecting to the second contact region Consisting of.
[0012]
The shape of the second gate is not particularly limited, and may be a conventionally applied shape such as a rectangular parallelepiped shape or a columnar shape . The pattern of the plurality of second gates is not particularly limited, and may be arranged in a matrix, for example.
[0014]
The first gate and the second gate may be made of polycrystalline silicon.
[0015]
Further, the first contact plug and the second contact plug may be made of tungsten metal or polycrystalline silicon. The sidewall may be made of a dielectric material such as silicon nitride.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The configuration and operation of an embodiment of the present invention that accomplishes the above-described object and eliminates the drawbacks of the prior art will be described in detail with reference to the accompanying drawings.
[0017]
FIG. 1A is a plan view showing a semiconductor device according to the present invention. Active region 10 having a serpentine first gate 30 and a plurality of first contact hole 20 is divided into two regions that are electrically insulated from each other by said serpentine gate 30. Detection regions 40 and 50 are connected to both sides of the active region 10, respectively. These detection regions include a second contact hole 60 and a plurality of second gates 70 located at the bottom of the second contact hole 60.
[0018]
The serpentine first gate 30 of the active region 10 is not limited to the one having the pattern as shown in FIG. 1A, and may be any one that partitions the active region 10 into both regions that are electrically insulated . For example, it may be as shown in FIG. 1B. The shape of the second gate 70 is not limited to the rectangular parallelepiped shape shown in the figure, and may be, for example, a cylindrical shape .
[0019]
FIG. 2 is a sectional view taken along the line BB ′ of FIG. 1A and shows details of the active region. In FIG. 2, 100 is a semiconductor substrate on the active region side, and 103 is an oxide layer. The plurality of first contact holes 20 are located between two adjacent first gates 101. There are sidewalls 102 on both sides of the first gate 101. A portion of the active region 100 other than the first gate 101 is a first contact region 110 formed by ion implantation. Each first contact hole 20 is filled with a first contact plug 105.
[0020]
3 is a cross-sectional view taken along the line CC ′ of FIG. 1A. In FIG. 3, reference numeral 200 denotes a semiconductor substrate on the detection region side, 203 denotes an oxide layer, and 60 denotes a second contact hole as in FIG. A plurality of second gates 201 are formed at the bottom of the second contact hole 60, and sidewalls 202 are formed on both sides of each second gate 201. A portion other than the second gate 201 of the detection region 200 is a second contact region 210 by ion implantation. Each second contact hole 60 is filled with a second contact plug 204.
[0021]
By providing the plurality of second gates 201, the substrate is prevented from being damaged by the etching solution when forming the contact hole, and the contact hole having a large size cannot be completely filled when filling the subsequent tungsten metal or polycrystalline silicon. Thus, when checking the electrical characteristics, the voltage can be uniformly distributed in the detection region.
[0022]
The number and pattern of the second gates 201 in the detection region 200 are not particularly limited, and should be adjusted according to the number of first gates in the active region to be detected and the manufacturing conditions. However, in order to smoothly advance the manufacturing stage, it is preferable that the width of the first gate in the active region is the same as that of the second gate in the detection region.
[0023]
Hereinafter, a method for manufacturing the semiconductor as described above will be described in detail.
[0024]
4 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
[0025]
In this embodiment, it is assumed that the semiconductor device has an active region to be checked (detected) and at least two detection regions, and its manufacturing stage is performed simultaneously. In each figure, the left side of the disconnection is the active area AA, and the right side is the detection area PP (probe pad). Manufacturing steps are performed simultaneously in both these different regions.
[0026]
First, in FIG. 4, the active region side substrate 100 in which the meandering first gate 101 having the sidewall 102 is formed, and the detection region side substrate in which a plurality of second gates 201 having the sidewall 202 are formed. 200. Here, the sidewall 102 may be made of a dielectric material such as silicon nitride. Thereafter, the first contact region 110 and the second contact region 210 are formed by performing ion implantation (for example, N ⁺ ion implantation) on the active region side substrate 100 and the detection region side substrate 200. In the present embodiment, the first gate 101 of the active area AA bisects the active area as shown in FIG. 1A or 1B. On the other hand, the second gates 201 of the detection region PP are arranged in a 4 × 4 matrix (there are four gates in the horizontal and vertical directions). For this reason, four second gates 201 are shown in the cross section of the detection region PP in FIG.
[0027]
Next, in FIG. 5, oxide layers 103 and 203 are entirely formed over the substrates 100 and 200 so as to cover the serpentine first gate 101 and the plurality of second gates 201.
[0028]
Next, as shown in FIG. 6, the oxide layers 103 and 203 are etched using the sidewalls 102 and 202 on both sides of the gate as an etching mask, so that the active region side substrate 100 is exposed to be adjacent to each other in the active region AA. A plurality of first contact holes 20 are formed between the meandering first gates 101, and only about half of the second gates at both ends are exposed, and the other second gates 201 are exposed at all portions. Thus, the second contact hole 60 is formed in the detection region PP.
[0029]
Finally, as shown in FIG. 7, the plurality of first contact holes 20 in the active region AA and the second contact holes 60 in the detection region PP are filled with tungsten metal, and the first contact plug 105 and the second contact hole 60 are filled. Contact plug 204 is formed.
[0030]
Through each stage of the, Ru can be formed a semiconductor device having a function of defects of a self-aligned contact holes are detected immediately.
[0031]
During the manufacturing of the semiconductor, after performing each of the above-described steps, a ground and a voltage are applied to the detection regions formed on both sides of the semiconductor device, thereby detecting a defect with respect to the contact hole. In this case, if a current is detected, it is determined that the contact hole is defective because a short circuit occurs. The grounds for making such a determination are as follows.
[0032]
That is, in the semiconductor device according to the invention, the active region since it is divided into two areas you electrical isolation of circuit when the gate sides of the sidewalls over etched defects caused during the formation of the self-aligned contact hole A short circuit occurs . Therefore, when a short circuit occurs, current is always detected when the defect detection is performed.
[0033]
Although the present invention has been presented as in the foregoing embodiments, this is not intended to limit the present invention, and those skilled in the art can make variations and modifications within the spirit and scope of the present invention.
[0034]
【The invention's effect】
As described above, according to the present invention, it is possible to detect a defect of a semiconductor device, that is, a defect of a self-aligned contact hole and / or a gate by an electrical characteristic check immediately after forming a contact plug. Moreover, the semiconductor device according to the present invention has good sensitivity, and defect detection is performed promptly and reliably.
[Brief description of the drawings]
FIG. 1A is a plan view showing a semiconductor device of the present invention.
FIG. 1B is a diagram showing another example of an active region pattern by the defect detection structure of the present invention.
FIG. 2 is a cross-sectional view taken along line BB ′ of FIG. 1A.
FIG. 3 is a cross-sectional view taken along the line CC ′ of FIG. 1A.
FIG. 4 is a cross-sectional view showing a part of steps in the method for manufacturing a semiconductor device according to the embodiment of the invention.
5 is a cross-sectional view showing a step that follows the step shown in FIG. 4. FIG.
6 is a cross-sectional view showing a stage that follows the stage shown in FIG. 5. FIG.
7 is a cross-sectional view showing a stage that follows the stage shown in FIG. 6. FIG.
[Explanation of symbols]
10, AA active region 20 first contact hole 30, 101 first gate 40, 50, PP detection region 60 second contact hole 70, 201 second gate 100 active region side substrate 102, 202 sidewall 103 , 203 Oxide layer 105 First contact plug 110 First contact region 204 Second contact plug 210 Second contact region

Claims (13)

In a semiconductor device formed on a semiconductor substrate,
An active region formed in the semiconductor substrate;
And at least two detection regions formed on the semiconductor substrate,
In the active region, a first gate distributed in a serpentine shape is formed, and a sidewall is formed on a side of the serpentine first gate,
The meandering first gate divides the region of the active region excluding the first gate into two electrically insulated regions, and the semiconductor in the two electrically insulated regions. A first contact region is formed on the substrate;
An active region insulating layer is formed to cover the first gate;
In the active region insulating layer, at least one first contact hole is formed on the first contact region ,
A first contact plug is formed in the first contact hole , and the first contact plug is connected to the first contact region;
In the at least two detection regions , a plurality of second gates are formed, and side walls are formed on the side of each of the second gates,
A second contact region is formed in the semiconductor substrate in a region excluding the plurality of second gates in the at least two detection regions ;
In each of the detection regions, a detection region insulating layer is formed so as to cover the plurality of second gates,
A second contact hole exposing the plurality of second gates is formed in the detection region insulating layer,
A second contact plug is formed in the second contact hole, and the second contact plug is connected to the second contact region;
The second contact region in each of the detection regions is electrically connected to the two electrically isolated regions in the first contact region, respectively.
A semiconductor device . The semiconductor device according to claim 1 , wherein the second gate has a rectangular parallelepiped shape or a cylindrical shape . The semiconductor device according to claim 2 , wherein the plurality of second gates are arranged in a matrix. The semiconductor device according to any one of claims 1 to 3 wherein the first contact plug and a second contact plug is characterized in that it consists of tungsten or polycrystalline silicon. The semiconductor device according to any one of claims 1 to 4 wherein the first gate and the second gate is characterized in that it consists of polycrystalline silicon. The semiconductor device according to claim 1, wherein the sidewall is made of silicon nitride . (A) providing a semiconductor substrate having an active region and two detection regions ;
(B) A first gate distributed in a serpentine shape is formed in the active region , a sidewall is formed on a side of the serpentine first gate, and arranged in a matrix in each of the detection regions. Forming a plurality of second gates, and forming a sidewall on the side of each of the second gates ;
(C) subjecting the overall ion implantation against the semiconductor substrate definitive in the active region and the detection region, the region excluding the first gate in the active region is partitioned by the first gate of the serpentine to form the electrically isolated first contact region comprising two regions that, in the semiconductor substrate definitive in each of said detection region, a region except for the second gate, the first contact Forming a second contact region electrically connected to each of the two electrically isolated regions in the region, and covering the oxide layer over the first gate and the second gate. And forming into
(D) In the active region , at least one first contact hole is formed in the insulating layer on the first contact region, and in the detection region, the second insulating layer is formed in the second insulating layer. Forming a second contact hole exposing the gate of
(E) a first contact plug formed in the first contact hole, connected to the first contact region, the second contact plug formed in the second contact hole, the second And a step of connecting to the contact region of the semiconductor device . 8. The method of manufacturing a semiconductor device according to claim 7, wherein the second gate formed in the step (b) is a rectangular parallelepiped or a cylinder . 9. The method of manufacturing a semiconductor device according to claim 7, wherein the first contact plug and the second contact plug are made of tungsten metal or polycrystalline silicon. The method for manufacturing a semiconductor device according to claim 7, wherein the first gate and the second gate are made of polycrystalline silicon. The method for manufacturing a semiconductor device according to claim 7, wherein the sidewall is made of a dielectric material. 12. The method of manufacturing a semiconductor device according to claim 11 , wherein the dielectric material is silicon nitride. The method of manufacturing a semiconductor device according to claim 7, wherein the implanted ions in the step (c) are N ⁺ ions.

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