Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP3811447B2 - Semiconductor element storage package and semiconductor device using the same - Google Patents
[go: Go Back, main page]

JP3811447B2 - Semiconductor element storage package and semiconductor device using the same - Google Patents

Semiconductor element storage package and semiconductor device using the same Download PDF

Info

Publication number
JP3811447B2
JP3811447B2 JP2002375526A JP2002375526A JP3811447B2 JP 3811447 B2 JP3811447 B2 JP 3811447B2 JP 2002375526 A JP2002375526 A JP 2002375526A JP 2002375526 A JP2002375526 A JP 2002375526A JP 3811447 B2 JP3811447 B2 JP 3811447B2
Authority
JP
Japan
Prior art keywords
wiring conductor
semiconductor element
mass
terms
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002375526A
Other languages
Japanese (ja)
Other versions
JP2004207524A (en
Inventor
学 米倉
義信 澤
哲生 平川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002375526A priority Critical patent/JP3811447B2/en
Publication of JP2004207524A publication Critical patent/JP2004207524A/en
Application granted granted Critical
Publication of JP3811447B2 publication Critical patent/JP3811447B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Compositions Of Oxide Ceramics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は高周波の電気信号を送受信する半導体素子を収納する半導体素子収納用パッケージ、およびその半導体素子収納用パッケージを用いて成る半導体装置に関するものである。
【0002】
【従来の技術】
従来、電気信号を送受信する半導体素子を収容するための半導体素子収納用パッケージは、一般に、酸化アルミニウム質焼結体等の電気絶縁材料から成り、上面に半導体素子の搭載部が形成された基体と、タングステン、モリブデン、マンガン、銅、銀等の金属材料から成り、基体の半導体素子搭載部から下面にかけて被着導出された複数の入出力用配線導体(第1配線導体)およびグランド用配線導体と、この配線導体と電気的に接続するようにして基体の下面に形成された複数個のグランド用パッドおよび入出力用パッドと、基体の搭載部より上面もしくは側面にかけて導出されている出入力用配線導体(第2配線導体)と、この出入力用配線導体(第2配線導体)に一端が接続されるとともに他端が外部に導出されているコネクターとにより構成されている。
【0003】
かかる半導体素子収納用パッケージは、その搭載部に電気信号を送受信する半導体素子がAu−Snろう材あるいは半田等の接合材を介して搭載固定されるとともに、半導体素子の電極が入出力用配線導体(第1配線導体)、グランド用の配線導体および出入力用配線導体(第2配線導体)にボンディングワイヤや接続用リボン、半田等の導電性接続材を介して接続され、その後、必要に応じて蓋体等で半導体素子を封止することによって半導体装置となる。
【0004】
また前記半導体装置は基体の下面に形成されているグランド用パッドおよび入出力用パッドを外部電気回路基板の回路導体に半田バンプ等を介し接続させることによって内部に収容する半導体素子が外部電気回路に接続され、同時にコネクターに同軸ケーブル等を介し外部の通信装置等の外部機器を接続させることによって半導体素子と外部機器とが接続するようになっている。
【0005】
なお、前記半導体装置に使用されている半導体素子は複数の電気信号を合成して一つの電気信号に変換する、或いは一つの電気信号を分離して複数の電気信号に変換する機能を有しており、第1配線導体を介して入力される複数の周波数帯域が低い電気信号は半導体素子で合成されて一つの周波数帯域が高い電気信号となり、この周波数帯域の高い電気信号は第2配線導体を介してコネクターに伝送されるとともにコネクターより外部の通信装置等の外部機器に伝送され、またコネクターを介して外部機器より伝送された周波数帯域の高い電気信号は半導体素子で複数の周波数帯域が低い電気信号に変換され、各々の周波数帯域の低い電気信号は第1配線導体を介して外部電気回路に伝送されることとなる。
【0006】
【特許文献1】
特開2002−164466号公報
【0007】
【発明が解決しようとする課題】
しかしながら、近年、光通信や無線通信等の機器は電気信号が高周波領域に達するとともに、高速で伝送させることが要求されるようになってきており、従来の配線基板は基体を形成する酸化アルミニウム質焼結体の比誘電率が約10(室温、1MHz)と高いことから、基体に設けた第1配線導体、第2配線導体を伝わる電気信号の伝送速度が遅く、高周波の電気信号を高速で伝送させるという要求を満足させることができなかった。
【0008】
本発明は上記欠点に鑑み案出されたもので、その目的は配線導体に電気信号を高速で伝送させることを可能とするとともに内部に収容する半導体素子を外部電気回路に確実に接続することができる半導体素子収納用パッケージおよびそれを用いた半導体装置を提供することにある。
【0009】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、40GHz〜80GHzの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第1配線導体と、前記基体の下面に形成され、前記グランド配線導体および第1配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第2配線導体と、前記基体における前記第2配線導体が形成された面と側面との間の角部に形成された切欠きに嵌め込まれるように取着され、前記第2配線導体に電気的に接続されているコネクターとから成り、前記基体が、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成されていることを特徴とするものである。
【0010】
また本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、40GHz〜80GHzの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第1配線導体および第2配線導体に電気的に接続したことを特徴とするものである。
【0011】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、パッケージの基体を、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成し、かかる焼結体の比誘電率が約6(室温、1MHz)と低いことから、基体に形成される第1配線導体、第2配線導体を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【0012】
【発明の実施の形態】
次に、本発明を添付図面に基づき詳細に説明する。
【0013】
図1は本発明の半導体素子収納用パッケージの一実施例を示し、1は基体、2aは第1配線導体、2bはグランド配線導体、3aは入出力用パッド、3bはグランド用パッド、4は第2配線導体、5はコネクターである。これら基体1、第1配線導体2a、グランド配線導体2b、入出力用パッド3a、グランド用パッド3b、第2配線導体4およびコネクター5により半導体素子6を収納するための半導体素子収納用パッケージ7が基本的に構成される。
【0014】
前記基体1は、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成されており、その上面に半導体素子6を搭載するための搭載部1aを有し、該搭載部1aに半導体素子6がガラス、樹脂、ロウ材等の接着剤を介して接着固定される。
【0015】
前記基体1は、例えば、SiO2、BaO、B23、Al23、CaO等の原料粉末に有機バインダーを添加混合して原料粉末を調整するとともに、これをドクターブレード法や圧延法、プレス金型法により所定形状に成形して成形体を得、しかる後、前記成形体を800℃〜1000℃の温度で焼成することによって製作される。
【0016】
また前記基体1は、半導体素子の搭載部1aから下面にかけて複数個の第1配線導体2aおよびグランド配線導体2bが形成されており、該各配線導体2a、2bは半導体素子6の電気信号入出力用、接地用の各電極を、入出力用パッド3aやグランド用パッド3bに接続するための導電路として作用し、搭載部1a側の一端には半導体素子6の電気信号入出力用、接地用の各電極が導電性接続材を介して電気的に接続される。
【0017】
前記第1配線導体2aおよびグランド配線導体2b、入出力用パッド3aおよびグランド用パッド3bは、銅、銀、金、パラジウム等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体1となるセラミックグリーンシートの表面に所定パターンに印刷しておくことによって形成される。
【0018】
この第1配線導体2aおよびグランド配線導体2bの基体1下面側の一端は、それぞれ対応する入出力用パッド3aおよびグランド用パッド3bと電気的に接続しており、これらの入出力用パッド3a、グランド用パッド3bを外部電気回路の所定の信号用や接地用等の回路導体に接続することにより、半導体素子6の電気信号入出力用、接地用の各電極が外部電気回路と電気的に接続される。
【0019】
また前記基体1は、半導体素子の搭載部1aから上面や側面等にかけて第2配線導体4が形成されており、該第2配線導体4は半導体素子6の電極をコネクター5に接続するための導電路として作用し、搭載部1a側の一端には半導体素子6の電極が導電性接続材8を介して電気的に接続される。
【0020】
前記第2配線導体4は、上述の第1配線導体2a等と同様に、銅、銀、金、パラジウム等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体1となるセラミックグリーンシートの表面に所定パターンに印刷しておくことにより形成される。
【0021】
この第2配線導体4の基体1外表面側の一端はコネクター5と電気的に接続しており、このコネクター5を同軸ケーブル等を介して通信装置等の外部機器に接続することにより半導体素子6と外部機器との間で高周波信号の送受信が行われる。
【0022】
前記コネクター5は、半導体素子収納用パッケージ7の第2配線導体4を同軸ケーブル等を介して外部機器に接続するための接続体として作用し、例えば、鉄−ニッケル−コバルト等の金属の線材の周囲を、ホウ珪酸系ガラス等の絶縁体で取り囲んだ構造である。
【0023】
かくして上述の半導体素子収納用パッケージによれば、基体1の搭載部1aに半導体素子6を搭載するとともに、ガラス、樹脂、ロウ材等の接着剤を介して固定し、しかる後、半導体素子6の各電極を第1配線導体2aおよびグランド配線導体2bに例えばボンディングワイヤ8を介して接続し、最後に蓋体10を基体1上面に封止材を介して接合させ、半導体素子6を気密に封止することによって半導体装置11となる。
【0024】
この半導体装置11は、基体1下面の入出力用パッド3aおよびグランド用パッド3bが外部電気回路基板の所定の信号用や接地用等の回路導体に半田バンプ等の外部端子を介して接続され、これによって半導体素子6の信号用、接地用の各電極は外部電気回路と電気的に接続される。
【0025】
また、この半導体装置11に取着されているコネクター5に同軸ケーブル等の外部接続用の導線を接続することにより、半導体素子6の電極が通信装置等の外部機器に接続される。
【0026】
そしてかかる半導体装置11は、外部電気回路から供給される複数の周波数帯域が低い(5〜10GHz)電気信号を第1配線導体2aを介して半導体素子6に入力させ、半導体素子6でこれら入力された電気信号を合成して、一つの周波数帯域が高い(40〜80GHz)電気信号とするとともにこれを第2配線導体4を介してコネクター5に出力し、該コネクター5を介して外部の通信装置等の外部機器に伝送する、或いは、外部の通信装置等の外部機器から伝送された一つの周波数帯域が高い(40〜80GHz)電気信号をコネクター5及び第2配線導体4を介して半導体素子6に入力し、半導体素子6で入力された周波数帯域が高い(40〜80GHz)電気信号を複数の周波数帯域が低い(5〜10GHz)電気信号に変換するとともに、これらの個々の周波数帯域が低い電気信号を第1配線導体2aを介して外部電気回路に供給することとなる。
【0027】
本発明の半導体素子収納用パッケージおよびこれを用いた半導体装置においては、基体1をSi成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成しておくことが重要である。
【0028】
前記基体1を、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成すると、かかる焼結体の比誘電率が約6(室温、1MHz)と低いことから基体1に形成される第1配線導体2a、第2配線導体4を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【0029】
また上述の焼結体はその焼成温度が800℃〜1000℃と低いことから、基体1と同時焼成により形成される第1配線導体2a等を比抵抗が2.5Ω・cm(20℃)以下と低い銅や銀、金で形成することができ、その結果、第1配線導体2a等に高周波の電気信号を伝送させた場合、電気信号に大きな減衰が生じることはなく、電気信号を正確かつ確実に伝送させることも可能となる。
【0030】
なお、前記基体1を構成するSi成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体は、SiO2の量が25質量%未満であると誘電損失が大きくなって第1配線導体2aや第2配線導体4を伝送する電気信号に減衰や遅延を招来してしまい、また80質量%を超えると基体1の機械的強度が大きく低下してしまうと同時に焼成温度が高いものとなって銅等の金属材料から成る第1配線導体2a等と同時焼成するのが困難となる。したがって、SiO2の量は25乃至80質量%の範囲に特定される。
【0031】
また、BaOが15質量%未満であると焼成温度が高いものとなって銅等の金属材料から成る第1配線導体2a等と同時焼成するのが困難となる。また70質量%を超えると誘電損失が大きくなって第1配線導体2aや第2配線導体4を伝送する電気信号に減衰や遅延を招来してしまう。したがって、BaOの量は15乃至70質量%の範囲に特定される。
【0032】
更に、B23が1.5質量%未満となると焼成温度が高いものとなって銅等の金属材料から成る第1配線導体2a等と同時焼成するのが困難となり、また5質量%を超えると基体1の機械的強度が大きく低下してしまう。したがって、B23の量は1.5乃至5質量%の範囲に特定される。
【0033】
また更に、Al23が1質量%未満となると焼成温度が高いものとなって銅等の金属材料から成る第1配線導体2a等と同時焼成するのが困難となり、また30質量%を超えると誘電損失が大きくなって第1配線導体2aや第2配線導体4を伝送する電気信号に減衰や遅延を招来してしまう。したがって、Al23の量は1乃至30質量%の範囲に特定される。
【0034】
更にまたCaOが30質量%を超えると焼成温度が高いものとなって銅等の金属材料から成る第1配線導体2a等と同時焼成するのが困難となる。したがって、CaOの量は0質量%を超えて30質量%以下の範囲に特定される。
【0035】
前記焼結体から成る基体1は、例えば、SiO2、BaO、B23、Al23、CaO等の原料粉末にアクリル樹脂を主成分とするバインダー及び分散剤、可塑剤、有機溶媒を加えて泥漿物を作るとともに該泥漿物をドクターブレード法やカレンダーロール法を採用することによってグリーンシートとなし、しかる後、前記グリーンシートに適当な打ち抜き加工を施すとともにこれを複数枚積層し、約800℃〜1000℃の温度で焼成することによって製作される。
【0036】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【0037】
【発明の効果】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、パッケージの基体を、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成し、かかる焼結体の比誘電率が約6(室温、1MHz)と低いことから、基体に形成される第1配線導体、第2配線導体を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージおよびこの半導体素子収納用パッケージを用いた半導体装置の一実施例を示す断面図である。
【符号の説明】
1・・・・・基体
1a・・・・搭載部
2a・・・・第1配線導体
2b・・・・グランド配線導体
3a・・・・入出力用パッド
3b・・・・グランド用パッド
4・・・・・第2配線導体
5・・・・・コネクター
6・・・・・半導体素子
7・・・・・半導体素子収納用パッケージ
8・・・・・ボンディングワイヤ
10・・・・蓋体
11・・・・半導体装置
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element storage package for storing a semiconductor element that transmits and receives a high-frequency electrical signal, and a semiconductor device using the semiconductor element storage package.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a package for housing a semiconductor element for housing a semiconductor element that transmits and receives an electrical signal is generally made of an electrically insulating material such as an aluminum oxide sintered body, and a base having a semiconductor element mounting portion formed on an upper surface thereof. A plurality of input / output wiring conductors (first wiring conductors) and ground wiring conductors that are made of a metal material such as tungsten, molybdenum, manganese, copper, silver, etc. , A plurality of ground pads and input / output pads formed on the lower surface of the base so as to be electrically connected to the wiring conductor, and input / output wiring led out from the mounting portion of the base to the upper surface or the side surface A conductor (second wiring conductor) and a connector having one end connected to the input / output wiring conductor (second wiring conductor) and the other end led to the outside; It is more configuration.
[0003]
In such a package for housing a semiconductor element, a semiconductor element that transmits and receives an electrical signal is mounted and fixed to the mounting portion via a bonding material such as an Au—Sn brazing material or solder, and the electrode of the semiconductor element is an input / output wiring conductor. (First wiring conductor), ground wiring conductor and input / output wiring conductor (second wiring conductor) are connected to each other through a conductive connecting material such as a bonding wire, a connecting ribbon, and solder. Then, a semiconductor device is obtained by sealing the semiconductor element with a lid or the like.
[0004]
In the semiconductor device, a ground pad and an input / output pad formed on the lower surface of the base are connected to a circuit conductor of an external electric circuit board through a solder bump or the like, so that a semiconductor element accommodated in the semiconductor device is an external electric circuit. At the same time, an external device such as an external communication device is connected to the connector via a coaxial cable or the like, so that the semiconductor element and the external device are connected.
[0005]
The semiconductor element used in the semiconductor device has a function of synthesizing and converting a plurality of electric signals into one electric signal, or separating one electric signal into a plurality of electric signals. In addition, a plurality of low frequency band electrical signals input through the first wiring conductor are combined by the semiconductor element to become one high frequency frequency electrical signal. The high frequency band electrical signal passes through the second wiring conductor. The high frequency signal transmitted from the connector to the external device such as an external communication device is transmitted from the connector to the external device such as a communication device. The signals are converted into signals, and the electric signals having low frequency bands are transmitted to the external electric circuit via the first wiring conductor.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-164466
[Problems to be solved by the invention]
However, in recent years, devices such as optical communication and wireless communication have come to be required to transmit electric signals at a high speed as the electric signal reaches a high frequency region. Conventional wiring boards are made of an aluminum oxide material that forms a base. Since the relative permittivity of the sintered body is as high as about 10 (room temperature, 1 MHz), the transmission speed of the electric signal transmitted through the first wiring conductor and the second wiring conductor provided on the base is low, and the high-frequency electric signal is transmitted at high speed. The request for transmission could not be satisfied.
[0008]
The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to enable an electrical signal to be transmitted at high speed to a wiring conductor and to securely connect a semiconductor element accommodated in an external electrical circuit. An object of the present invention is to provide a semiconductor element storage package and a semiconductor device using the same.
[0009]
[Means for Solving the Problems]
A package for housing a semiconductor element according to the present invention includes a base having a mounting portion on which a semiconductor element for transmitting and receiving an electrical signal of 40 GHz to 80 GHz is mounted, and a plurality of ground wirings extending from the mounting portion to the lower surface of the base A plurality of ground pads and input / output pads formed on a lower surface of the base body and electrically connected to the ground wiring conductor and the first wiring conductor; and mounting the base body The second wiring conductor led out from the upper part to the upper surface or the side surface, and attached so as to be fitted into a notch formed in a corner portion between the surface and the side surface of the base on which the second wiring conductor is formed. is composed of a connector that is electrically connected to the second wiring conductor, said substrate, 25 to 80 wt% Si component in terms of SiO 2, Ba Min 15 to 70 wt% in terms of BaO, 1.5 to 5 wt% B component in terms of B 2 O 3, 1 to 30 wt% Al component in terms of Al 2 O 3, Ca The component is formed of a sintered body containing more than 0% by mass and 30% by mass or less in terms of CaO.
[0010]
The semiconductor device according to the present invention includes a package for housing a semiconductor element configured as described above and a semiconductor element that transmits and receives an electrical signal of 40 GHz to 80 GHz. The semiconductor element is mounted and fixed on the mounting portion of the package, and Each electrode is electrically connected to the first wiring conductor and the second wiring conductor.
[0011]
According to the semiconductor element storage package and the semiconductor device of the present invention, the base of the package is 25 to 80% by mass in terms of Si component converted to SiO 2 and 15 to 70% by mass in terms of Ba component converted to BaO. The component is 1.5 to 5% by mass in terms of B 2 O 3 , the Al component is in the range of 1 to 30% by mass in terms of Al 2 O 3 , and the Ca component is in excess of 0% by mass in terms of CaO. It is formed of a sintered body that is contained by mass% or less, and since the relative dielectric constant of the sintered body is as low as about 6 (room temperature, 1 MHz), electricity transmitted through the first wiring conductor and the second wiring conductor formed on the base body. The signal transmission speed can be made extremely fast.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
[0013]
FIG. 1 shows an embodiment of a package for housing a semiconductor device according to the present invention. Reference numeral 1 denotes a base, 2a denotes a first wiring conductor, 2b denotes a ground wiring conductor, 3a denotes an input / output pad, 3b denotes a ground pad, The second wiring conductor 5 is a connector. A semiconductor element housing package 7 for housing the semiconductor element 6 by the substrate 1, the first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, the ground pad 3b, the second wiring conductor 4 and the connector 5 is provided. Basically composed.
[0014]
In the substrate 1, the Si component is converted to SiO 2 by 25 to 80% by mass, the Ba component is converted to BaO by 15 to 70% by mass, and the B component is converted to B 2 O 3 by 1.5 to 5%. It is formed of a sintered body containing 1 to 30% by mass in terms of mass%, Al component in terms of Al 2 O 3, and containing 0% by mass to less than 30% by mass in terms of Ca component in terms of CaO. A mounting portion 1a for mounting the semiconductor element 6 is provided on the upper surface, and the semiconductor element 6 is bonded and fixed to the mounting portion 1a through an adhesive such as glass, resin, or brazing material.
[0015]
The substrate 1 is prepared by adding an organic binder to a raw material powder such as SiO 2 , BaO, B 2 O 3 , Al 2 O 3 , and CaO to adjust the raw material powder. The molded body is obtained by molding into a predetermined shape by a press die method, and then the molded body is fired at a temperature of 800 ° C. to 1000 ° C.
[0016]
The base body 1 is formed with a plurality of first wiring conductors 2a and ground wiring conductors 2b from the semiconductor element mounting portion 1a to the lower surface, and the wiring conductors 2a and 2b are connected to the electric signal input / output of the semiconductor element 6, respectively. Each of the electrodes for grounding and grounding acts as a conductive path for connecting to the input / output pad 3a and the grounding pad 3b. These electrodes are electrically connected through a conductive connecting material.
[0017]
The first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, and the ground pad 3b are made of a metal material such as copper, silver, gold, or palladium. A metal paste formed by adding an organic solvent or the like is formed by printing a predetermined pattern on the surface of the ceramic green sheet serving as the substrate 1.
[0018]
One end of the first wiring conductor 2a and the ground wiring conductor 2b on the lower surface side of the base 1 is electrically connected to the corresponding input / output pad 3a and ground pad 3b, respectively. By connecting the ground pad 3b to a predetermined signal or ground circuit conductor of the external electric circuit, the electric signal input / output and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit. Is done.
[0019]
The base 1 has a second wiring conductor 4 formed from the semiconductor element mounting portion 1 a to the upper surface, side surface, and the like. The second wiring conductor 4 is a conductive material for connecting the electrode of the semiconductor element 6 to the connector 5. The electrode of the semiconductor element 6 acts as a path, and is electrically connected to one end on the mounting portion 1a side via the conductive connecting material 8.
[0020]
The second wiring conductor 4 is made of a metal material such as copper, silver, gold, or palladium, like the first wiring conductor 2a described above. For example, if the second wiring conductor 4 is made of copper, an organic solvent or the like is added to the copper powder. The added metal paste is formed by printing a predetermined pattern on the surface of the ceramic green sheet to be the base 1.
[0021]
One end of the second wiring conductor 4 on the outer surface side of the base body 1 is electrically connected to a connector 5, and the semiconductor element 6 is obtained by connecting the connector 5 to an external device such as a communication device via a coaxial cable or the like. High-frequency signals are transmitted and received between the device and the external device.
[0022]
The connector 5 acts as a connection body for connecting the second wiring conductor 4 of the semiconductor element storage package 7 to an external device via a coaxial cable or the like. For example, the connector 5 is made of a metal wire such as iron-nickel-cobalt. The structure is surrounded by an insulator such as borosilicate glass.
[0023]
Thus, according to the above-described package for housing a semiconductor element, the semiconductor element 6 is mounted on the mounting portion 1a of the base body 1 and fixed through an adhesive such as glass, resin, brazing material, and then the semiconductor element 6 is mounted. Each electrode is connected to the first wiring conductor 2a and the ground wiring conductor 2b via, for example, a bonding wire 8. Finally, the lid 10 is bonded to the upper surface of the base body 1 with a sealing material, and the semiconductor element 6 is hermetically sealed. By stopping, the semiconductor device 11 is obtained.
[0024]
In this semiconductor device 11, input / output pads 3a and ground pads 3b on the lower surface of the substrate 1 are connected to predetermined signal or ground circuit conductors of an external electric circuit board via external terminals such as solder bumps. As a result, the signal and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit.
[0025]
Further, by connecting an external connection conductor such as a coaxial cable to the connector 5 attached to the semiconductor device 11, the electrode of the semiconductor element 6 is connected to an external device such as a communication device.
[0026]
The semiconductor device 11 inputs a plurality of low frequency band (5 to 10 GHz) electric signals supplied from an external electric circuit to the semiconductor element 6 through the first wiring conductor 2a, and these are input by the semiconductor element 6. The electrical signal is synthesized into an electrical signal having a high frequency band (40 to 80 GHz) and output to the connector 5 via the second wiring conductor 4, and an external communication device via the connector 5. The semiconductor element 6 transmits an electrical signal having a high frequency band (40 to 80 GHz) transmitted from an external device such as an external communication device via the connector 5 and the second wiring conductor 4. Is converted into an electrical signal having a high frequency band (40 to 80 GHz) and a plurality of low frequency bands (5 to 10 GHz). Both, so that these individual frequency band is supplied to an external electrical circuit through the first wiring conductor 2a low electrical signal.
[0027]
In the package for housing a semiconductor element and the semiconductor device using the same according to the present invention, the substrate 1 has a Si component converted to SiO 2 of 25 to 80% by mass, a Ba component converted to BaO of 15 to 70% by mass, B component is 1.5 to 5% by mass in terms of B 2 O 3 , Al component is in the range of 1 to 30% by mass in terms of Al 2 O 3 , and Ca component is in excess of 0% by mass in terms of CaO. It is important to form the sintered body that is contained in an amount of 30% by mass or less.
[0028]
In the substrate 1, the Si component is converted to SiO 2 in the range of 25 to 80% by mass, the Ba component in terms of BaO in the range of 15 to 70% by mass, and the B component in the range of B 2 O 3 of 1.5 to 5%. mass%, 1 to 30 wt% Al component in terms of Al 2 O 3, to form a sintered body Ca component contained 30 wt% or less than 0 wt% in terms of CaO, such sintering Since the relative dielectric constant of the body is as low as about 6 (room temperature, 1 MHz), the transmission speed of the electrical signal transmitted through the first wiring conductor 2a and the second wiring conductor 4 formed on the base body 1 can be extremely high. .
[0029]
Moreover, since the above-mentioned sintered body has a low firing temperature of 800 ° C. to 1000 ° C., the specific resistance of the first wiring conductor 2a and the like formed by simultaneous firing with the substrate 1 is 2.5 Ω · cm (20 ° C.) or less. As a result, when a high-frequency electrical signal is transmitted to the first wiring conductor 2a or the like, the electrical signal is not greatly attenuated, and the electrical signal can be accurately and accurately formed. It is also possible to ensure transmission.
[0030]
The Si component constituting the substrate 1 is 25 to 80% by mass in terms of SiO 2 , the Ba component is in terms of BaO and 15 to 70% by mass, and the B component is in terms of B 2 O 3 . A sintered body containing 5 to 5% by mass, 1 to 30% by mass in terms of Al component in terms of Al 2 O 3 , and 0 to 30% by mass in terms of Ca component in terms of CaO is SiO 2 If the amount is less than 25% by mass, the dielectric loss increases, leading to attenuation or delay in the electrical signal transmitted through the first wiring conductor 2a and the second wiring conductor 4, and if the amount exceeds 80% by mass, the substrate The mechanical strength of 1 is greatly reduced, and at the same time, the firing temperature becomes high, and it becomes difficult to fire simultaneously with the first wiring conductor 2a made of a metal material such as copper. Therefore, the amount of SiO 2 is specified in the range of 25 to 80% by mass.
[0031]
Further, when BaO is less than 15% by mass, the firing temperature becomes high and it is difficult to fire simultaneously with the first wiring conductor 2a made of a metal material such as copper. On the other hand, if it exceeds 70% by mass, the dielectric loss becomes large, and the electrical signal transmitted through the first wiring conductor 2a or the second wiring conductor 4 is attenuated or delayed. Therefore, the amount of BaO is specified in the range of 15 to 70% by mass.
[0032]
Further, if B 2 O 3 is less than 1.5% by mass, the firing temperature becomes high, and it becomes difficult to co-fire with the first wiring conductor 2a made of a metal material such as copper, and 5% by mass. If it exceeds, the mechanical strength of the substrate 1 is greatly reduced. Therefore, the amount of B 2 O 3 is specified in the range of 1.5 to 5% by mass.
[0033]
Furthermore, if the Al 2 O 3 content is less than 1% by mass, the firing temperature becomes high, making it difficult to co-fire with the first wiring conductor 2a made of a metal material such as copper, and exceeding 30% by mass. As a result, the dielectric loss increases and the electrical signals transmitted through the first wiring conductor 2a and the second wiring conductor 4 are attenuated or delayed. Therefore, the amount of Al 2 O 3 is specified in the range of 1 to 30% by mass.
[0034]
Furthermore, if CaO exceeds 30% by mass, the firing temperature becomes high and it is difficult to fire simultaneously with the first wiring conductor 2a made of a metal material such as copper. Therefore, the amount of CaO is specified in the range of more than 0% by mass and 30% by mass or less.
[0035]
The substrate 1 made of the sintered body includes, for example, a binder and a dispersant, a plasticizer, and an organic solvent mainly composed of an acrylic resin in a raw material powder such as SiO 2 , BaO, B 2 O 3 , Al 2 O 3 , and CaO. Is added to the green sheet by adopting a doctor blade method and a calendar roll method, and then, the green sheet is appropriately punched and laminated in a plurality of layers. It is manufactured by firing at a temperature of about 800 ° C to 1000 ° C.
[0036]
In addition, this invention is not limited to the above-mentioned Example, A various change is possible if it is a range which does not deviate from the summary of this invention.
[0037]
【The invention's effect】
According to the semiconductor element storage package and the semiconductor device of the present invention, the base of the package is 25 to 80% by mass in terms of Si component converted to SiO 2 and 15 to 70% by mass in terms of Ba component converted to BaO. The component is 1.5 to 5% by mass in terms of B 2 O 3 , the Al component is in the range of 1 to 30% by mass in terms of Al 2 O 3 , and the Ca component is in excess of 0% by mass in terms of CaO. It is formed of a sintered body that is contained by mass% or less, and since the relative dielectric constant of the sintered body is as low as about 6 (room temperature, 1 MHz), electricity transmitted through the first wiring conductor and the second wiring conductor formed on the base body. The signal transmission speed can be made extremely fast.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package and a semiconductor device using the semiconductor element housing package of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base 1a ... Mounting part 2a ... 1st wiring conductor 2b ... Ground wiring conductor 3a ... Input / output pad 3b ... Ground pad 4 2nd wiring conductor 5 Connector 6 Semiconductor element 7 Package 8 for storing semiconductor element Bonding wire 10 Lid 11 .... Semiconductor devices

Claims (2)

40GHz〜80GHzの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第1配線導体と、前記基体の下面に形成され、前記グランド配線導体および第1配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第2配線導体と、前記基体における前記第2配線導体が形成された面と側面との間の角部に形成された切欠きに嵌め込まれるように取着され、前記第2配線導体に電気的に接続されているコネクターとから成り、前記基体が、Si成分がSiO2に換算して25乃至80質量%、Ba成分がBaOに換算して15乃至70質量%、B成分がB23に換算して1.5乃至5質量%、Al成分がAl23に換算して1乃至30質量%、Ca成分がCaOに換算して0質量%を超えて30質量%以下含まれる焼結体で形成されていることを特徴とする半導体素子収納用パッケージ。A base having a mounting portion on which a semiconductor element for transmitting and receiving electrical signals of 40 GHz to 80 GHz is mounted; a plurality of ground wiring conductors and first wiring conductors extending from the mounting portion to a lower surface of the base; and the base A plurality of ground pads and input / output pads that are electrically connected to the ground wiring conductor and the first wiring conductor, and are led out from the mounting portion of the base body to the upper surface or the side surface. The second wiring conductor is attached so as to be fitted into a notch formed in a corner portion between the side surface of the base on which the second wiring conductor is formed, and is electrically connected to the second wiring conductor. consists of a connector that is connected to the substrate, 25 to 80 wt% Si component in terms of SiO 2, 15 to 70 wt Ba component in terms of BaO Greater than B component B 2 O 3 1.5 to 5 wt% in terms of, 1 to 30 wt% Al component in terms of Al 2 O 3, Ca component 0 mass% in terms of CaO A package for housing a semiconductor element, wherein the package is formed of a sintered body that is contained in an amount of 30% by mass or less. 請求項1に記載の半導体素子収納用パッケージと、40GHz〜80GHzの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第1配線導体および第2配線導体に電気的に接続したことを特徴とする半導体装置。A package for housing a semiconductor element according to claim 1, and a semiconductor element for transmitting and receiving an electrical signal of 40 GHz to 80 GHz. A semiconductor device, wherein the semiconductor device is electrically connected to a wiring conductor and a second wiring conductor.
JP2002375526A 2002-12-25 2002-12-25 Semiconductor element storage package and semiconductor device using the same Expired - Fee Related JP3811447B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002375526A JP3811447B2 (en) 2002-12-25 2002-12-25 Semiconductor element storage package and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002375526A JP3811447B2 (en) 2002-12-25 2002-12-25 Semiconductor element storage package and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JP2004207524A JP2004207524A (en) 2004-07-22
JP3811447B2 true JP3811447B2 (en) 2006-08-23

Family

ID=32813234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002375526A Expired - Fee Related JP3811447B2 (en) 2002-12-25 2002-12-25 Semiconductor element storage package and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP3811447B2 (en)

Also Published As

Publication number Publication date
JP2004207524A (en) 2004-07-22

Similar Documents

Publication Publication Date Title
JP3811447B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3780514B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3847247B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3722793B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3847239B2 (en) Semiconductor device
JP3847248B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3847249B2 (en) Semiconductor device
JP3847237B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3808423B2 (en) Semiconductor element storage package and semiconductor device using the same
JP2004207523A (en) Semiconductor element storage package and semiconductor device using the same
JP4291113B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3722796B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3847236B2 (en) Semiconductor element storage package and semiconductor device using the same
JP3847250B2 (en) Mounting structure of semiconductor device
JP3811460B2 (en) Semiconductor device
JP3811459B2 (en) Semiconductor device
JP2005019729A (en) Semiconductor element storage package and semiconductor device using the same
JP4077769B2 (en) Semiconductor device
JP4303564B2 (en) Semiconductor device
JP2004259769A (en) Semiconductor device
JP3679090B2 (en) Semiconductor device
JP3808421B2 (en) Semiconductor element storage package and semiconductor device using the same
JP4002540B2 (en) Semiconductor device
JP2004172298A (en) Semiconductor element storage package and semiconductor device using the same
JP2004158573A (en) Semiconductor element storage package and semiconductor device using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040924

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051017

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060421

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060523

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060526

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090602

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100602

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110602

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees