JP3825874B2 - Frequency conversion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a frequency variable circuit, particularly used in a wireless transceiver for handling high-frequency signals such as quasi-microwave band, about the configuration of an integrated circuit frequency converter.
[0002]
[Prior art]
As a frequency conversion circuit for a high-frequency signal such as a quasi-microwave band, an integrated circuit (IC) using, for example, a dual-gate field effect transistor (FET-Field Effect Transistor) using a GaAs compound semiconductor is used. An example of the frequency conversion semiconductor integrated circuit is shown in FIG.
[0003]
In FIG. 3, a depletion mode FET 2 is formed in the integrated circuit unit 1, and a high-frequency signal source 5 is connected to a terminal 3 on the first gate side (lower side in the figure) of the FET 2 via an impedance matching circuit 4. The high-frequency signal source 5 has a resistor 6 shown as an internal impedance. On the other hand, a local oscillation signal source 9 is connected to a terminal 7 on the second gate side (upper side in the figure) of the FET 2 via an impedance matching circuit 8, and a resistor 10 shown in the figure is connected to the local oscillation signal source 9. Present as internal impedance.
[0004]
The terminal 12 on the drain side of the FET 2 is provided with an output terminal 14 via an impedance matching circuit 13 and a bias supply terminal 16 for supplying a DC bias voltage via an inductor 15. The inductor 15 functions as a high frequency cutoff choke coil, and is set to have a sufficiently high impedance in a high frequency range.
[0005]
A resistor 19 for setting the drain-bias current of the FET 2 is connected between the source side of the FET 2 and a terminal 18 for connection to the ground potential. A resistor 20 is connected to the gate, and a resistor 21 is connected to the second gate. The resistors 20 and 21 are provided to apply a predetermined DC bias voltage to the first gate and the second gate.
[0006]
In such an integrated circuit 1, since a bonding wire and a lead, which are IC package mounting members, are formed between the terminal 18 and the ground potential, there exists a parasitic inductance 23 as the sum of these inductance components. It will be. In order to reduce the impedance component generated by the presence of the parasitic inductance 23, a capacitor 24 is arranged in series with the parasitic inductance 23 between the source of the FET 2 and the ground potential.
[0007]
That is, in order to secure a gain (conversion gain) at the time of frequency conversion in the frequency conversion circuit, it is necessary to reduce the impedance between the source of the FET 2 and the ground potential at a required frequency. However, due to the presence of the parasitic inductance 23, an impedance component that becomes higher as the frequency becomes higher is generated. Therefore, a capacitor 24 is provided on the source side of the FET 2 so as to obtain a low impedance characteristic.
[0008]
The capacitor 24 has a large capacity in order to obtain a low impedance characteristic in a wide band in frequency conversion. For example, a capacitor using a dielectric having a high relative dielectric constant generated by a special process, that is, a so-called ferroelectric between electrodes. used. As this ferroelectric, there is BST (Barium Strontium Titanium), and when this is adopted, the same capacitance is obtained with an area of only 2% compared to SiN (Silicon Nitride) as a dielectric frequently used in ordinary integrated circuits. Since it can be realized, for example, a capacitance of 400 pF or more is formed in the integrated circuit.
[0009]
[Problems to be solved by the invention]
However, when the capacitor 24 is formed of a ferroelectric BST in the frequency conversion semiconductor integrated circuit, as described above, the capacitance per unit area is 50 times that of the case where the capacitor 24 is formed of SiN. However, there is a problem that the manufacturing cost becomes high because of a complicated semiconductor manufacturing process step. On the other hand, it is also possible to form an equivalent large-capacitance capacitor 24 in the integrated circuit using the above-described SiN dielectric material due to restrictions on the mounting package size of the integrated circuit and an increase in chip cost. Have difficulty.
[0010]
For this reason, as shown in FIG. 4, it may be considered that an equivalent of the capacitor 24 is disposed outside the integrated circuit. That is, in the example of FIG. 4, a terminal 26 is provided on the source side of the FET 2, and a large-capacity external capacitor 27 is disposed between the terminal 26 and the ground potential. However, even in a circuit having such a configuration, the inductance of a bonding wire or lead that is a mounting member of an IC package, the wiring inductance from this lead to the capacitor 27, and the parasitic inductance that is the sum of the parasitic inductances in the external capacitor 27 28, and the low impedance characteristic is hindered by the impedance of the parasitic inductance 28.
[0011]
That is, although the impedance of the parasitic inductance 28 does not affect the conversion gain of the frequency conversion at a frequency sufficiently lower than the impedance of the external capacitor 27, the low impedance state of the external capacitor 27 changes as the frequency increases. Therefore, the bypass effect by the so-called external capacitor 27 cannot be obtained.
[0012]
FIG. 5 shows a case where the capacity of the external capacitor 27 is 470 pF, the frequency of the high-frequency signal source 5 is 820 MHz, the frequency of the local oscillation signal source 9 is 690 MHz, and the output intermediate frequency is 130 MHz in the circuit of FIG. A simulation result of the impedance between the source of the FET 2 and the ground potential is shown. As understood from this figure, as the frequency becomes higher, the impedance increases, and therefore, the conversion gain also decreases significantly as the frequency increases. This reduction in conversion gain is caused by the parasitic inductance 28 described above, and therefore cannot be eliminated even if the capacitance value of the external capacitor 27 is changed. I can't.
[0013]
The present invention has been made to solve the above-described problems, and its purpose is to employ a high-cost capacitor using a ferroelectric material between the source electrode of the field effect transistor and the ground potential. , suppressing an increase in impedance caused by the parasitic inductance of the mounting member of the IC package is to provide a frequency varying circuit without adversely affecting the frequency conversion gain.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has a semiconductor integrated circuit in which a field effect transistor for frequency conversion is formed, and the source electrode of the field effect transistor in this semiconductor integrated circuit is connected via a ground potential connection terminal. Te in an integrated circuit external frequency conversion circuitry connected to the ground potential of connecting the outer BUKO capacitor connection terminal to the source electrodes of the field effect transistor, the capacitor connecting terminal and the integrated circuit external ground potential In order to reduce the impedance in the low frequency range of 50 MHz to 300 MHz generated between the source electrode of the field effect transistor and the ground potential, an external capacitor having a capacity of 200 pF to 1000 pF is connected to the source of the field effect transistor. between the electrode and the ground potential connecting terminal, the drain of the field effect transistor - Bas An internal capacitor is formed so as to be in parallel with the resistor for setting the bias current, and this internal capacitor lowers the impedance in the high frequency range of 650 MHz to 1.2 GHz generated between the source electrode of the field effect transistor and the ground potential. The capacitance is 30 pF to 50 pF, or the capacitance is 10 pF to 25 pF for lowering the impedance in the high frequency range of 1.3 GHz to 1.7 GHz .
[0015]
According to the above configuration, the integrated circuit outside the external capacitor, it is possible to lower the impedance component of the low frequency region that caused by parasitic inductance between the source electrode and the ground potential of the field effect transistor (FET), also The internal capacitor can reduce the high frequency impedance component caused by the parasitic inductance. Therefore, even when an inexpensive capacitor using a dielectric is employed, the frequency characteristics of the conversion gain in a wide band in the frequency conversion circuit can be improved.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example of a frequency conversion semiconductor integrated circuit according to the embodiment, and the same members as those in the conventional circuit are denoted by the same reference numerals. As shown in FIG. 1, the FET 2 in the integrated circuit section 1 is a depletion mode field effect transistor using a GaAs compound semiconductor, and an impedance matching circuit is connected to a terminal 3 on the first gate side of the FET 2. The local oscillation signal source 9 is connected to the high-frequency signal source 5 via 4 and the terminal 7 on the second gate side via the impedance matching circuit 8. The resistor 6 shown is the internal impedance of the high-frequency signal source 5, and the other resistor 10 is the internal impedance of the local oscillation signal source 9.
[0017]
The drain terminal 12 of the FET 2 is provided with an output terminal 14 via an impedance matching circuit 13, and a bias supply terminal for supplying a DC bias voltage via an inductor 15 functioning as a high-frequency cutoff choke coil. 16 is provided.
[0018]
A resistor 19 for setting the drain-bias current of the FET 2 is connected between the source side of the FET 2 and a terminal (ground potential connection terminal) 18 for connection to an external ground potential. A resistor 20 is connected between the terminal 18 and the first gate of the FET 2, and a resistor 21 is connected between the second gate. The resistors 20 and 21 apply a predetermined DC bias voltage to the first gate and the second gate. According to the frequency conversion circuit having such a configuration, for example, by applying a high frequency signal of 820 MHz from the high frequency signal source 5 and a local oscillation signal of 690 MHz from the local oscillation signal source 9 to each gate of the FET 1, the output terminal 14 An intermediate frequency signal of 130 MHz can be obtained.
[0019]
In this frequency conversion circuit, a bonding wire and leads, which are IC package mounting members, are formed between the terminal 18 and the ground potential, and a parasitic inductance 23 is present as the sum of these inductance components.
[0020]
In this example, a terminal (capacitor connection terminal) 26 is provided on the source side of the FET 2, an external capacitor 30 is externally disposed between the terminal 26 and the ground potential, and the FET 2 is provided in the integrated circuit 1. The internal capacitor 31 is formed in parallel with the resistor 19 between the source and the terminal 18.
[0021]
However, in this case, as in the case of FIG. 4, the inductance of the bonding wire or lead that is the mounting member of the IC package, the wiring inductance from this lead to this external capacitor 30, and the parasitic in the external capacitor 30 A parasitic inductance 32 as a sum of inductances exists between the terminal 26 and the ground potential. When this parasitic inductance 32 is compared with the above-described parasitic inductance 23, the parasitic inductance 23 becomes a bonding wire or a lead portion dedicated to the ground potential, and therefore has an inductance value lower than that of the parasitic inductance 32.
[0022]
Therefore, in this example, in order to reduce the impedance in the low frequency range of 50 MHz to 300 MHz, the external capacitor 30 has a capacity of 200 pF to 1000 pF, and the internal capacitor 31 has a high frequency range of 650 MHz to 1.2 GHz. In order to reduce the impedance in the case of 30 pF to 50 pF, the impedance is reduced in a wide band.
[0023]
That is, since the external capacitor 30 is not limited in capacity, the external capacitor 30 performs the role of lowering the impedance in the low frequency range where a large capacity is required, while the role of lowering the impedance in the high frequency range where a smaller capacity is sufficient. This is performed by the capacitor 31. Therefore, the SiN dielectric can be used between the electrodes to form the internal capacitor 31 with a small occupation area, and the internal capacitor 31 can be formed in the integrated circuit 1 without difficulty.
[0024]
According to the external capacitor 30, the conversion gain is maintained at a relatively low frequency (for example, 50 MHz to 300 MHz) where the impedance due to the parasitic inductance 23 has an influence and the impedance due to the parasitic inductance 32 does not. Can do. Note that the impedance characteristic of the resistor 19 connected to the source of the FET 2 does not depend on the frequency.
[0025]
Further, according to the internal capacitor 31, the impedance can be lowered mainly in the high frequency range (for example, 650 MHz to 1.2 GHz) in which the impedance is increased by the parasitic inductance 32, and the conversion gain can be improved. Can be maintained.
[0026]
FIG. 2 shows a simulation result of the impedance between the source of the FET 2 and the ground potential when the capacitance of the external capacitor 30 is 470 pF and the capacitance of the internal capacitor 31 is 35 pF. This is the case of FIG. Similarly, the frequency of the high-frequency signal source 5 is 820 MHz, the frequency of the local oscillation signal source 9 is 690 MHz, and the intermediate frequency is 130 MHz. As can be seen from this figure, the impedance is much lower at other desired frequencies such as 130 MHz, 690 MHz, and 820 MHz.
[0027]
Therefore, the external capacitor 30 and the internal capacitor 31 complement each other over a wide band, so that a low impedance characteristic between the source electrode of the FET and the ground potential is obtained. Compared with the circuit of FIG. Can be improved in a high frequency range.
[0028]
Further, the circuit equivalent to FIG. 1 and the circuit equivalent to FIG. 4 are mounted on a surface mount plastic package (outer shape 2.9 mm × 1.6 mm), and small chip capacitors (outer shape 1.. The conversion gain by simulation assuming the case of applying 6 mm × 0.8 mm) is as shown in FIG. 1 under the condition that the frequency of the high-frequency signal source 5 is 820 MHz, the frequency of the local oscillation signal source 9 is 690 MHz, and the intermediate frequency is 130 MHz. The result was 14.6 dB for the circuit and 5.7 dB for the circuit of FIG. 4, and the circuit of FIG. 1 clearly improved the frequency conversion gain compared to the circuit of FIG.
[0029]
The capacitances of the external capacitor 30 and the internal capacitor 31 are set to 200 pF to 1000 pF in order to reduce the impedance of the external capacitor 30 in the low frequency range of 50 MHz to 300 MHz as described above. For 31, in order to lower the impedance in the high frequency range of 1.3 GHz to 1.7 GHz, the capacitance can be 10 pF to 25 pF. Even in such a frequency range, a good frequency conversion gain can be obtained as a low impedance characteristic. It is possible to obtain.
[0030]
【The invention's effect】
As described above, according to the present invention, the frequency conversion circuitry to the source electrode of the FET for frequency conversion is connected to the ground potential of the integrated circuit outside via the ground connection terminal, to the outside of the integrated circuit Since an external capacitor for lowering the impedance of the low frequency region generated between the source electrode of the FET and the ground potential is connected, and an internal capacitor for lowering the impedance of the high frequency region is formed in the integrated circuit. Without using a capacitor with a ferroelectric material between the electrodes, the increase in impedance caused by the parasitic inductance of the IC package mounting member is suppressed between the FET source electrode and the ground potential, especially in the high frequency range. Gain can be greatly improved. In addition, there is an advantage that a frequency conversion circuit having a semiconductor integrated circuit can be manufactured at low cost.
[0031]
Specifically, the external capacitor has a capacitance of 200 pF to 1000 pF, the impedance in a low frequency range of 50 MHz to 300 MHz is reduced, the internal capacitor has a capacitance of 30 pF to 50 pF, and a high frequency range of 650 MHz to 1.2 GHz. Impedance can be reduced. Although the upper Kigaibu capacitor is the same as described above, if the internal capacitor and the capacity of 10PF～25pF, it is possible to reduce the impedance of the high frequency range of 1.3GHz～1.7GHz. According to these configurations, it is possible to obtain low impedance characteristics in a desired frequency band.
[Brief description of the drawings]
1 is a circuit diagram showing a configuration of a frequency conversion circuitry according to an embodiment of the present invention.
Is a graph showing the relationship between the frequency of the impedance characteristic between the Figure 2. The mounting simulation of frequency conversion circuitry of Figure 1 and the source electrode of the FET and the ground potential.
3 is a circuit diagram showing an example of a conventional frequency conversion circuitry.
[4] In another example of the frequency conversion circuitry with an improved circuit of FIG. 3 is a circuit diagram when provided with external capacitors.
Is a graph showing the relationship between the frequency of the impedance characteristic between the Figure 5. The mounting simulation of frequency conversion circuitry of Figure 4 and the source electrode of the FET and the ground potential.
[Explanation of symbols]
1 ... integrated circuit,
2… FET,
5 ... high frequency signal source,
9: Local oscillation signal source,
14: Output terminal,
18: Ground potential connection terminal,
23, 28, 32 ... parasitic inductance,
24, 31 ... internal capacitors,
26: Capacitor connection terminal,
27, 30 ... External capacitors.

Claims (1)

A frequency having a semiconductor integrated circuit in which a field effect transistor for frequency conversion is formed, and a source electrode of the field effect transistor in the semiconductor integrated circuit is connected to a ground potential outside the integrated circuit via a ground potential connection terminal in a strange circuit,
Connect the outer BUKO capacitor connection terminal to the source electrodes of the field effect transistor, between the capacitor connecting terminal and the integrated circuit external ground potential, the source electrode of the field effect transistor - occurs between the ground potential 50MHz~ In order to reduce the impedance in the low frequency range of 300 MHz, an external capacitor having a capacity of 200 pF to 1000 pF is connected,
An internal capacitor is formed between the source electrode of the field effect transistor and the ground potential connection terminal so as to be in parallel with a resistor for setting a drain-bias current of the field effect transistor . In order to reduce the capacitance of 30 pF to 50 pF for reducing the impedance in the high frequency range of 650 MHz to 1.2 GHz generated between the source electrode and the ground potential of the field effect transistor or the impedance in the high frequency range of 1.3 GHz to 1.7 GHz. frequency conversion circuitry, characterized in that it has the capacity of 10pF~25pF of.

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