JP3827983B2

JP3827983B2 - Semiconductor evaluation method and semiconductor evaluation apparatus

Info

Publication number: JP3827983B2
Application number: JP2001291522A
Authority: JP
Inventors: 辺浩志渡
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2001-09-25
Filing date: 2001-09-25
Publication date: 2006-09-27
Anticipated expiration: 2021-09-25
Also published as: JP2003100830A

Description

【０００１】
【発明の属する技術分野】
本発明は、ＭＯＳトランジスタやＭＯＳキャパシタ等における絶縁膜の下部に位置する導電膜表面の不純物濃度を評価する半導体評価方法および半導体評価装置に関する。
【０００２】
【従来の技術】
半導体基板中の不純物濃度は深さ方向に分布しているが、半導体装置の電気特性は表面近傍での不純物濃度に敏感である。このため、表面不純物濃度を正確に測定する技術が半導体装置の設計および製造の面から不可欠である。
【０００３】
【発明が解決しようとする課題】
しかしながら、従来は、基板深さ方向の不純物濃度を測定する際、半導体装置を削り取りながらSIMS(Secondary Ion Mass Spectrometry)という方法を使って測定するのが一般的であった。この方法では測定後の半導体装置を破壊してしまう上に、削り取る深さを非常に薄くし、しかもその幅を正確にしなければ十分な測定精度が得られないという問題がある。
【０００４】
また、ウエハ表面を部分的に削り取るのは技術的に難しい上に、部分的に削り取るだけでは、ウエハ表面上の不純物濃度の全体的な分布を評価することはできない。さらに、ウエハ表面を削り取った個所では、不純物濃度が変化するおそれもある。
【０００５】
本発明は、上記の問題点に鑑みてなされたもので、その目的は、半導体基板上に形成された半導体装置を破壊することなく、基板表面の不純物濃度の分布を精度よく測定可能な半導体評価方法および半導体評価装置を提供することにある。
【０００６】
【課題を解決するための手段】
上述した課題を解決するために、本発明の一態様によれば、絶縁膜の上面に第１導電膜が形成され前記絶縁膜の下面に第２導電膜が形成された半導体装置の電気的特性をシミュレータを用いて評価する半導体評価方法であって、前記第１および第２導電膜と前記絶縁膜とが形成された測定用半導体装置の前記絶縁膜に対して、前記測定用半導体装置が破壊されない程度の電圧を印加した状態で、前記絶縁膜を介して前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を測定するステップと、前記半導体装置の前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を前記シミュレータにより計算し、その計算結果が測定結果に一致するように前記絶縁膜の膜厚を調節するステップと、前記絶縁膜を挟む前記第1及び第２導電膜間の電位差の変動幅が１Ｖ以下になるような電圧を印加した状態で、前記絶縁膜を介して前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を測定するステップと、前記半導体装置の前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を前記シミュレータにより計算し、その計算結果が測定結果に一致するように前記第２導電膜の表面不純物濃度を決定するステップと、を備え、前記第 1 導電膜がゲート電極、前記第２導電膜がシリコン基板であることを特徴とする半導体評価方法を提供するものである。
【０００７】
また、本発明の一態様によれば、絶縁膜の上面に第１導電膜が形成され前記絶縁膜の下面に第２導電膜が形成された半導体装置の電気的特性をシミュレータを用いて評価する半導体評価装置であって、前記第１および第２導電膜と前記絶縁膜とが形成された測定用半導体装置の前記第１導電膜に対して、前記半導体装置が破壊しない程度の電圧を印加した状態で、前記絶縁膜を介して前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を測定する初期特性測定部と、前記半導体装置の前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を前記シミュレータにより計算し、その計算結果が測定結果に一致するように前記絶縁膜の膜厚を調節する膜厚逆抽出部と、前記絶縁膜を挟む前記第1及び第２導電膜間の電位差の変動幅が１Ｖ以下になるような電圧を印加した状態で、前記絶縁膜を介して前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を測定するＭＯＳ特性測定部と、前記測定用半導体装置の前記第1および第２導電膜間を流れる電流と前記第１および第２導電膜間の容量との少なくとも一方を前記シミュレータにより計算し、その計算結果が測定結果に一致するように前記第２導電膜の表面不純物濃度を決定する表面濃度決定部と、を備え、前記第 1 導電膜が、ゲート電極、前記第２導電膜がシリコン基板であることを特徴とする半導体評価装置を提供するものである。
【０００８】
本発明では、絶縁膜にほとんど電界がかからない低電界領域で、第１および第２導電膜間を流れる電流と第１および第２導電膜間の容量との少なくとも一方を測定し、その測定結果に基づいて第２導電膜の表面不純物濃度を決定するため、基板のバルク部分の不純物濃度に影響されることなく、簡易かつ精度よく不純物濃度を決定できる。
【０００９】
【発明の実施の形態】
以下、本発明に係る半導体評価方法および半導体評価装置について、図面を参照しながら具体的に説明する。
【００１０】
図１は本発明に係る半導体評価装置の一実施形態の概略構成を示すブロック図である。図１の半導体評価装置は、ＭＯＳトランジスタやＭＯＳキャパシタ内の絶縁膜の下部に形成された導電膜表面の不純物濃度を決定するものである。以下では、ＭＯＳトランジスタを例にとって説明するが、ＭＯＳキャパシタを用いても同様である。また、ＭＯＳトランジスタやＭＯＳキャパシタ内の絶縁膜の上部に形成された導電膜を第１導電膜、絶縁膜の下部に位置する導電膜を第２導電膜と呼ぶ。
【００１１】
図１の半導体評価装置は、初期特性測定部１と、膜厚逆抽出部２と、ＭＯＳ特性測定部３と、表面濃度決定部４とを備えている。
【００１２】
初期特性測定部１は、測定試料中の絶縁膜の上部に形成された第１導電膜にＭＯＳトランジスタが破壊しない程度の電圧（例えば、１Ｖ程度）を印加した状態で、絶縁膜を介して第１および第２導電膜間を流れる電流、あるいは第１および代２導電膜間の容量を測定する。
【００１３】
膜厚逆抽出部２は、第２導電膜の表面濃度の初期値を設定し、第１導電膜に上記の電圧を印加した状態で、第１および第２導電膜間を流れる電流、または第１および第２導電膜間の容量をシミュレータを用いて計算する。そして、その計算結果が前記初期特性測定部１に一致するように、上述した絶縁膜の膜厚を調節して、上記電流または容量の計算を繰り返す。計算結果と測定結果が一致したときの絶縁膜の膜厚が逆抽出された膜厚になる。
【００１４】
ＭＯＳ特性測定部３は、絶縁膜の電圧の変動幅が所定電圧以下になるような電圧範囲内の電圧を測定試料、ここではＭＯＳトランジスタの第１導電膜に印加した状態で、絶縁膜を介して第1および第２導電膜間を流れる電流か、または第１および第２導電膜間の容量を測定する。すなわち、ＭＯＳトランジスタのゲート電流密度とゲート電圧との関係（Ｊ−Ｖ特性）またはゲート容量とゲート電圧との関係（Ｃ−Ｖ特性）を測定する。
【００１５】
表面濃度決定部４は、絶縁膜の電圧の変動幅が所定電圧以下になるような電圧範囲について、シミュレータによりＪ−Ｖ特性またはＣ−Ｖ特性を計算し、その計算結果がＭＯＳ特性測定部３で測定した測定結果に一致するように、第２導電膜の表面不純物濃度を調節してＪ−Ｖ特性またはＣ−Ｖ特性の計算を繰り返す。
【００１６】
本実施形態は、絶縁膜厚を調節しながら計算したゲート電流またはゲート容量を測定結果に一致させることにより絶縁膜厚を逆抽出する第一段階を経た後に、逆抽出した絶縁膜厚をシミュレータに入力して第２導電膜の表面不純物濃度を調節しながら計算したＪ−Ｖ特性またはＣ−Ｖ特性を測定試料による測定結果に一致させることにより表面不純物濃度を逆抽出する第二段階を行う。
【００１７】
このような二段階の逆抽出法が可能になるのは、図２に示すように、ＭＯＳキャパシタやＭＯＳトランジスタのＪ−Ｖ特性曲線やＣ−Ｖ特性曲線における表面不純物濃度依存性が低ゲート電圧領域側（例えば、−１Ｖ〜０Ｖ）に限られるためである。
【００１８】
図２（ａ）はｎ-基板、図２（ｂ）はｐ-基板の表面不純物濃度依存性を示している。ｎ-基板では、表面不純物濃度の増大に伴い、低電界領域のゲート電流が増大する。一方、ｐ-基板では、表面不純物濃度の増大に伴い、低電界領域のゲート電流が減少する。
【００１９】
ここで、このような特徴が得られる原因を、図３を用いて説明する。図３（ａ）はゲート電圧と絶縁膜（例えば、酸化膜）電圧との関係を示している。図３（ａ）からわかるように、ゲート電圧が−１Ｖから０Ｖの電圧範囲では絶縁膜電圧はあまり変化しない。すなわち、この電圧範囲は、絶縁膜に電界がかかりにくい低電界領域である。
【００２０】
ゲート電圧が−１Ｖ〜０Ｖの電圧範囲内のエネルギーバンドは図３（ｂ）のようになり、０Ｖを超える電圧範囲内のエネルギーバンドは図３（ｃ）のようになる。
【００２１】
図３（ｂ）に示すように、絶縁膜に電界があまりかからない低電界領域では、バンドの曲がり（バンドベンディング）が表面領域に限られ、表面電荷密度Ｑsが表面領域のみで決定されるのがわかる。すなわち、表面不純物濃度が表面電荷密度を決定する。このような低電界時に流れるゲート電流やゲート容量は、表面電荷密度に敏感なので、結局、ゲート電流もゲート容量も表面不純物濃度に敏感になる。
【００２２】
一方、図３（ｃ）に示すように、絶縁膜に高電界がかかる高電界領域では、基板のバルク部分までバンドが曲がるため、表面電荷密度に与える表面不純物濃度の影響は相対的に小さくなる。
【００２３】
このように、ＭＯＳトランジスタのゲート電流およびゲート容量の表面不純物濃度依存性は、絶縁膜に電界がほとんどかからない低電界領域に限定される。
【００２４】
図４は図１の半導体評価装置の処理動作を示すフローチャートである。まず、シミュレータに対して、第２導電膜を形成する基板のバルク部分の不純物濃度とゲートポリシリコンからなる第１導電膜の不純物濃度とを与える（ステップＳ１）。
【００２５】
次に、測定装置を用いて、測定試料のＪ−Ｖ特性かＣ−Ｖ特性を測定する（ステップＳ２）。例えば、Ｊ−Ｖ特性を測定する場合、絶縁膜が破壊しない程度の電界が絶縁膜にかかるように、ゲートポリシリコンに所定の電圧（例えば、１Ｖ）を印加した状態で、測定装置にてゲート電流Ｊを測定する。これらステップＳ１およびＳ２の処理は初期特性測定部１が行う。
【００２６】
次に、シミュレータに対して、第２導電膜の初期値として適当な表面濃度を与える（ステップＳ３）。次に、ＭＯＳトランジスタのゲート電流を精度よく再現できるように予め用意されたシミュレータを用い、ゲート電圧を例えば１Ｖとしてゲート電流を計算し、その計算結果がステップＳ２の測定結果に一致するまで、絶縁膜の膜厚を調整してゲート電流の計算を繰り返す（ステップＳ４）。以上の処理により、絶縁膜の膜厚が逆抽出される。このステップＳ３およびＳ４の処理は膜厚逆抽出部２が行う。
【００２７】
次に、絶縁膜に電界がかからないような電圧範囲内にゲート電圧を設定した状態で、シミュレータによりＪ−Ｖ特性またはＣ−Ｖ特性を計算し、その計算結果がステップＳ２による測定結果に一致するまで、基板の表面不純物濃度を調節してＪ−Ｖ特性またはＣ−Ｖ特性の計算を繰り返す（ステップＳ５）。これにより、基板の表面不純物濃度が逆抽出される。このステップＳ５の処理は、表面濃度決定部４が行う。
【００２８】
ここで、Ｊ−Ｖ特性は、例えば（１）式で表される。
【００２９】
【数１】

（１）式において、m_deは状態密度電子質量、EC_polyはポリシリコンの伝導帯端、EC_subは基板シリコンの伝導帯端、ｔ_oxは絶縁膜厚、ｑ＝1.6×10^-19[C]、Ｍ_c＝６である。
【００３０】
（１）式中の関数ｆは、（２）式で表される。
【００３１】
【数２】

（２）式において、Ｅ_Fはフェルミ準位、k_B＝1.38×10^-23[J/K]、Ｔは絶対温度[K]である。
【００３２】
（１）式中のκは、（３）式で表される。
【００３３】
【数３】

（３）式において、EC_oxは絶縁膜の伝導帯端である。
【００３４】
（３）式中のｍ_oxは、（４）式で表される。
【００３５】
【数４】

（４）式において,EG_oxは絶縁膜のエネルギーバンドギャップ、ｍ_pはパラボリック・トンネルマス、ｍ_Fはフランツのトンネルマス、ｍ_cは伝導帯トンネルマス、ｍ_vは価電子帯トンネルマスである。
【００３６】
（１）式中のΨs_polyとΨs_subとの間には、以下の関係が成り立つ。
【００３７】
【数５】

（５）式中の関数Ｆは、（６）式で表される。
【００３８】
【数６】

（６）式中のβとＬ_Dはそれぞれ（７）式および（８）式で表される。
【００３９】
【数７】

【数８】

（８）式において、ε_s＝11.9×ε₀で、ε₀＝8.85×10^-12[F/m]である。
【００４０】
図５は上述した二段階逆抽出法により得られた調節パラメータ（絶縁膜厚と表面不純物濃度）を（１）式に代入して計算した直接トンネル電流と、ＭＯＳトランジスタで測定したゲート電流との一致の度合いを比較した図である。図５の横軸はゲート電圧を、縦軸は直接トンネル電流（ゲート電流）を示している。
【００４１】
図示のように、広範なゲート電圧範囲について計算結果と測定結果はほぼ完全に一致しており、本実施形態の計算手法の精度が十分に高いことがわかる。
【００４２】
一方、Ｃ−Ｖ特性は（９）式で表される。
【００４３】
【数９】

（９）式中のＱ_sは（１０）式で表される。
【００４４】
【数１０】

上述した図４のステップＳ５では、（１）式によりＪ−Ｖ特性を計算するか、あるいは（９）式によりＣ−Ｖ特性を計算し、その計算結果を測定結果と比較し、両方の結果が一致しなければ、基板の表面不純物濃度を調節して、再度Ｊ−Ｖ特性またはＣ−Ｖ特性を計算して、測定結果と比較する。このような計算処理を繰り返すことで、基板の表面不純物濃度を逆抽出することができる。
【００４５】
図５の二段階逆抽出法により得られた基板の表面不純物濃度は、例えばＭＯＳトランジスタのしきい値電圧を計算するのに用いられる。しきい値電圧は、表面不純物濃度Ｎ_A ^'を用いると、（１１）式で表される。
【００４６】
【数１１】

（１１）式において、Ψ_Bは真性半導体のフェルミ準位と基板のフェルミ準位との電位差、Ｃiは絶縁膜容量[F/cm²]である。
【００４７】
このように、本実施形態では、まずゲート電圧を１Ｖ程度に設定して、絶縁膜厚を調節しながらゲート電流やゲート容量の計算結果と測定結果とをフィッティングさせて絶縁膜厚を逆抽出し、次に、ゲート電圧が−１Ｖ〜０Ｖの範囲内で、基板の表面不純物濃度を調節しながらＪ−Ｖ特性またはＣ−Ｖ特性の計算結果と測定結果とをフィッティングさせて表面不純物濃度を逆抽出するため、絶縁膜の下部の基板の表面不純物濃度を精度よく予測できる。
【００４８】
すなわち、表面不純物濃度を逆抽出する際、絶縁膜に電圧がかからないような電圧範囲内の電圧（−１Ｖ〜０Ｖ）を第１導電膜に印加するため、基板のバルク部分の不純物濃度の影響を受けることなく、簡易な手法で精度よく表面不純物濃度を計算できる。
【００４９】
上述した本実施形態の二段階逆抽出法による表面不純物濃度の非破壊測定は、拡散層のチャネル電界に与える影響が相対的に小さくなるほど長いゲートを持つMOSFETを半導体測定装置として用いる。その他、保護素子部のライン・アンド・スペースパターンを用いてもよいし、あるいは予め選択的にウエハ上に配置されたＭＯＳトランジスタやＭＯＳキャパシタを用いてもよい。
【００５０】
図６は半導体装置の製造に用いられるウエハの平面図である。一枚のウエハ上には多数のチップが形成されているが、ウエハには若干の空きスペースが残されている。このような空きスペースに本実施形態の半導体測定装置となるＭＯＳトランジスタやＭＯＳキャパシタを予め形成しておけば、半導体測定装置以外のチップに非接触の状態で上述した評価処理を行うことができる。したがって、評価処理を行ったウエハについても、通常通りチップの製造を行うことができ、ウエハを無駄にしなくて済む。
【００５１】
ところで、図６では、ウエハ上の複数箇所に分散して測定試料を形成している。このように、複数の測定試料を分散して形成すると、ウエハの反りや歪み等が表面不純物濃度にどのように影響するかを調べることができる。
【００５２】
図７は、ウエハをロット単位で製造する場合に、一ロット分のウエハの配置を示す図である。ウエハ上の複数の測定点での表面不純物濃度分布にばらつきがなくても、ウエハごとの表面不純物濃度の測定結果にずれが生じる場合がある。通常、複数のウエハをロット単位で処理するので、複数のウエハを収納するチェンバ内のガス分圧や温度の偏りが表面不純物濃度にどのように影響しているか調べることができる。
【００５３】
このように、本実施形態の表面不純物濃度測定技術を用いれば、基板の反りや歪み、あるいはチェンバ内のガス分圧や温度の分布等の半導体製造プロセスのリスク要因を調べることができる。
【００５４】
上述した実施形態で説明した半導体評価装置は、ハードウェアで構成してもよいし、ソフトウェアで構成してもよい。ソフトウェアで構成する場合には、半導体評価装置の機能を実現するプログラムをフロッピーディスクやＣＤ−ＲＯＭ等の記録媒体に収納し、コンピュータに読み込ませて実行させてもよい。記録媒体は、磁気ディスクや光ディスク等の携帯可能なものに限定されず、ハードディスク装置やメモリなどの固定型の記録媒体でもよい。
【００５５】
また、半導体評価装置の機能を実現するプログラムを、インターネット等の通信回線（無線通信も含む）を介して頒布してもよい。さらに、同プログラムを暗号化したり、変調をかけたり、圧縮した状態で、インターネット等の有線回線や無線回線を介して、あるいは記録媒体に収納して頒布してもよい。
【００５６】
【発明の効果】
以上詳細に説明したように、本発明によれば、絶縁膜に電圧がかからないような電圧範囲内の電圧を第１導電膜に印加して、第２導電膜の表面不純物濃度を決定するため、表面不純物濃度の計算精度が向上し、ひいては、ＭＯＳトランジスタのしきい値電圧を精度よく計算できる。
【００５７】
また、測定点を分布させることにより、半導体製造プロセスのリスク要因を分析することも可能になる。
【図面の簡単な説明】
【図１】本発明に係る半導体評価装置の一実施形態の概略構成を示すブロック図。
【図２】（ａ）はｎ-基板、（ｂ）はｐ-基板の表面不純物濃度依存性を示す図。
【図３】（ａ）はゲート電圧に対する絶縁膜（例えば、酸化膜）電圧の特性図、（ｂ）はゲート電圧が−１Ｖ〜０Ｖの電圧範囲内のエネルギーバンド図、（ｃ）は０Ｖを超える電圧範囲内のエネルギーバンド図。
【図４】図１の半導体評価装置の処理動作を示すフローチャート。
【図５】二段階逆抽出法により得られた調節パラメータを用いて計算した直接トンネル電流と、半導体測定装置であるＭＯＳトランジスタやＭＯＳキャパシタで測定したゲート電流との一致の度合いを比較した図。
【図６】半導体装置の製造に用いられるウエハの平面図。
【図７】ウエハをロット単位で製造する場合に、一ロット分のウエハの配置を示す図。
【符号の説明】
１初期特性測定部
２膜厚逆抽出部
３ＭＯＳ特性測定部
４表面濃度決定部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor evaluation method and a semiconductor evaluation apparatus for evaluating the impurity concentration on the surface of a conductive film located under an insulating film in a MOS transistor, a MOS capacitor, or the like.
[0002]
[Prior art]
Although the impurity concentration in the semiconductor substrate is distributed in the depth direction, the electrical characteristics of the semiconductor device are sensitive to the impurity concentration in the vicinity of the surface. For this reason, a technique for accurately measuring the surface impurity concentration is indispensable from the viewpoint of designing and manufacturing a semiconductor device.
[0003]
[Problems to be solved by the invention]
However, conventionally, when measuring the impurity concentration in the substrate depth direction, it is common to use a method called SIMS (Secondary Ion Mass Spectrometry) while scraping the semiconductor device. In this method, there is a problem that the semiconductor device after the measurement is destroyed, and the depth to be scraped is made very thin and the width cannot be made accurate, so that sufficient measurement accuracy cannot be obtained.
[0004]
In addition, it is technically difficult to partially scrape the wafer surface, and it is impossible to evaluate the overall distribution of the impurity concentration on the wafer surface only by partially scraping. Furthermore, there is a possibility that the impurity concentration changes at the location where the wafer surface is scraped.
[0005]
The present invention has been made in view of the above problems, and its purpose is to evaluate a semiconductor that can accurately measure the distribution of impurity concentration on the surface of the substrate without destroying the semiconductor device formed on the semiconductor substrate. A method and a semiconductor evaluation apparatus are provided.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, according to one embodiment of the present invention, electrical characteristics of a semiconductor device in which a first conductive film is formed on an upper surface of an insulating film and a second conductive film is formed on a lower surface of the insulating film. A semiconductor evaluation method for evaluating a semiconductor device using a simulator, wherein the measurement semiconductor device destroys the insulation film of the measurement semiconductor device in which the first and second conductive films and the insulation film are formed. Measuring at least one of a current flowing between the first and second conductive films through the insulating film and a capacitance between the first and second conductive films in a state where an unappropriate voltage is applied; At least one of a current flowing between the first and second conductive films of the semiconductor device and a capacitance between the first and second conductive films is calculated by the simulator, and the calculation result matches the measurement result. Said insulation And adjusting the film thickness of the first and second conductive films sandwiching the insulating film and applying a voltage such that a fluctuation range of a potential difference between the first and second conductive films is 1 V or less. Measuring at least one of a current flowing between the first and second conductive films and a capacitance between the first and second conductive films; a current flowing between the first and second conductive films of the semiconductor device; Calculating at least one of the capacitance between the first and second conductive films by the simulator and determining the surface impurity concentration of the second conductive film so that the calculation result matches the measurement result, The first conductive film is a gate electrode, and the second conductive film is a silicon substrate. A semiconductor evaluation method is provided.
[0007]
According to one embodiment of the present invention, electrical characteristics of a semiconductor device in which a first conductive film is formed on an upper surface of an insulating film and a second conductive film is formed on a lower surface of the insulating film are evaluated using a simulator. In the semiconductor evaluation apparatus, a voltage that does not damage the semiconductor device is applied to the first conductive film of the measurement semiconductor device in which the first and second conductive films and the insulating film are formed. An initial characteristic measuring unit that measures at least one of a current flowing between the first and second conductive films and a capacitance between the first and second conductive films via the insulating film in a state; At least one of the current flowing between the first and second conductive films and the capacitance between the first and second conductive films is calculated by the simulator, and the calculation result of the insulating film is set so that the calculation result matches the measurement result. Film thickness to adjust film thickness In a state where a voltage is applied so that the fluctuation range of the potential difference between the extraction unit and the first and second conductive films sandwiching the insulating film is 1 V or less, the first and second conductive elements are interposed through the insulating film. A MOS characteristic measuring unit that measures at least one of a current flowing between the films and a capacitance between the first and second conductive films; a current flowing between the first and second conductive films of the semiconductor device for measurement; A surface concentration determination unit that calculates at least one of the capacitance between the first and second conductive films by the simulator and determines the surface impurity concentration of the second conductive film so that the calculation result matches the measurement result; The semiconductor device is characterized in that the first conductive film is a gate electrode and the second conductive film is a silicon substrate .
[0008]
In the present invention, at least one of the current flowing between the first and second conductive films and the capacitance between the first and second conductive films is measured in a low electric field region where almost no electric field is applied to the insulating film. Since the surface impurity concentration of the second conductive film is determined based on this, the impurity concentration can be determined easily and accurately without being affected by the impurity concentration of the bulk portion of the substrate.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor evaluation method and a semiconductor evaluation apparatus according to the present invention will be specifically described with reference to the drawings.
[0010]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a semiconductor evaluation apparatus according to the present invention. The semiconductor evaluation apparatus shown in FIG. 1 determines the impurity concentration on the surface of a conductive film formed under an insulating film in a MOS transistor or MOS capacitor. Hereinafter, a MOS transistor will be described as an example, but the same applies when a MOS capacitor is used. Also, the conductive film formed above the insulating film in the MOS transistor or MOS capacitor is referred to as a first conductive film, and the conductive film located below the insulating film is referred to as a second conductive film.
[0011]
The semiconductor evaluation apparatus in FIG. 1 includes an initial characteristic measurement unit 1, a film thickness reverse extraction unit 2, a MOS characteristic measurement unit 3, and a surface concentration determination unit 4.
[0012]
The initial characteristic measurement unit 1 applies a voltage (eg, about 1 V) that does not cause the MOS transistor to break down to the first conductive film formed on the insulating film in the measurement sample via the insulating film. The current flowing between the first and second conductive films or the capacitance between the first and second conductive films is measured.
[0013]
The film thickness reverse extraction unit 2 sets the initial value of the surface concentration of the second conductive film, and the current flowing between the first and second conductive films in the state where the voltage is applied to the first conductive film, or the first The capacitance between the first and second conductive films is calculated using a simulator. Then, the calculation of the current or capacitance is repeated by adjusting the film thickness of the insulating film described above so that the calculation result matches the initial characteristic measuring unit 1. The film thickness of the insulating film when the calculation result and the measurement result coincide with each other is the reversely extracted film thickness.
[0014]
The MOS characteristic measuring unit 3 applies a voltage within a voltage range such that the fluctuation range of the voltage of the insulating film is equal to or less than a predetermined voltage to the measurement sample, here the first conductive film of the MOS transistor, and the MOS film is measured via the insulating film. Then, the current flowing between the first and second conductive films or the capacitance between the first and second conductive films is measured. That is, the relationship between the gate current density and the gate voltage (JV characteristic) or the relationship between the gate capacitance and the gate voltage (CV characteristic) of the MOS transistor is measured.
[0015]
The surface concentration determination unit 4 calculates JV characteristics or CV characteristics by a simulator for a voltage range in which the fluctuation range of the voltage of the insulating film is a predetermined voltage or less, and the calculation result is the MOS characteristic measurement unit 3. The calculation of the JV characteristic or the CV characteristic is repeated by adjusting the surface impurity concentration of the second conductive film so as to coincide with the measurement result measured in (1).
[0016]
In this embodiment, after the first stage of back-extracting the insulating film thickness by matching the gate current or gate capacitance calculated while adjusting the insulating film thickness with the measurement result, the back-extracted insulating film thickness is stored in the simulator. A second stage of back-extracting the surface impurity concentration is performed by matching the JV characteristic or CV characteristic calculated while adjusting the surface impurity concentration of the second conductive film with the measurement result of the measurement sample.
[0017]
As shown in FIG. 2, such a two-step back extraction method is possible because the surface impurity concentration dependency in the JV characteristic curve or CV characteristic curve of the MOS capacitor or MOS transistor is low. This is because it is limited to the region side (for example, -1V to 0V).
[0018]
FIG. 2A shows the surface impurity concentration dependence of the n− substrate and FIG. 2B shows the p-substrate. In the n − substrate, the gate current in the low electric field region increases as the surface impurity concentration increases. On the other hand, in the p− substrate, the gate current in the low electric field region decreases as the surface impurity concentration increases.
[0019]
Here, the reason why such a feature is obtained will be described with reference to FIG. FIG. 3A shows the relationship between the gate voltage and the insulating film (for example, oxide film) voltage. As can be seen from FIG. 3A, the insulating film voltage does not change much when the gate voltage is in the voltage range of -1V to 0V. That is, this voltage range is a low electric field region in which an electric field is not easily applied to the insulating film.
[0020]
The energy band within the voltage range of the gate voltage from −1V to 0V is as shown in FIG. 3B, and the energy band within the voltage range exceeding 0V is as shown in FIG.
[0021]
As shown in FIG. 3B, in a low electric field region where an electric field is not applied to the insulating film, band bending (band bending) is limited to the surface region, and the surface charge density Qs is determined only by the surface region. Recognize. That is, the surface impurity concentration determines the surface charge density. Since the gate current and the gate capacitance flowing in such a low electric field are sensitive to the surface charge density, both the gate current and the gate capacitance are sensitive to the surface impurity concentration.
[0022]
On the other hand, as shown in FIG. 3C, in the high electric field region where a high electric field is applied to the insulating film, the band bends to the bulk portion of the substrate, so that the influence of the surface impurity concentration on the surface charge density becomes relatively small. .
[0023]
Thus, the surface impurity concentration dependence of the gate current and gate capacitance of the MOS transistor is limited to a low electric field region where an electric field is hardly applied to the insulating film.
[0024]
FIG. 4 is a flowchart showing the processing operation of the semiconductor evaluation apparatus of FIG. First, the impurity concentration of the bulk portion of the substrate on which the second conductive film is formed and the impurity concentration of the first conductive film made of gate polysilicon are given to the simulator (step S1).
[0025]
Next, using the measuring device, the JV characteristic or the CV characteristic of the measurement sample is measured (step S2). For example, when measuring the J-V characteristic, the gate is measured with a measuring device in a state where a predetermined voltage (for example, 1 V) is applied to the gate polysilicon so that an electric field that does not destroy the insulating film is applied to the insulating film. Measure current J. The initial characteristic measurement unit 1 performs the processes in steps S1 and S2.
[0026]
Next, an appropriate surface concentration is given to the simulator as an initial value of the second conductive film (step S3). Next, using a simulator prepared in advance so that the gate current of the MOS transistor can be accurately reproduced, the gate current is calculated by setting the gate voltage to 1 V, for example, and insulation is performed until the calculation result matches the measurement result in step S2. The calculation of the gate current is repeated by adjusting the film thickness (step S4). Through the above processing, the film thickness of the insulating film is back-extracted. The film thickness reverse extraction unit 2 performs the processes in steps S3 and S4.
[0027]
Next, in a state where the gate voltage is set within a voltage range in which an electric field is not applied to the insulating film, a JV characteristic or a CV characteristic is calculated by a simulator, and the calculation result coincides with the measurement result in step S2. Until then, the calculation of the JV characteristic or CV characteristic is repeated by adjusting the surface impurity concentration of the substrate (step S5). Thereby, the surface impurity concentration of the substrate is back-extracted. The process of step S5 is performed by the surface concentration determination unit 4.
[0028]
Here, the J-V characteristic is expressed by, for example, equation (1).
[0029]
[Expression 1]

In equation (1), m _de is the state density electron mass, EC _poly is the conduction band edge of polysilicon, EC _sub is the conduction band edge of the substrate silicon, t _ox is the insulating film thickness, and q = 1.6 × 10 ⁻¹⁹ [C ], M _c = 6.
[0030]
The function f in the equation (1) is expressed by the equation (2).
[0031]
[Expression 2]

In the equation (2), E _F is the Fermi level, k _B = 1.38 × 10 ⁻²³ [J / K], and T is the absolute temperature [K].
[0032]
In the equation (1), κ is represented by the equation (3).
[0033]
[Equation 3]

In equation (3), EC _ox is the conduction band edge of the insulating film.
[0034]
_{M ox} in the formula (3) is represented by the formula (4).
[0035]
[Expression 4]

In (4), EG _ox is the energy band gap, m _p are parabolic tunnel mass, m _F Franz tunnel mass, m _c is the conduction band tunneling mass, m _v is the valence band tunnel mass of the insulating film .
[0036]
The following relationship is established between Ψs _poly and Ψs _sub in the equation (1).
[0037]
[Equation 5]

The function F in the equation (5) is expressed by the equation (6).
[0038]
[Formula 6]

In the formula (6), β and L _D are represented by formulas (7) and (8), respectively.
[0039]
[Expression 7]

[Equation 8]

In the equation (8), ε _s = 11.9 × ε ₀ and ε ₀ = 8.85 × 10 ⁻¹² [F / m].
[0040]
FIG. 5 shows the direct tunnel current calculated by substituting the adjustment parameters (insulating film thickness and surface impurity concentration) obtained by the above-described two-step back extraction method into the equation (1) and the gate current measured by the MOS transistor. It is the figure which compared the degree of coincidence. The horizontal axis in FIG. 5 represents the gate voltage, and the vertical axis represents the direct tunnel current (gate current).
[0041]
As shown in the figure, the calculation results and the measurement results almost completely coincide with each other over a wide gate voltage range, and it can be seen that the accuracy of the calculation method of the present embodiment is sufficiently high.
[0042]
On the other hand, the CV characteristic is expressed by equation (9).
[0043]
[Equation 9]

Q _s in the formula (9) is represented by the formula (10).
[0044]
[Expression 10]

In step S5 of FIG. 4 described above, the JV characteristic is calculated by the expression (1) or the CV characteristic is calculated by the expression (9), and the calculation result is compared with the measurement result. If they do not match, the surface impurity concentration of the substrate is adjusted, the JV characteristic or the CV characteristic is calculated again, and compared with the measurement result. By repeating such calculation processing, the surface impurity concentration of the substrate can be back-extracted.
[0045]
The surface impurity concentration of the substrate obtained by the two-stage back-extraction method of FIG. 5 is used to calculate the threshold voltage of a MOS transistor, for example. The threshold voltage is expressed by equation (11) when the surface impurity concentration N _A ^′ is used.
[0046]
[Expression 11]

In equation (11), Ψ _B is the potential difference between the Fermi level of the intrinsic semiconductor and the Fermi level of the substrate, and Ci is the insulating film capacitance [F / cm ² ].
[0047]
As described above, in this embodiment, first, the gate voltage is set to about 1 V, and the calculation result of the gate current and gate capacitance is fitted to the measurement result while adjusting the insulation film thickness, and the insulation film thickness is back-extracted. Next, when the gate voltage is in the range of −1V to 0V, the surface impurity concentration is reversed by fitting the calculation result and the measurement result of the JV characteristic or CV characteristic while adjusting the surface impurity concentration of the substrate. Since extraction is performed, the surface impurity concentration of the substrate below the insulating film can be accurately predicted.
[0048]
That is, when the surface impurity concentration is back-extracted, a voltage (−1 V to 0 V) within a voltage range in which no voltage is applied to the insulating film is applied to the first conductive film, so that the influence of the impurity concentration in the bulk portion of the substrate is affected. Without being affected, the surface impurity concentration can be calculated with a simple method with high accuracy.
[0049]
In the non-destructive measurement of the surface impurity concentration by the two-step back extraction method of the present embodiment described above, a MOSFET having a longer gate is used as a semiconductor measuring device as the influence on the channel electric field of the diffusion layer becomes relatively smaller. In addition, a line and space pattern of the protection element portion may be used, or a MOS transistor or a MOS capacitor that is selectively placed on the wafer in advance may be used.
[0050]
FIG. 6 is a plan view of a wafer used for manufacturing a semiconductor device. A large number of chips are formed on one wafer, but some empty space is left on the wafer. If the MOS transistor and the MOS capacitor that are to be the semiconductor measurement device of the present embodiment are formed in advance in such an empty space, the above-described evaluation process can be performed in a non-contact state with a chip other than the semiconductor measurement device. Therefore, even for a wafer that has been subjected to evaluation processing, chips can be manufactured as usual, and the wafer need not be wasted.
[0051]
By the way, in FIG. 6, the measurement sample is formed dispersedly at a plurality of locations on the wafer. In this way, when a plurality of measurement samples are formed in a dispersed manner, it is possible to investigate how the wafer warp, distortion, etc. affect the surface impurity concentration.
[0052]
FIG. 7 is a diagram showing an arrangement of wafers for one lot when wafers are manufactured in lot units. Even if there is no variation in the surface impurity concentration distribution at a plurality of measurement points on the wafer, there may be a deviation in the measurement result of the surface impurity concentration for each wafer. Usually, since a plurality of wafers are processed in lot units, it is possible to examine how the gas partial pressure and temperature deviation in the chamber accommodating the plurality of wafers influence the surface impurity concentration.
[0053]
As described above, by using the surface impurity concentration measurement technique of the present embodiment, it is possible to examine the risk factors of the semiconductor manufacturing process such as the warpage and distortion of the substrate, or the gas partial pressure and temperature distribution in the chamber.
[0054]
The semiconductor evaluation apparatus described in the above-described embodiment may be configured by hardware or software. When configured by software, a program for realizing the function of the semiconductor evaluation apparatus may be stored in a recording medium such as a floppy disk or a CD-ROM and read and executed by a computer. The recording medium is not limited to a portable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.
[0055]
Further, a program for realizing the function of the semiconductor evaluation apparatus may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the program may be distributed through being stored in a recording medium via a wired line or a wireless line such as the Internet in a state where the program is encrypted, modulated, or compressed.
[0056]
【The invention's effect】
As described above in detail, according to the present invention, a voltage within a voltage range in which no voltage is applied to the insulating film is applied to the first conductive film to determine the surface impurity concentration of the second conductive film. The calculation accuracy of the surface impurity concentration is improved, and as a result, the threshold voltage of the MOS transistor can be calculated with high accuracy.
[0057]
In addition, by distributing the measurement points, it becomes possible to analyze risk factors of the semiconductor manufacturing process.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a semiconductor evaluation apparatus according to the present invention.
FIGS. 2A and 2B are diagrams showing the surface impurity concentration dependence of an n-substrate and FIG. 2B, a p-substrate.
3A is a characteristic diagram of an insulating film (for example, oxide film) voltage with respect to a gate voltage, FIG. 3B is an energy band diagram in a voltage range of a gate voltage of −1 V to 0 V, and FIG. Energy band diagram in the voltage range that exceeds
4 is a flowchart showing a processing operation of the semiconductor evaluation apparatus in FIG. 1;
FIG. 5 is a diagram comparing the degree of coincidence between a direct tunnel current calculated using an adjustment parameter obtained by a two-step back-extraction method and a gate current measured by a MOS transistor or a MOS capacitor as a semiconductor measurement device.
FIG. 6 is a plan view of a wafer used for manufacturing a semiconductor device.
FIG. 7 is a view showing an arrangement of wafers for one lot when wafers are manufactured in lot units.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Initial characteristic measurement part 2 Film thickness reverse extraction part 3 MOS characteristic measurement part 4 Surface concentration determination part

Claims

A semiconductor evaluation method for evaluating, using a simulator, electrical characteristics of a semiconductor device in which a first conductive film is formed on an upper surface of an insulating film and a second conductive film is formed on a lower surface of the insulating film,
The insulating film is applied to the insulating film of the measuring semiconductor device in which the first and second conductive films and the insulating film are formed in a state where a voltage is applied so that the measuring semiconductor device is not destroyed. Measuring at least one of a current flowing between the first and second conductive films and a capacitance between the first and second conductive films,
At least one of a current flowing between the first and second conductive films of the semiconductor device and a capacitance between the first and second conductive films is calculated by the simulator, and the calculation result matches the measurement result. Adjusting the thickness of the insulating film;
Flowing between the first and second conductive films through the insulating film in a state where a voltage is applied so that the fluctuation range of the potential difference between the first and second conductive films sandwiching the insulating film is 1 V or less. Measuring at least one of a current and a capacitance between the first and second conductive films;
At least one of a current flowing between the first and second conductive films of the semiconductor device and a capacitance between the first and second conductive films is calculated by the simulator, and the calculation result matches the measurement result. Determining the surface impurity concentration of the second conductive film , wherein the first conductive film is a gate electrode and the second conductive film is a silicon substrate .

The step of determining the surface impurity concentration of the second conductive film includes the first and second of the semiconductor device with respect to a plurality of types of voltages within a voltage range such that a voltage fluctuation range of the insulating film is 1 V or less. The semiconductor evaluation method according to claim 1, wherein a measurement result is compared with a calculation result of at least one of a current flowing between the conductive films and a capacitance between the first and second conductive films.

The semiconductor evaluation method according to claim 1, wherein the semiconductor device is at least one of a MOS transistor and a MOS capacitor.

The measurement semiconductor device is formed in an empty area on a wafer on which a plurality of the semiconductor devices are formed,
The semiconductor evaluation method according to claim 1, wherein the process of each step is performed in a non-contact state with respect to the plurality of semiconductor devices.

5. The semiconductor evaluation method according to claim 4, wherein it is possible to select whether or not to perform the process of each step for each of the measurement semiconductor devices on the wafer.

A semiconductor evaluation apparatus that evaluates, using a simulator, electrical characteristics of a semiconductor device in which a first conductive film is formed on an upper surface of an insulating film and a second conductive film is formed on a lower surface of the insulating film.
The insulating film is applied to the first conductive film of the measurement semiconductor device in which the first and second conductive films and the insulating film are formed in a state in which a voltage is applied to such an extent that the semiconductor device does not break down. An initial characteristic measuring unit for measuring at least one of a current flowing between the first and second conductive films and a capacitance between the first and second conductive films via
At least one of a current flowing between the first and second conductive films of the semiconductor device and a capacitance between the first and second conductive films is calculated by the simulator, and the calculation result matches the measurement result. A film thickness reverse extraction unit for adjusting the film thickness of the insulating film;
It flows between the first and second conductive films through the insulating film in a state where a voltage is applied so that the fluctuation range of the potential difference between the first and second conductive films sandwiching the insulating film is 1 V or less. A MOS characteristic measuring unit that measures at least one of a current and a capacitance between the first and second conductive films;
At least one of the current flowing between the first and second conductive films and the capacitance between the first and second conductive films of the measurement semiconductor device is calculated by the simulator, and the calculation result matches the measurement result. And a surface concentration determination unit for determining a surface impurity concentration of the second conductive film, wherein the first conductive film is a gate electrode and the second conductive film is a silicon substrate. .