JP3833570B2 - Microwave frequency multiplier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microwave frequency multiplier, and more particularly to a microwave frequency multiplier that outputs a microwave or millimeter wave signal having a frequency twice or four times the input microwave signal frequency of about 10 GHz or more.
[0002]
[Prior art]
FIG. 14 is a circuit diagram of a balanced microwave frequency multiplier disclosed in Japanese Patent No. 2807508.
[0003]
This frequency multiplier includes a common-source FET 10 and a common-gate FET 11. A gate G that is an input terminal of the FET 10 and a source S that is an input terminal of the FET 11 are both coupled to the input transmission line 12. Both the drain D as the output terminal and the drain D as the output terminal of the FET 11 are directly connected to the output transmission line 13.
[0004]
A DC blocking capacitor 14 is connected between the gate G of the FET 10 and the input transmission line 12, and a reactance element 15 that causes a phase delay is connected between the source S of the FET 11 and the input transmission line 12. ing.
[0005]
A DC bias voltage is applied to the gates of the FET 10 and the FET 11 from the constant voltage power supplies 16 and 17 via the resistors 18 and 19 so that the FET 10 and the FET 11 operate near the pinch-off. DC cut capacitor between the gate of FET 11 and groundCIs connected.
[0006]
When a sine wave is supplied to the microwave input terminal T1, the FET 10 outputs a rectified positive half wave, and the FET 11 outputs a rectified negative half wave and inverted polarity. That is, the fundamental wave and the odd-order harmonics included in the drain currents of the FET 10 and the FET 11 are opposite in phase to each other, so that both are canceled at T3. On the other hand, the even harmonics included in the drain currents of the FET 10 and the FET 11 are in phase with each other, and thus strengthen each other. The amplitude of the fourth harmonic is considerably smaller than the amplitude of the second harmonic.
[0007]
The reactance element 15 prevents the fundamental wave and odd-order harmonics from being out of phase and the even-order harmonics (especially second and fourth harmonics) from being in phase due to the difference in the transfer characteristics of the FETs 10 and 11. Is done.
[0008]
The frequency multiplier of FIG. 14 does not require a hybrid circuit that generates fundamental waves of opposite phases from the input microwave signal, and thus has the advantage that it can be miniaturized.
[0009]
[Problems to be solved by the invention]
However, when the present inventor supplied an input microwave of about 10 GHz or more to the above-described microwave frequency multiplier and examined the characteristics thereof, it was found that there were the following problems.
[0010]
It has been found that when the input frequency is about 10 GHz or higher, and as a result, the output frequency is 20 GHz or higher, the FET 11 which is a grounded gate exhibits instability such as negative resistance characteristics at the gate G or drain D. . In this case, an attenuator was connected near the output terminal T2 as a countermeasure, but spurious oscillation could not be prevented.
[0011]
In the design of the multiplier, it is common to connect a stub for supplying a DC voltage / current for bias to the drain D of the FET 11 and further match the impedance so that the output becomes maximum with respect to the target multiplication frequency. It is.
[0012]
However, a combination of this stub and the negative resistance, or oscillation by a closed loop including the FETs 10 and 11 occurs. The spurious oscillation becomes noticeable when the input matching state of the output buffer amplifier connected to the output of the frequency multiplier is poor (reflection coefficient is close to 1).
[0013]
Further, when the quadruple circuit is realized, the output frequency reaches the millimeter wave region, so that the high-performance (high maximum oscillation frequency fmax that can be called the maximum response frequency) sufficient to realize this is high. The above problem becomes more serious as the negative resistance or reflection gain becomes larger.
[0014]
The cause of the negative resistance is a parasitic inductance of a conductor that grounds the gate G of the FET 11 and a minute feedback capacitance that is parasitic between the drain D and the source S of the FET 11. In particular, since the input signal and the output signal of the common-gate FET are in phase, the parasitic inductance causes a positive feedback to the gate-grounded FET 11 (in the common-source FET where the input signal and the output signal are in reverse phase, (Feedback and grounded source FETs are commonly used in low noise amplifiers).
[0015]
However, in either case of grounding via a bonding wire or a via formed in the substrate or connecting to a grounding conductor of a coplanar line, some grounding lead is always necessary to form a gate grounded FET. There is also a method of grounding by forming a 1/4 wavelength transmission line with an open end on the substrate, but in this case, since only a predetermined frequency (or band) component is grounded, a frequency component higher than the predetermined frequency is used. The above-described parasitic inductance occurs.
[0016]
After all, it is difficult to reduce the parasitic inductance to such an extent that the operation of the grounded-gate FET does not become unstable at all frequencies, and the circuit including the grounded-gate FET becomes unstable at a millimeter wave or a high frequency close thereto. There was a problem that it was easy.
[0017]
In view of the above problems, an object of the present invention is to provide a stable microwave frequency multiplier that does not cause spurious oscillation due to parasitic inductance of a conductor that grounds a control input terminal of a transistor.
[0018]
[Means for Solving the Problems]
  A microwave frequency multiplier according to the present invention comprises:
  An input transmission line to which an input microwave signal is supplied;
  An output transmission line;
  A first control input and a first current path, the first control input coupled to the input transmission line;FirstA first transistor having one end of a current path connected to a ground conductor;
  A second control input and a second current path, the second control input connected to the ground conductor;SecondA second transistor having one end of a current path coupled to the input transmission line;
  A first damping resistor connected between the other end of the first current path and the output transmission line;
  A second damping resistor connected between the other end of the second current path and the output transmission line;
  Have
  The ground conductor is a ground plate and,Conductive to the ground plateAnd formed between the first transistor and the second transistor.With one viaThe firstOne end of the current path and the second control input end are both connected to the one via.Directly at approximately equal distanceConnected and conducted to the ground plate through the one via.
[0019]
In the above configuration, when a sine wave is supplied to the input transmission line, the first transistor outputs a rectified positive half wave, and the second transistor outputs a rectified negative half wave and inverted polarity. That is, the fundamental wave and odd harmonics included in the currents flowing through the current paths of the first and second transistors have phases opposite to each other, so that both are canceled by the output transmission line. On the other hand, the even harmonics included in the currents flowing through the current paths of the first and second transistors have the same phase, and thus strengthen each other.
[0020]
The first and second damping resistors reduce the amplitude of all frequency signals, but do not shift the phase. Therefore, even harmonics are strengthened and taken out from the output transmission line.
[0021]
Also, even if a negative resistance is generated due to the parasitic inductance of the conductor that grounds the control input terminal of the second transistor, the second damping resistor cannot form a pseudo oscillation circuit formed by the second transistor and the output transmission line. To do. In other words, it is possible to increase the loss in the output transmission line that functions as a resonator of the pseudo oscillation circuit so that the oscillation condition is not satisfied at an arbitrary frequency. Therefore, even when design parameters are determined so as to obtain a high-frequency multiplied signal such as a millimeter wave, a stable microwave frequency multiplier without spurious oscillation can be realized.
[0022]
Oscillation generated in a loop that circulates the first and second transistors is to suppress the loop oscillation by determining the resistance values of the first and second damping resistors so that the loop gain is smaller than 1. Can do.
[0023]
In addition, since the attenuator can be configured by combining a series resistor and a parallel resistor, a microwave frequency can be obtained by connecting a resistor between the connection point between the first and second damping resistors and the output transmission line and the ground. Impedance matching between the multiplier and the subsequent output buffer amplifier can be improved, or the overall level diagram including these circuits can be adjusted.
[0024]
Since current is supplied to the current paths of the first and second transistors through the first and second damping resistors, a voltage drop occurs. That is, when one of the first and second transistors is conducting and the other is non-conducting, the voltage between the terminals of the one current path is lower than the DC bias voltage, and between the terminals of the other current path. The voltage is maintained at a voltage approximately equal to the DC bias voltage. This voltage drop increases as the damping resistance value increases. However, since the first and second transistors are biased in the vicinity of the threshold voltage, the average value of the current flowing through the transistors is as low as 10 milliamperes or less, and the voltage drop is 0 if the damping resistance is about 30 ohms or less. .3V, and the reduction in multiplication efficiency due to the first and second transistors is negligible.
[0025]
  In addition, when the frequency is increased, the parasitic inductance associated with grounding essential for the microwave frequency multiplier cannot be ignored, but in the present invention, one end of the current path of the first transistor and the second control input end are Since it is electrically connected to the ground plate via the via, the parasitic inductance between the one end of the current path of the first transistor and the ground plate, the second control input end, and the ground plate The parasitic inductance betweenThe
[0026]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Corresponding identical or similar constituent elements in the drawings are denoted by identical or similar reference numerals.
[0028]
[First Embodiment]
FIG. 1 is a circuit diagram of a microwave frequency multiplier according to a first embodiment of the present invention.
[0029]
The external microwave is supplied to one end T1 of the input transmission line 12 having the characteristic impedance Z0. The other end of the input transmission line 12 is connected to a gate G which is a control input terminal of the FET 10 as the first transistor via a DC bias component blocking capacitor 14 on the one hand, and on the other hand via the transmission line 15. It is connected to the source S which is one end of the current path of the FET 11 as two transistors. The transmission line 15 is used for correcting a passing phase difference caused by the parasitic capacitances of the FETs 10 and 11 and inputting in-phase signals to the FETs 10 and 11.
[0030]
A damping resistor 20 is connected between the drain D which is the other end of the current path of the FET 10 and one end T3 of the external output transmission line 13 having the characteristic impedance Z0, and the drain D which is the other end of the current path of the FET 11 and the external output transmission line. A damping resistor 21 is connected between the one end T <b> 3 of 13.
[0031]
The source S of the FET 10 and the gate G of the FET 11 are grounded. Reference numerals 22 and 23 denote parasitic inductances of the conductors for grounding. The gate of the FET 11 is the capacitor of FIG.CIt is grounded without going through. That is, the capacitorCIn order to avoid the difference between the parasitic inductance of the FET 11 and the parasitic inductance 22 of the source grounded FET 10, the area occupied by the conductor and the area occupied by the grounding conductor increases the distance from the gate of the FET 11 to the grounding point. In the first embodiment, the capacitor of FIG.CDo not use.
[0032]
The gate of the FET 10 is connected to a DC constant voltage source 16 that outputs a voltage Vgg through a DC bias resistor 18. The DC constant voltage source 16 is applied to the bias resistor 18 so that the bias voltage between the gate and the source of the FET 10 is in the vicinity of the pinch-off voltage of the FET 10.
[0033]
A bias voltage proportional to the drain current is supplied to the source of the FET 11 by the self-bias circuit 24 connected to the microwave input terminal T1. The self-bias circuit 24 controls the drain current so that the bias voltage between the gate and the source of the FET 11 is close to the pinch-off voltage of the FET 11.
[0034]
When a sine wave is supplied to the microwave input terminal T1, the FET 10 outputs a rectified positive half wave, and the FET 11 outputs a rectified negative half wave and inverted polarity. That is, the fundamental wave and the odd-order harmonics included in the drain currents of the FET 10 and the FET 11 are opposite in phase to each other, so that both are canceled at T3. On the other hand, the even harmonics included in the drain currents of the FET 10 and the FET 11 are in phase with each other, and thus strengthen each other.
[0035]
By designing the bias voltage between the gate and the source of the FETs 10 and 11 to be as described above and adjusting the voltage of the DC constant voltage source 16, the fundamental and harmonics included in the drain currents of the FETs 10 and 11 can be adjusted. The gains are made identical to each other.
[0036]
As the signal level of the input microwave is increased, both drain currents gradually collapse due to the nonlinearity of the FETs 10 and 11, and the amplitude of the higher-order multiplied wave component increases.
[0037]
When the frequency of the multiplied wave exceeds 20 GHz, or when a field effect transistor having a very high maximum oscillation frequency fmax that can be called a maximum response frequency is used for the FET 10 and the FET 11, The inductance 23 acts to generate a positive feedback between the drain and source of the FET 11, and a negative resistance is generated. On the other hand, the FET 10 is in a negative feedback state.
[0038]
If the output transmission line 13 is directly connected to the drains of the FETs 10 and 11 and a circuit with low input impedance is followed, as in the conventional example of FIG. 14, a reflection type oscillation circuit is easily formed, and unexpected spurious Oscillation occurs. Even if this succeeding circuit is well matched with respect to the frequency of the desired multiplied wave, spurious oscillation occurs at a higher frequency outside the operating band. This is remarkable when the conventional circuit of FIG. 14 is configured using high-performance (high fmax) transistors.
[0039]
On the other hand, in the first embodiment, since the damping resistor 21 is connected between the drain of the FET 11 and the output transmission line 13, even if a negative resistance is generated, the oscillation condition is not satisfied. Spurious oscillation can be eliminated.
[0040]
In addition, since the damping resistor 20 is connected between the drain of the FET 10 and the output transmission line 13, the output levels of the fundamental frequency component and the multiplied wave component from the FET 10 are set to the fundamental frequency component from the FET 11 and the output level, respectively. The output level of the multiplied wave component can be matched.
[0041]
The resistance values of both damping resistors may theoretically be the same value, but the fundamental frequency component and the odd-order multiplied wave component are suppressed by anti-phase synthesis at T3, and the even-order multiplied wave component to be obtained at T3. In order to achieve more increase in output due to in-phase synthesis, the resistance values of both damping resistors may be different.
[0042]
Conventionally, the spurious oscillation reaches not only the reflection type oscillation circuit but also the gate of the FET 11 through reverse transmission in the FET 11, and further reaches the gate of the FET 10 through the transmission line 15 and the capacitor 14. This was also caused by the forward transmission reaching the drain of the FET 10 and from the drain of the FET 10 to the drain of the FET 11, and the loop gain being greater than 1 in the loop. In this case, the impedance at T3 and T1 is high. When the FET 11 exhibits a negative resistance due to the parasitic inductance 23, this loop gain may be larger than 1.
[0043]
On the other hand, in the first embodiment, the loop gain is reduced by the damping resistors 20 and 21 and becomes smaller than 1, so that oscillation does not occur.
[0044]
[Second Embodiment]
FIG. 2 is a circuit diagram of a microwave frequency multiplier according to the second embodiment of the present invention.
[0045]
This wave frequency multiplier is obtained by replacing the output transmission line 13 of the first embodiment with a combination of transmission lines 13 and 25 and a ground capacitor 26. The impedances of all transmission lines are not limited to the characteristic impedance Z0 and are determined as follows. That is, the microwave frequency multiplier has a load impedance that maximizes its output.
[0046]
In order to realize this, one end of the transmission line 13 having the characteristic impedance Z3 is connected to the composite point T3 of the multiplied wave outputs from the FETs 10 and 11, and one end of the transmission line 25 having the characteristic impedance Z4 is connected to the other end (T2). The drain bias voltage Vdd is applied to the other end, and the other end is grounded by a capacitor 26 at a high frequency. Since a desired load impedance can be realized by the T-type circuit composed of the transmission lines 13 and 25, the output level of the multiplied frequency component can be maximized.
[0047]
In addition, you may utilize not only this T-type circuit but the various circuit structure which implement | achieves desired load impedance.
[0048]
The impedance Z2 of the transmission line 15 for phase adjustment is determined according to the input impedance of the FET 10 and the FET 11 so that the fundamental frequency signal having the same phase and the same amplitude is supplied to the FETs 10 and 11 in a desired frequency band. .
[0049]
The impedance Z1 of the input transmission line 12 is a combination of this and the self-bias circuit 24, and the input impedance of the microwave frequency multiplier is a microwave signal source (not shown) connected to one end T1 of the input transmission line 12. It is determined to match the impedance.
[0050]
According to the microwave frequency multiplier of the second embodiment, all the functions of the first embodiment can be realized, and the optimum input / output condition can be realized.
[0051]
[Third Embodiment]
FIG. 3 is a circuit diagram of a microwave frequency multiplier according to the third embodiment of the present invention.
[0052]
In this frequency multiplier, an open-ended transmission line (open stub) having a length of ¼ wavelength is connected to the output terminal T2 of the second embodiment at a frequency twice the input fundamental frequency. Thereby, the double wave of the input fundamental frequency generated from the FETs 10 and 11 is trapped. As in the first and second embodiments, odd-order multiplied waves are suppressed by anti-phase synthesis, and the even-order multiplied waves of the sixth or higher order have a very low output level.
[0053]
Therefore, only the quadruple wave is output from the output terminal T2. For example, a fundamental frequency of 10 GHz is effectively converted into a 40 GHz signal. In addition, the phase noise of the oscillator can be suppressed to 12 dB increase (6 dB phase noise increase at twice the frequency (octave) from the multiplication principle).
[0054]
On the other hand, in an oscillator using a dielectric resonator, the phase noise rises at about 20 dB / octave (an empirical rule from a paper survey).
[0055]
In order to realize an oscillator with low phase noise using millimeter waves, the multiplication method is most excellent. Therefore, a high-order multiplier that can operate stably even with millimeter waves as in the third embodiment has a wide range of applications.
[0056]
As described above, the microwave quadrupler according to the third embodiment can be realized by adding only one trap stub to the microwave doubler. If there is no damping resistance, this trap stub acts on the gate-grounded FET 11 to cause new instability, or to change the instability in some form. This situation makes the design very complex and difficult. However, since the instability can be removed by connecting the damping resistors 20 and 21, a stable multiplication operation is possible.
[0057]
FIG. 4 is a layout diagram on a semi-insulating substrate such as GaAs for realizing the circuit of FIG.
[0058]
In FIG. 4, a hatched area indicates a dielectric area of a capacitor in which a dielectric is sandwiched between vertically opposed metal films. A ground plate, which is a metal film, is attached to the back surface of the semi-insulating substrate. Each transmission line is a strip line composed of a line pattern on the upper surface of the substrate, the ground plate, and the semi-insulating substrate functioning as a dielectric between them. V1 to V3 are all vias having a metal film deposited on the inner wall, and are connected to the ground plate. A metal film is deposited around the substrate upper surface side of each via. The via may be filled with metal.
[0059]
5 to 8 are enlarged sectional views taken along lines VV, VI-VI, VII-VII and VIII-VIII in FIG. 4, respectively.
[0060]
In FIG. 5, 30 is a semi-insulating substrate, 31 is a ground plate, and 141 to 143 are a metal film, a dielectric, and a metal film constituting the capacitor 14, respectively.
[0061]
In FIG. 6, D1 is the drain electrode of the FET 10, and 32 is an insulator.
[0062]
In FIG. 7, 33 and 34 are operation layers formed by implanting impurity ions into the semi-insulating substrate 30, G1 and G2 are gate electrodes, D2 is a drain electrode, and S3 and S4 are source electrodes. The FET 11 has an MES structure, and two transistors are connected in parallel. The sources S3 and S4 are connected by a wiring pattern, and the gates G1 and G2 are connected by a wiring pattern.
[0063]
  In FIG. 8, the resistance21Is formed by implanting impurity ions into the semi-insulating substrate 30, and 201 and 202 are wiring patterns connected to both sides of the resistor 20.
[0064]
In FIG. 4, the source electrodes S1 and S2 of the FET 10 and the gate electrode (thick line) of the FET 11 are all connected to the ground plate 31 via the metal wiring pattern and the via V2.
[0065]
In order to make the value of the resistor 18 relatively large, resistors formed at two locations are connected in series, and each of them is configured in the same manner as the resistor 20.
[0066]
The self-bias circuit 24 is generally used, and one end of a parallel circuit of a resistor 242 and an AC grounding capacitor 243 is connected to the spiral inductor 241 and the other end of the parallel circuit is grounded via a via V1. It is connected to the plate 31. The direct current flowing from the drain to the source of the FET 11 flows to the resistor 242 via the spiral inductor 241 and reaches the ground. The resistance value of the resistor 242 is determined so that the DC voltage between both ends becomes the threshold voltage of the FET 11. Since the capacitor 243 can ignore the impedance at the operating frequency of the microwave frequency multiplier, the spiral inductor 241 can be used for impedance matching.
[0067]
The open stub 27 is formed so as to surround the FET 10 and the transmission line 15 in order to reduce the size of the microwave frequency multiplier.
[0068]
9 to 12 show experimental results of the microwave frequency multiplier of FIG.
[0069]
9 to 11 are frequency characteristic diagrams of various S parameters. A solid line indicates the case where the microwave frequency multiplier of FIG. 4 having the damping resistors 20 and 21 is used, and a broken line indicates the microwave frequency multiplier of FIG. The case where the damping resistors 20 and 21 are not used in the device is shown.
[0070]
The design parameters of the microwave frequency multiplier are determined by the specification of converting a 9.5 GHz input signal into a 38 GHz output signal, and the resistance value of the damping resistor used is 12 ohms.
[0071]
FIG. 9 shows the frequency characteristic of the input reflection gain.
[0072]
As is clear from FIG. 9, there is a large difference between the two characteristics in the frequency range of 60 to 73 GHz, and the solid line shows a stable operation without reflection gain, whereas the broken line includes the frequency of the reflection gain number dB. It exhibits an unstable operation in which the frequency characteristics change significantly. It is considered that spurious oscillation occurs somewhere in the frequency region, and intermodulation is performed between the spurious oscillation component, the fundamental frequency component, and the multiplied wave component, and a large number of spurious components are generated.
[0073]
FIG. 10 shows the frequency characteristic of the output reflection gain.
[0074]
Since the drain of the FET 10 has a high impedance, the reflection gain is in the vicinity of 0 dB. The solid line is a stable operation with no gain at all frequencies, whereas the broken line has a gain in a wide frequency range (33 to 70 GHz), and an unstable reflection gain of 10 dB is observed especially in the vicinity of 60 GHz. Exhibits behavior.
[0075]
FIG. 11 shows the frequency characteristic of the reverse transfer gain.
[0076]
Since the FET 10 and the FET 11 are basically irreversible, even if the amount of transmission increases as the frequency increases due to the parasitic susceptance of the FET 10 and FET 11, the transmission gain in the reverse direction should be significantly lower than 0 dB. However, it reaches around -10 dB at frequencies exceeding 30 GHz. This is a feedback effect of parasitic inductance.
[0077]
The solid line shows a relatively smooth change at less than −10 dB at all frequencies, whereas the broken line shows a steep and unstable operation at a frequency of 60 GHz to 70 GHz. A reverse transfer gain close to 5 dB is also observed.
[0078]
FIG. 12 shows the change of the forward pass gain with respect to the damping resistance value (0 to 30Ω) at 38 GHz. When the damping resistance value is 12 ohms, the gain reduction is about 2 dB, which is sufficiently small for practical use.
[0079]
FIG. 12 also shows the K factor, which is a guideline for stability. Unconditional stability, that is, K> 1, is that the damping resistance value is less than 12 ohms. Further, even when the damping resistance value is increased, the decrease of the passing gain is gradual and is practically acceptable up to 20 ohms.
[0080]
As described above, the damping resistor, which is the main point of the present invention, can stabilize the microwave frequency multiplier, facilitate the design, and further suppress a decrease in the multiplication gain.
[0081]
[Fourth Embodiment]
FIG. 13 is a circuit diagram of a microwave frequency multiplier according to the fourth embodiment of the present invention.
[0082]
In this frequency multiplier, bipolar transistors 10A and 11A are used in place of the FETs 10 and 11 in FIG. The collector, base and emitter of the bipolar transistor correspond to the drain, gate and source of the FET of FIG. As the bipolar transistor, HBT having a high cutoff frequency is preferable.
[0083]
Other points are the same as those in the third embodiment.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a microwave frequency multiplier according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a microwave frequency multiplier according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a microwave frequency multiplier according to a third embodiment of the present invention.
4 is a layout diagram on a semi-insulating substrate that realizes the circuit of FIG. 3; FIG.
FIG. 5 is an enlarged cross-sectional view taken along line VV in FIG.
6 is an enlarged sectional view taken along line VI-VI in FIG. 4;
7 is an enlarged sectional view taken along line VII-VII in FIG.
8 is an enlarged sectional view taken along line VIII-VIII in FIG.
9 is a frequency characteristic diagram of input reflection gain of the microwave frequency multiplier of FIG. 4; FIG.
10 is a frequency characteristic diagram of output reflection gain of the microwave frequency multiplier of FIG. 4; FIG.
11 is a frequency characteristic diagram of a reverse transfer gain of the microwave frequency multiplier of FIG. 4. FIG.
FIG. 12 is a graph showing changes in forward pass gain and K factor with respect to a damping resistance value (0 to 30Ω) for a 38 GHz signal.
FIG. 13 is a circuit diagram of a microwave frequency multiplier according to a fourth embodiment of the present invention.
FIG. 14 is a circuit diagram of a conventional balanced microwave frequency multiplier.
[Explanation of symbols]
10, 11 FET
10A, 11A Bipolar transistor
12 Input transmission line
13 Output transmission line
14 capacitors
15 Transmission line
16 constant voltage power supply
18 Bias resistance
20, 21 Damping resistance
22, 23 Parasitic inductance
24 Self-bias circuit
T1 input terminal
T2 output terminal

Claims (7)

An input transmission line to which an input microwave signal is supplied;
An output transmission line;
Having a first control input and the first current path, said first control input coupled to said input transmission line, a first transistor one end of the first current path is connected to the ground conductor,
A second control input and the second current path, said second control input is connected to the grounding conductor, and a second transistor which the one end of the second current path is coupled to the input transmission line,
A first damping resistor connected between the other end of the first current path and the output transmission line;
A second damping resistor connected between the other end of the second current path and the output transmission line;
Have
The ground conductor includes a ground plate , and one via that is connected to the ground plate and is formed between the first transistor and the second transistor, and includes one end of the first current path and the first current path. 2. A microwave frequency multiplier characterized in that both control input terminals are directly connected to the one via at an approximately equal distance and are conducted to the ground plate through the one via. The first transistor, the second transistor, the first damping resistor, and the second damping resistor are formed on one surface of the semi-insulating substrate, and the ground plate is formed on the other surface of the semi-insulating substrate. The microwave frequency multiplier according to claim 1, wherein the via is formed in the semi-insulating substrate. A resistance value of the second damping resistor is determined so as to suppress oscillation generated by the connection between the second transistor and the output transmission line, and is generated by circulating through the first transistor and the second transistor. 3. The micro resistance according to claim 1, wherein a resistance value of the first damping resistor is determined so as to suppress oscillation caused by a series connection of the first damping resistor and the second damping resistor. Wave frequency multiplier. A stub connected to the output transmission line and trapping a signal having a frequency twice the frequency of the input microwave signal;
The microwave frequency multiplier according to any one of claims 1 to 3, further comprising: A bias resistor having one end connected to the first control input end;
A DC blocking capacitor connected between the input transmission line and the first control input terminal;
A self-bias circuit connected between the input transmission line and the ground conductor;
The microwave frequency multiplier according to any one of claims 1 to 4, wherein the microwave frequency multiplier is provided. The first transistor has a gate as the first control input terminal, a source as the one end of the first current path, and a drain as the other end of the first current path. And
The second transistor has a gate as the second control input terminal, a source as the one end of the second current path, and a drain as the other end of the first current path. Is,
The microwave frequency multiplier according to any one of claims 1 to 5, wherein The first transistor is a first bipolar transistor having a base as the first control input terminal, an emitter as the one end of the first current path, and a collector as the other end of the first current path. Yes,
The second transistor is a second bipolar transistor having a base as the second control input terminal, an emitter as the one end of the second current path, and a collector as the other end of the first current path. is there,
The microwave frequency multiplier according to any one of claims 1 to 5, wherein

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