JP3834564B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a gate electrode including a SiGe thin film and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) as semiconductor devices have been miniaturized and highly integrated. Along with this, thinning of the gate insulating film has been promoted from the viewpoint of securing driving current and reducing power consumption.
A silicon oxide film (SiO2) that has been widely used as a gate insulating film due to the demand for scaling law₂It is necessary to form a film with a film thickness of 2 nm or less. However, such extremely thin SiO₂When the film is used as a gate insulating film, the gate leakage current due to the tunnel current becomes a value that cannot be ignored with respect to the source / drain current, which is a big problem in improving the performance and power consumption of the MOSFET.
[0003]
As a countermeasure, SiO₂A method has been proposed in which a high dielectric film having a relative dielectric constant higher than that of a film is used as a gate insulating film. Thus, the physical film thickness can be increased while the effective gate insulating film thickness (that is, the electrical equivalent film thickness) is kept thin, and the gate leakage current due to the tunnel current can be suppressed.
[0004]
On the other hand, in order to reduce the electrical equivalent film thickness of the gate electrode, a method of reducing the parasitic capacitance resulting from the depletion of the gate electrode has been proposed. For example, a silicon germanium (hereinafter referred to as “SiGe”) film is used for the gate electrode. A transistor using a SiGe film as a gate electrode has the following advantages.
First, since the activation rate of conductive impurities (for example, boron) in the gate electrode is improved, the dose of boron can be reduced. As a result, boron penetration into the gate insulating film and channel region under the gate electrode can be suppressed, and gate leakage current can be suppressed. In addition, depletion of the gate electrode is suppressed by improving the boron activation rate, and parasitic capacitance due to depletion is reduced. Accordingly, the gate insulating film can be made thicker by the amount corresponding to the parasitic capacitance, and the gate leakage current can be further suppressed.
Further, since the work function of SiGe is smaller than that of the substrate (Si) in the P-channel MOSFET, the channel concentration can be lowered when the threshold voltage (Vth) is adjusted to a desired value. As a result, the electric field in the vertical direction is reduced, so that the carrier mobility of the substrate is improved and the transistor driving capability is improved.
Furthermore, since the SiGe film has a higher growth rate than the polysilicon film conventionally used for the gate electrode, it can be formed in a short time. Further, the SiGe film can be polycrystallized at a lower temperature than Si. In order to sufficiently diffuse conductive impurities at a low temperature and in a short time, polycrystalline is more advantageous. Therefore, it is possible to reduce the thermal history of the thermal diffusion process at the time of film formation and in the subsequent process.
[0005]
By the way, in the gate electrode using the SiGe film, there is a problem that the film surface is roughened when the SiGe film is formed. When such surface roughness occurs, it becomes difficult to process the gate electrode by dry etching in a later step. In order to avoid this problem, an ultra-thin amorphous Si film (seed Si film) is made of SiGe film and SiO, which is a gate insulating film.₂A method for suppressing surface roughness of the SiGe film formed between the film and the film has been proposed (see, for example, Patent Document 1).
[0006]
[Patent Document 1]
JP 2002-261274 A (Page 5, FIG. 3)
[0007]
[Problems to be solved by the invention]
However, the introduction of the seed Si film lowers the germanium composition (hereinafter referred to as “Ge composition”) at the interface between the gate electrode and the gate insulating film that most affects the transistor characteristics.
Further, even when Ge is diffused from the SiGe film to the seed Si film by a heat treatment in a subsequent process, the Ge composition at the interface between the gate electrode and the gate insulating film after the diffusion varies due to a temperature variation in the wafer surface or the like. It will occur.
As a result, there has been a problem that it is difficult to control the Ge composition at the gate electrode-gate insulating film interface as designed. Furthermore, there is a problem in that the work function changes due to the change in the Ge composition at the gate electrode-gate insulating film interface, resulting in variations in the threshold voltage of the transistor.
[0008]
The present invention has been made to solve the above-described conventional problems, and suppresses surface roughness of the SiGe film constituting the gate electrode and improves controllability of the Ge composition at the gate electrode-gate insulating film interface. With the goal.
[0009]
[Means for solving the problems]
  A semiconductor device according to the present invention is a semiconductor device having a gate electrode including a SiGe film,
  A dielectric film formed on the substrate;
  Formed on the dielectric film, the film thickness is 0.1 nm ~0.3nm and HfO₂Substrate consisting of a filmGate insulationWith a membrane,
  The baseGate insulationThe SiGe film is formed on the film.
[0010]
  In the semiconductor device according to the present invention, theDielectric film, Silicon oxide film, silicon nitride film or silicon oxynitride filmIsIs preferred.
[0011]
  In the semiconductor device according to the present invention, theThe dielectric film includes a first dielectric film formed on the substrate and a second dielectric film formed on the first dielectric film,
  The first dielectric film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film,
  The second dielectric film is made of Al. ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , HfSiOx, ZrSiOx, HfAlOx or ZrAlOxIt is preferable that
[0012]
  In the semiconductor device according to the present invention, the gate electrode includes the baseGate insulationIt is preferable to include an amorphous SiGe film formed on the film and a polycrystalline SiGe film formed on the amorphous SiGe film.
[0013]
In the semiconductor device according to the present invention, it is preferable that the gate electrode further includes a Si film formed on the polycrystalline SiGe film.
[0014]
  In the manufacturing method according to the present invention, a step of forming a dielectric film on the substrate;
  HfO on the dielectric film₂Substrate consisting of a filmGate insulationFrom 0.1 nm0.3forming with a film thickness of nm;
  The baseGate insulationForming a SiGe film on the film;
  Patterning the SiGe film to form a gate electrode;
  Forming source / drain regions on the substrate by ion implantation using the gate electrode as a mask;
  Is preferably included.
[0015]
The manufacturing method according to the present invention further includes a step of forming a Si film on the SiGe film after forming the SiGe film,
In the step of forming the gate electrode, it is preferable to further pattern the Si film.
[0016]
  In the manufacturing method according to the present invention, the step of forming the SiGe film includes:
  The baseGate insulationForming an amorphous SiGe film on the film;
  Forming a polycrystalline SiGe film on the amorphous SiGe film;
  Is preferably included.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.
[0018]
Embodiment 1 FIG.
First, the structure of the semiconductor device according to the first embodiment of the present invention will be described.
FIG. 1 is a cross-sectional view for explaining a semiconductor device according to the first embodiment of the present invention.
As shown in FIG. 1, the silicon substrate as the substrate 2 has an element region in which a semiconductor element such as a transistor is formed, and an isolation region that isolates the element region, and a field insulating film ( Also referred to as “element isolation insulating film”) 4 is formed. Although not shown, a well region is formed in the substrate 2 in the element region.
[0019]
On the substrate 2 in the element region, a gate insulating film composed of multilayer films 6 and 8 is formed.
The lower dielectric film 6 formed immediately above the substrate 2 is, for example, SiO 2₂Film, Si₃N₄Film, SiON film (hereinafter referred to as “SiO₂"Membrane etc." ) Can be used. SiO₂The film thickness of the lower dielectric film 6 made of a film or the like is, for example, 0.7 nm.
Further, the lower dielectric film 6 is made of SiO.₂Instead of a film etc., the SiO₂A high dielectric film (High-k film) having a higher relative dielectric constant than a film or the like can be used. Here, as a material of the high dielectric film, for example, Al₂O₃, HfO₂, ZrO₂, La₂O₃Metal oxides such as, metal nitrides, metal oxynitrides, metal silicates such as HfSiOx and ZrSiOx, metal aluminates such as HfAlOx and ZrAlOx, and the like can be used. In this case, the physical film thickness can be increased, which is preferable from the viewpoint of suppressing the gate leakage current.
Further, the lower dielectric film 6 is made of SiO.₂A laminated film of the film and the high dielectric film formed thereon can be formed. That is, the gate insulating film is formed on the SiO 2 formed on the substrate 2.₂This film and this SiO₂A laminated film of the high dielectric film formed on a film or the like and a transition metal oxide film (described later) formed on the high dielectric film can be formed. In this case, the solid phase reaction between the high dielectric film and the silicon substrate 2 is performed using SiO.₂It can be suppressed by a film or the like. Moreover, it is suitable from a viewpoint of improvement of interface characteristics and suppression of gate leakage current.
[0020]
A transition metal oxide film (hereinafter referred to as “transition metal oxide film”) 8 is formed on the lower dielectric film 6. That is, the gate insulating film includes the transition metal oxide film 8 on the uppermost layer of the gate insulating film. The transition metal oxide film 8 functions as a gate insulating film and also functions as a base film for forming a SiGe film described later. As the transition metal oxide film 8, HfO₂A membrane can be used. HfO₂The film thickness of the transition metal oxide film 8 made of a film is preferably, for example, 0.1 nm (monoatomic layer) to 5 nm.
The lower dielectric film 6 is HfO.₂By using the film, the gate insulating film is changed to HfO.₂It can also be composed only of a film. In this case, HfO₂The film thickness is preferably 4 nm to 5 nm, for example.
The transition metal oxide film 8 is required to grow with good uniformity even when the transition metal oxide film 8 is made extremely thin to a thickness of about 0.3 nm or less due to thermal stability requirements, for example. Therefore, it is preferable to use the ALD method or the MOCVD method for the growth of the transition metal oxide film 8 (described later).
[0021]
On the transition metal oxide film 8, a SiGe film as the gate electrode 10 is formed. The SiGe film 10 is made of Si._(100-x)Ge_xThe Ge composition X (%) is preferably 20% to 30%. By forming the SiGe film 10 immediately above the transition metal oxide film 8, excellent flatness can be obtained without a seed Si film (described later).
[0022]
A source / drain region 12 is formed in the upper layer of the silicon substrate 2 with a channel region (not shown) below the gate electrode interposed therebetween.
[0023]
Next, a method for manufacturing the semiconductor device will be described.
FIG. 2 is a process cross-sectional view for explaining a method of manufacturing the semiconductor device shown in FIG.
First, as shown in FIG. 2A, a field insulating film 4 is formed in an isolation region of the silicon substrate 2 by using an STI (Shallow Trench Isolation) technique. Although not shown, a well region is formed by ion implantation of conductive impurities into the element region of the silicon substrate 2 and further annealing.
[0024]
Next, as shown in FIG. 2B, after performing a predetermined pretreatment (for example, removal of a natural oxide film), thermal oxidation (or thermal nitridation or thermal oxynitridation) or plasma oxidation (or plasma nitridation or SiO 2 as the lower dielectric film 6 on the silicon substrate 2 by using a method such as plasma oxynitridation).₂A film or the like (described above) is formed with a film thickness of 0.7 nm, for example.
As described above, SiO₂Instead of a film etc. or SiO₂A high dielectric film can be formed as the lower dielectric film 6 together with the film and the like. In this case, an ALD (Atomic Layer Deposition) method or a MOCVD (Metal Organic Chemical Vapor Deposition) method can be used for the growth of the high dielectric film.
[0025]
Next, HfO as the transition metal oxide film 8 is formed on the lower dielectric film 6 by using the ALD method or the MOCVD method.₂A film is formed. HfO using ALD method₂When forming a film, for example, the substrate temperature is set to 300 ° C. and HfCl₄As a raw material, H₂O or O₃Is an oxidizing agent. According to the average film formation rate per atomic layer under these conditions, HfO₂The film can be made very thin to a thickness of about 0.3 nm or less. HfO₂Even when the film 8 is made very thin, the above method can be used to perform growth with good uniformity.
[0026]
After forming the transition metal oxide film 8 and before forming a SiGe film (described later), it is preferable to perform heat treatment in an extremely small amount of oxygen atmosphere (the same applies to Embodiments 2 and 3 described later). ). HfO as the transition metal oxide film 8₂When the film is formed, for example, heat treatment is performed for several seconds at a temperature of about 800 ° C. in a lamp type rapid thermal annealing apparatus (RTA: Rapid Thermal Annealer). By this heat treatment, oxygen vacancies in the transition metal oxide film 8 are compensated, and at the same time, the impurity concentration in the transition metal oxide film 8 can be reduced.
HfO₂SiO immediately below the film 8₂When the film 6 or the like is formed, this heat treatment causes HfO₂From film 8 to SiO₂Hf diffuses into the film 6 etc., and SiO₂Since the film 6 or the like 6 becomes Hf silicate, the electrical equivalent film thickness of the lower dielectric film 6 decreases. Thereby, since the physical film thickness of the transition metal oxide film 8 can be increased, the gate leakage current can be further suppressed.
[0027]
Subsequently, using a CVD method, HfO₂The SiGe film 10 is formed on the film 8 with a film thickness of 50 nm to 150 nm, for example. Where Si_(100-x)Ge_xThe Ge composition X (%) in the SiGe film 10 represented by the composition formula is preferably 20 to 30%.
The deposition temperature of the SiGe film 10 is preferably 450 ° C. or higher and lower than 500 ° C. This is because when the film forming temperature is 500 ° C. or higher, the surface roughness of the SiGe film 10 becomes significant when the SiGe film 10 is grown without the seed Si film interposed. Further, when the film formation temperature is lower than 450 ° C., the growth rate of the SiGe film 10 is slow and the throughput is low, which is not preferable from the viewpoint of productivity.
For example, a batch type vertical LPCVD apparatus can be used to form the SiGe film 10. The growth conditions of the SiGe film 10 are, for example, SiH₄Flow rate: 1 slm; H₂Diluted 10% GeH₄Flow rate: 0.96 slm; Growth temperature: 475 ° C .; Growth pressure: 200 Pa. In this formation condition, since the film deposition rate is faster than the crystal nucleus growth rate, an amorphous SiGe film 10 can be obtained. The surface flatness of the amorphous SiGe film 10 is remarkably improved, and the maximum unevenness on the surface is reduced to about 2 nm.
[0028]
Here, the inventor investigated the surface morphology of the SiGe film when the SiGe film was formed on various dielectric films. The investigation result will be described with reference to FIGS.
[0029]
FIG. 3 shows SiO₂It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film. Specifically, FIG. 3 (a) shows SiO.₂When a SiGe film is formed on the film via a seed Si film having a thickness of 5 nm, FIG.₂It is a figure which shows each SiGe film surface in the case of forming a SiGe film directly on a film | membrane. The Ge composition x of the SiGe film is 30% and the growth condition is SiH.₄Flow rate: 1 slm; H₂Diluted 10% GeH₄Flow rate: 0.96 slm; Growth temperature: 475 ° C .; Growth pressure: 200 Pa.
As shown in FIG.₂When a SiGe film is formed on a film with a seed Si film interposed therebetween, a flat surface morphology (root mean square roughness: 1.3 nm) is achieved. On the other hand, as shown in FIG. 3B, when the seed Si film is not interposed, the crystal grains of the SiGe film are observed as projections, and the surface morphology deteriorates (root mean square roughness: 14.5 nm). ing.
[0030]
Figure 4 shows Al₂O₃It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film. Specifically, FIG. 4 (a) shows Al.₂O₃When a SiGe film is formed on the film via a seed Si film having a thickness of 5 nm, FIG.₂O₃It is a figure which shows each SiGe film surface in the case of forming a SiGe film directly on a film | membrane.
As shown in FIG.₂O₃When the SiGe film is formed on the film with the seed Si film interposed, as in the case shown in FIG. 3A, a flat surface morphology (root mean square roughness: 0.3 nm) is achieved. Yes. On the other hand, as shown in FIG. 4B, when the seed Si film is not interposed, the crystal grains of the SiGe film are observed in the shape of protrusions as in the case shown in FIG. Has deteriorated (root mean square roughness: 14.6 nm).
[0031]
FIG. 5 shows HfO₂It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film. Specifically, FIG. 5 (a) shows HfO.₂When a SiGe film is formed on the film via a seed Si film having a thickness of 5 nm, FIG.₂It is a figure which shows each SiGe film surface in the case of forming a SiGe film directly on a film | membrane.
As shown in FIGS. 5A and 5B, a flat surface morphology (both mean square roughness: 0.2 nm) is achieved regardless of the presence or absence of the seed Si film. That is, as described above, SiO₂Film or Al₂O₃Unlike the case of forming a SiGe film on the film, HfO₂It was found that when the SiGe film is formed on the film, a flat surface morphology of the SiGe film can be obtained without interposing the seed Si film.
[0032]
Next, as shown in FIG. 2C, the SiGe film 10, the transition metal oxide film 8, and the lower dielectric film 6 are sequentially patterned using a known lithography technique and etching technique. Thereby, the gate electrode of the MOSFET is formed.
Further, as shown in FIG. 2D, source / drain regions 12 are formed in the upper layer of the silicon substrate 2 by ion-implanting conductive impurities using the gate electrode as a mask.
[0033]
As described above, in the first embodiment, the transition metal oxide film 8 is formed as the uppermost layer of the gate insulating film. That is, the transition metal oxide film 8 was formed as a gate insulating film / underlayer film. Then, a SiGe film 10 was formed immediately above the transition metal oxide film 8.
Thereby, the flatness of the SiGe film surface can be ensured without forming a conventional seed Si film. Since it is not necessary to interpose the seed Si film at the gate insulating film-gate electrode interface, the Ge composition of the SiGe film at the interface can be controlled as designed, and the variation in threshold voltage in the transistor can be suppressed. Can do. Therefore, transistors with reduced variations in threshold voltage can be formed uniformly within the wafer surface.
[0034]
Further, by applying the SiGe film 10 having excellent surface flatness as described above to the gate electrode, the process margin in the subsequent gate processing step can be expanded, the processing yield can be improved, and the productivity is improved. To do.
In addition, since the SiGe film 10 is an amorphous film, channeling of conductive impurities to be implanted can be suppressed when forming the gate electrode, the source / drain region, the extension region, and the pocket region. Thus, variation in threshold voltage among transistors can be suppressed.
[0035]
In the first embodiment, the amorphous SiGe film 10 is formed. However, the present inventor forms the SiGe film by reducing only the pressure to 30 Pa or less under the above-described growth conditions of the SiGe film, and the surface thereof. The flatness was investigated. The obtained SiGe film was a polycrystalline SiGe film having a grain size as small as about 15 nm and uniform grain size. It was found that even when the polycrystalline SiGe film is formed on the transition metal oxide film, the flatness of the SiGe film surface can be secured without forming the seed Si film. Therefore, as in the case of forming an amorphous SiGe film, the Ge composition at the gate insulating film-gate electrode interface can be controlled as designed.
Further, by using such a polycrystalline SiGe film as a gate electrode, the heat treatment required for diffusion of conductive impurities (for example, boron) implanted in a later process can be further reduced, so that the gate leakage current in the transistor can be further suppressed. it can.
[0036]
Embodiment 2. FIG.
First, the structure of the semiconductor device according to the second embodiment of the present invention will be described.
FIG. 6 is a cross-sectional view for explaining a semiconductor device according to the second embodiment of the present invention.
The difference between the semiconductor device according to the second embodiment shown in FIG. 6 and the semiconductor device according to the first embodiment described above is that the amorphous SiGe film 10 is thinned and a large number of films are formed on the thinned SiGe film 10. A crystalline SiGe film 14 is further formed.
That is, as shown in FIG. 6, the semiconductor device according to the second embodiment has HfO as the gate electrode.₂An amorphous SiGe film 10 formed on the film 8 and a polycrystalline SiGe film 14 formed on the SiGe film 10 are provided.
The film thickness of the amorphous SiGe film 10 is, for example, about 20 nm to 30 nm. The film thickness of the polycrystalline SiGe film 14 may be controlled so that the film thickness of the entire gate electrode is 50 nm to 150 nm.
[0037]
Next, a method for manufacturing the semiconductor device will be described.
First, the amorphous SiGe film 10 is formed as in the manufacturing method according to the first embodiment. The amorphous SiGe film 10 is formed with a film thickness of, for example, about 20 nm to 30 nm. Even when the thickness is reduced in this way, crystal grain growth does not occur during the formation of the SiGe film, and therefore, a continuous SiGe film 10 can be formed at the gate insulating film-gate electrode interface.
[0038]
Next, although not shown, a polycrystalline SiGe film 14 is formed on the SiGe film 10 using LPCVD. For the formation of the SiGe film 14, the above-described batch type vertical LPCVD apparatus can be used. The growth condition of the SiGe film 14 is, for example, SiH.₄Flow rate: 0.6 slm; H₂Diluted 10% GeH₄Flow rate: 0.58 slm; growth temperature: 475 ° C., growth pressure: 10 Pa.
The SiGe film 14 formed under such conditions becomes a polycrystalline film despite the same growth temperature as the amorphous SiGe film 10. Further, since the amorphous SiGe film 10 and the polycrystalline SiGe film 14 are formed at the same growth temperature, the quality of the amorphous SiGe film 10 is maintained during the growth of the polycrystalline SiGe film 14. Further, since the SiGe films 10 and 14 can be continuously grown in the same LPCVD apparatus, the throughput and productivity are not lowered.
[0039]
Next, similarly to the first embodiment, the polycrystalline SiGe film 14, the amorphous SiGe film 10, the transition metal oxide film 8, and the lower dielectric film 6 are sequentially formed using a known lithography technique and etching technique. Pattern. Thereby, the gate electrode of the MOSFET is formed. Further, as in the first embodiment, source / drain regions 12 are formed in the upper layer of the silicon substrate 2 by ion-implanting conductive impurities using the gate electrode as a mask.
[0040]
As described above, in the second embodiment, the transition metal oxide film 8 is formed as the uppermost layer of the gate insulating film. That is, the transition metal oxide film 8 was formed as a gate insulating film / underlayer film. Then, a SiGe film 10 was formed immediately above the transition metal oxide film 8. Therefore, the same effect as in the first embodiment can be obtained.
[0041]
Further, in the second embodiment, the polycrystalline SiGe film 14 is formed on the thin amorphous SiGe film 10. As a result, the conductive impurities (for example, boron) implanted into the gate electrode in the subsequent process can be efficiently thermally diffused using the accelerated diffusion phenomenon along the polycrystalline crystal grain boundary. Therefore, the lower dielectric film 6 and HfO₂The thermal history of the subsequent process can be reduced with respect to the film 8, and the electrical characteristics such as leakage current characteristics and long-term reliability of the gate insulating films 6 and 8 are improved. Therefore, since the reliability of the transistor element is improved, the yield is improved and the productivity is improved.
[0042]
In the second embodiment, the polycrystalline SiGe film 14 is formed on the amorphous SiGe film 10, but a polycrystalline Si film may be formed instead of the polycrystalline SiGe film 14. Also in this case, the conductive impurities injected into the gate electrode can be efficiently diffused by utilizing the enhanced diffusion phenomenon.
[0043]
Embodiment 3 FIG.
First, the structure of the semiconductor device according to the third embodiment of the present invention will be described.
FIG. 7 is a cross-sectional view for explaining a semiconductor device according to the third embodiment of the present invention.
The difference between the semiconductor device according to the third embodiment shown in FIG. 7 and the semiconductor device according to the second embodiment described above is that an Si film (hereinafter referred to as “cap Si film”) is formed on the polycrystalline SiGe film 14. 16 is further formed.
That is, as shown in FIG. 7, the semiconductor device according to the third embodiment has HfO as the gate electrode.₂An amorphous SiGe film 10 formed on the film 8, a polycrystalline SiGe film 14 formed on the SiGe film 10, and a cap Si film 16 formed on the SiGe film 14 were provided. Is.
The film thickness of the amorphous SiGe film 10 is, for example, about 20 nm to 30 nm, as in the second embodiment. The film thicknesses of the polycrystalline SiGe film 14 and the cap Si film 16 may be controlled so that the film thickness of the entire gate electrode is 50 nm to 150 nm. In FIG. 7, the cap Si film 16 is thicker than the SiGe film 14, but the SiGe film 14 may be thicker.
[0044]
Next, a method for manufacturing the semiconductor device will be described.
First, the polycrystalline SiGe film 14 is formed as in the manufacturing method according to the second embodiment. The film thickness of the polycrystalline SiGe film 14 is made thinner than that of the second embodiment in consideration of the film thickness of a cap Si film 16 described later.
[0045]
Next, although not shown, a cap Si film 16 is formed on the SiGe film 14 using the LPCVD method. The above-described batch type vertical LPCVD apparatus can be used to form the cap Si film 16, and a temperature higher than the growth temperature of the SiGe film 14 can be applied. The growth condition of the cap Si film 16 is, for example, SiH₄Flow rate: 1 slm; growth temperature: 530 ° C., growth pressure: 100 Pa.
Since the cap Si film 16 is grown under the influence of the crystallinity of the polycrystalline SiGe film 14, many regions are grown to be polycrystalline. Here, in order to grow the polycrystalline Si film, a high temperature of 600 ° C. or higher is usually required. Crystallize.
[0046]
As described above, in the third embodiment, the transition metal oxide film 8 is formed as the uppermost layer of the gate insulating film. That is, the transition metal oxide film 8 was formed as a gate insulating film / underlayer film. Then, a SiGe film 10 was formed immediately above the transition metal oxide film 8. Therefore, the same effect as in the first embodiment can be obtained.
[0047]
Further, in the third embodiment, the polycrystalline cap Si film 16 is formed on the polycrystalline SiGe film 14. Thereby, as in the second embodiment, the conductive impurities (for example, boron) implanted in the subsequent process can be efficiently thermally diffused using the accelerated diffusion phenomenon along the polycrystalline grain boundary. Can do. Therefore, the lower dielectric film 6 and HfO₂The thermal history of the subsequent process can be reduced with respect to the film 8, and the electrical characteristics such as leakage current characteristics and long-term reliability of the gate insulating films 6 and 8 are improved. Therefore, since the reliability of the transistor element is improved, the yield is improved and the productivity is improved.
Further, by forming the cap Si film 16 on the polycrystalline SiGe film 14, a salicide defect caused by Ge in the SiGe film is avoided when a salicide wiring is formed in a later process using a known salicide process. be able to. For this reason, a yield improves and productivity improves.
Further, since the cap Si film 16 can be polycrystallized at a lower temperature than usual by interposing the polycrystalline SiGe film 14, the lower dielectric film 6 and the HfO₂The thermal history of the post-process can be further reduced with respect to the film 8, and the electrical characteristics such as the leakage current characteristics and long-term reliability of the gate insulating films 6 and 8 are improved. Therefore, since the reliability of the transistor element is improved, the yield is improved and the productivity is improved.
In the cleaning process performed after introducing impurities into the gate electrode, the Si film has a lower etching rate than the SiGe film. Therefore, a reduction in the thickness of the gate electrode in the cleaning process can be reduced as compared with Embodiments 1 and 2, and a reduction in the conductive impurity concentration in the gate electrode and a variation in the in-plane distribution can be suppressed. Therefore, the transistor can be manufactured as designed, and the production reproducibility and stability are improved.
[0048]
Next, a modification of the third embodiment will be described. The following modifications can be used depending on the performance required for the transistor.
FIG. 8 is a cross-sectional view for explaining a first modification of the third embodiment of the present invention, and FIG. 9 is a cross-sectional view for explaining a second modification of the third embodiment of the present invention. is there.
[0049]
In the first modification, as shown in FIG. 8, an extension 22 is formed by implanting impurities using a gate electrode made of multilayer films 10, 14, and 16 as a mask, and a sidewall 20 is formed so as to cover the sidewall of the gate electrode. The source / drain regions 12 having an impurity concentration higher than that of the extension 22 are formed by implanting impurities using the gate electrode and the sidewall 20 as a mask.
[0050]
As shown in FIG. 9, the second modified example is formed after forming the structure of the first modified example shown in FIG. 8 and then forming a protective film (not shown), for example, Co film, Ni film, Ta film, Ti A metal film such as a film is formed, and a heat treatment is performed to form a metal silicide layer 24 such as CoSi on the surface layer of the cap Si film 16 and the source / drain regions 12. That is, after the structure of the first modification is formed, the metal silicide layer 24 is formed by the salicide method. According to the second modification, the resistance of the diffusion layer can be reduced.
With the first and second modifications, the performance of the semiconductor device can be further improved.
[0051]
【The invention's effect】
According to the present invention, the surface roughness of the SiGe film constituting the gate electrode can be suppressed, and the controllability of the Ge composition at the gate electrode-gate insulating film interface can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a process sectional view for explaining the method for manufacturing the semiconductor device shown in FIG. 1;
[Fig. 3] SiO₂It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film.
[Fig.4] Al₂O₃It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film.
FIG. 5 HfO₂It is a microscope picture which shows the surface morphology of a SiGe film at the time of forming a SiGe film on a film.
FIG. 6 is a cross-sectional view for explaining a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining a semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a cross-sectional view for explaining a first modification of the third embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining a second modification of the third embodiment of the present invention.
[Explanation of symbols]
2 Substrate (silicon substrate)
4 Field insulation film
6 Lower dielectric film (SiO₂Membrane)
8 Transition metal oxide film (HfO₂film)
10 SiGe film
12 Source / drain regions
14 SiGe film (polycrystalline SiGe film)
16 Si film (cap Si film)
20 sidewall
22 Extension
24 Metal silicide layer

Claims (9)

A semiconductor device having a gate electrode including a SiGe film,
A dielectric film formed on the substrate;
A base gate insulating film formed on the dielectric film, having a thickness of 0.1 nm to 0.3 nm and made of an HfO ₂ film;
A semiconductor device, wherein the SiGe film is formed on the base gate insulating film. The semiconductor device according to claim 1,
A semiconductor device, wherein the dielectric film is a lower dielectric film made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The semiconductor device according to claim 1,
The dielectric film includes a first dielectric film formed on the substrate and a second dielectric film formed on the first dielectric film,
The first dielectric film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film,
The semiconductor device, wherein the second dielectric film is a film made of Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , HfSiOx, ZrSiOx, HfAlOx, or ZrAlOx. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein the gate electrode includes an amorphous SiGe film formed on the base gate insulating film and a polycrystalline SiGe film formed on the amorphous SiGe film. The semiconductor device according to claim 4,
The semiconductor device, wherein the gate electrode further comprises a Si film formed on the polycrystalline SiGe film. Forming a dielectric film on the substrate;
Forming a base gate insulating film made of an HfO ₂ film with a thickness of 0.1 nm to 0.3 nm on the dielectric film;
Forming a SiGe film on the underlying gate insulating film;
Patterning the SiGe film to form a gate electrode;
Forming source / drain regions on the substrate by ion implantation using the gate electrode as a mask;
A method for manufacturing a semiconductor device, comprising: The manufacturing method according to claim 6,
Forming a Si film on the SiGe film after forming the SiGe film;
The method of manufacturing a semiconductor device, wherein in the step of forming the gate electrode, the Si film is further patterned. In the manufacturing method of Claim 6 or 7,
The step of forming the SiGe film includes
Forming an amorphous SiGe film on the underlying gate insulating film;
Forming a polycrystalline SiGe film on the amorphous SiGe film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method in any one of Claim 6 to 8,
A method of manufacturing a semiconductor device, wherein the SiGe film is formed at a temperature of 450 ° C. or higher and lower than 500 ° C.

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