JP3834673B2

JP3834673B2 - Power regulator circuit

Info

Publication number: JP3834673B2
Application number: JP2001385459A
Authority: JP
Inventors: 光治大田; 智至中野; 泰生樋口
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2001-12-19
Filing date: 2001-12-19
Publication date: 2006-10-18
Anticipated expiration: 2021-12-19
Also published as: JP2003186555A

Description

【０００１】
【発明の属する技術分野】
本発明は、電源レギュレータ回路に係り、過大電流による破壊を防ぐ電流制限回路を有した電源レギュレータ回路に関するものである。
【０００２】
【従来の技術】
従来の電源レギュレータ回路は、図４に示す回路図のように構成されている。図４において、１は電源端子、２は接地端子、３は出力端子、４は基準電圧源、５は増幅器、６は出力トランジスタである第１ＰチャンネルＭＯＳＦＥＴ（以下、Ｐ−ＭＯＳＦＥＴという）、７，８は出力電圧設定用の第１，第２抵抗、９は負荷電流検出用の抵抗、１０は電流検出用のＰＮＰトランジスタである。
【０００３】
図４に示す電源レギュレータ回路は、出力端子３と接地端子２との間に第１抵抗７および第２抵抗８の直列に接続して、その抵抗分割点の電圧と基準電圧源４の電圧を第１増幅器５によって比較し、この比較出力により第１Ｐ−ＭＯＳＦＥＴ６を駆動、出力端子３に接続される負荷（図示せず）に負荷電流を供給する。出力端子３の出力電圧Ｖｏは、第１増幅器５，第１Ｐ−ＭＯＳＦＥＴ６および第１抵抗７，第２抵抗８の直列回路を介して第１増幅器５のプラス入力に帰還して構成される負帰還ループによって安定化される。
【０００４】
ここで、基準電圧源４の電圧をＶref、第１抵抗７の抵抗値をＲ７、第２抵抗８の抵抗値をＲ８とすれば、出力電圧Ｖｏは次の(数１)で表すことができる。
【０００５】
【数１】
Ｖｏ＝Ｖref（Ｒ７＋Ｒ８）／Ｒ８
次に、電流検出用のＰＮＰトランジスタ１０および抵抗９で構成される電流制限回路は、負荷電流が大きくなりすぎて、負荷電流を供給する第１Ｐ−ＭＯＳＦＥＴ６が破壊されることを防ぐために設けられている。この抵抗９の電圧降下がＰＮＰトランジスタ１０のベース・エミッタ間電圧Ｖbe（約０．７Ｖ）より大きくなるとＰＮＰトランジスタ１０が導通し、第１Ｐ−ＭＯＳＦＥＴ６のゲート・ソース間の電圧を小さくして、第１Ｐ−ＭＯＳＦＥＴ６をオフする方向に動作させて、負荷電流を制限するように動作する。
【０００６】
ここで、出力電圧Ｖｏ＝２Ｖに設定した場合、従来の電源レギュレータ回路の動作特性を図３の破線Ｃで示す。
【０００７】
【発明が解決しようとする課題】
しかしながら、このような構成の電源レギュレータ回路は、図４に示す第１Ｐ−ＭＯＳＦＥＴ６に流れる負荷電流を検出するために、直列に抵抗９を接続すると、抵抗９の端子間に電圧降下が生じることになる。過大な負荷電流のときに電流を検出して、かつ通常の動作時には抵抗９の電圧降下があまり影響しないようにするためには、抵抗９の抵抗値を小さな値に選択する必要がある。
【０００８】
しかしながらそれは、電流制限機能を大きな電流値で機能させることになり、負荷がショートした場合には第１Ｐ−ＭＯＳＦＥＴ６に電源入力の殆どの電圧が印加されることになり、第１Ｐ−ＭＯＳＦＥＴ６の許容損失をオーバーして、第１Ｐ−ＭＯＳＦＥＴ６が破壊されるような不都合があった。
【０００９】
また、電流検出のために設ける抵抗９の電圧降下は避けられず、電源利用効率が必ずしも良くないという点においても問題があった。
【００１０】
本発明は、前記従来技術の問題を解決することに指向するものであり、出力トランジスタと直列に電流検出抵抗を接続せずに、過大な負荷電流を制限すると共に、電源電圧の利用効率が良い電源レギュレータ回路を提供することを目的とする。
【００１１】
【課題を解決するための手段】
この目的を達成するために、本発明に係る電源レギュレータ回路は、基準電圧源とマイナス入力を接続した第１増幅器と、第１増幅器の出力とゲート、電源端子とソース、および出力端子とドレインを接続した負荷電流を供給する第１ＰチャンネルＭＯＳＦＥＴと、出力端子と接地端子間に直列接続される第１，第２抵抗とを有し、第１抵抗と第２抵抗の接続点に第１増幅器のプラス入力を接続した電源レギュレータ回路において、第１ＰチャンネルＭＯＳＦＥＴとカレントミラーを構成し、ドレインを第３抵抗を介して出力端子に接続した第２ＰチャンネルＭＯＳＦＥＴと、第３抵抗における第２ＰチャンネルＭＯＳＦＥＴのドレイン側にソース、出力端子側にゲートを接続した第３ＰチャンネルＭＯＳＦＥＴと、第３ＰチャンネルＭＯＳＦＥＴのドレイン、および第４，第５抵抗を介して接地端子とベース、第６抵抗を介して電源端子とコレクタ、接地端子とエミッタとを接地した第１ＮＰＮトランジスタと、第１ＮＰＮトランジスタのコレクタとゲート、電源端子とソース、第１ＰチャンネルＭＯＳＦＥＴのゲートとドレインとを接続した第４ＰチャンネルＭＯＳＦＥＴと、基準電圧源とプラス入力、出力端子とマイナス入力、第４抵抗と第５抵抗の接続点と出力とを接続した第２増幅器と、第１ＰチャンネルＭＯＳＦＥＴとカレントミラーを構成し、第７抵抗を介してドレインを出力端子に接続した第５ＰチャンネルＭＯＳＦＥＴと、第７抵抗における第５ＰチャンネルＭＯＳＦＥＴのドレイン側にソース、出力端子側にゲートを接続した第６ＰチャンネルＭＯＳＦＥＴとを備え、第６ＰチャンネルＭＯＳＦＥＴのドレイン電流を第２増幅器のバイアス電流としたことを特徴とする。
【００１４】
さらに、前記第６ＰチャンネルＭＯＳＦＥＴに代えてＰＮＰトランジスタを用いたことを特徴とする。
【００１５】
また、基準電圧源とマイナス入力を接続した第１増幅器と、第１増幅器の出力とゲート、電源端子とソース、および出力端子とドレインを接続した負荷電流を供給する第１ＰチャンネルＭＯＳＦＥＴと、出力端子と接地端子間に直列接続される第１，第２抵抗とを有し、第１抵抗と第２抵抗の接続点に第１増幅器のプラス入力を接続した電源レギュレータ回路において、プラス入力を第８抵抗を介して電源端子と接続すると共に定電流源を介して接地し、マイナス入力を第９抵抗を介して電源端子と接続した第２増幅器と、第１Ｐ−ＭＯＳＦＥＴのゲート，ドレインと共通にゲート，ドレインのそれぞれを接続し、第２増幅器のマイナス入力とソースを接続した第７Ｐ−ＭＯＳＦＥＴと、ベースを第２増幅器の出力と接続すると共に直列接続した第４，第５抵抗を介して接地し、コレクタを第６の抵抗を介して電源端子、エミッタを第１０抵抗を介して接地端子と接続した第１ＮＰＮトランジスタと、第１ＮＰＮトランジスタのコレクタとゲート、電源端子とソース、第１Ｐ−ＭＯＳＦＥＴのゲートとドレインとを接続した第４Ｐ−ＭＯＳＦＥＴと、電源端子とコレクタ，ベースを接続しダイオード接続した第２ＮＰＮトランジスタと、第２ＮＰＮトランジスタのエミッタとソース、第１Ｐ−ＭＯＳＦＥＴのゲートとゲートとを接続した第８Ｐ−ＭＯＳＦＥＴと、プラス入力を基準電圧源と直列接続された第１１，第１２抵抗の接続点、マイナス入力を出力端子、および出力を直列接続した第４，第５抵抗の接続点と接続した第３増幅器とを備え、第８Ｐ−ＭＯＳＦＥＴのドレイン電流を第３増幅器のバイアス電流としたことを特徴とする。
【００１６】
さらに、前記第４のＭＯＳＦＥＴに代えてＰＮＰトランジスタを用いたことを特徴とする。
【００１７】
前記構成によれば、無負荷時のバイアス電流が増加せず、電源電圧利用率を悪化させず、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴが破壊する過電流を制限でき、負荷ショート時の負荷電流および消費電力を低減し、破壊から保護でき、さらに、電源電圧と出力電圧の差が少ないときには、過剰な電流制限が働かずに、負荷供給用の第１Ｐ−ＭＯＳＦＥＴの能力を十分発揮できる。
【００１８】
【発明の実施の形態】
以下、図面を参照して本発明における実施の形態を詳細に説明する。
【００１９】
図１は本発明の実施の形態１における電源レギュレータ回路の回路例を示す図である。ここで、前記従来例を示す図４において説明した構成部材に対応し同等の機能を有するものには同一の符号を付してこれを示し、以下の各図においても同様とする。本実施の形態１の電源レギュレータ回路の動作を図１を参照しながら説明する。
【００２０】
電源端子１に接続した定電流源１１から基準電圧源４に定電流を流して、基準電圧を第１増幅器５のマイナス入力に接続する。負荷電流供給用の出力トランジスタである第１Ｐ−ＭＯＳＦＥＴ６のゲートは第１増幅器５の出力に接続し、ソースは電源端子１に接続する。また、ドレインは出力端子３に接続すると共に、第１抵抗７を介して第１増幅器５のプラス入力に接続、さらに、第１増幅器５のプラス入力から第２抵抗８を介して接地端子２に接続する。
【００２１】
第１Ｐ−ＭＯＳＦＥＴ６とゲート，ソースをそれぞれ共通とするカレントミラーに接続した第２Ｐ−ＭＯＳＦＥＴ１２のドレインを、第３抵抗１３を介して出力端子３に接続すると共に、第３Ｐ−ＭＯＳＦＥＴ１４のソースに接続する。さらに、第３Ｐ−ＭＯＳＦＥＴ１４のゲートを出力端子３に接続する。また、第３Ｐ−ＭＯＳＦＥＴ１４のドレインを、エミッタを接地端子２に接続した第１ＮＰＮトランジスタ１５のベースに接続すると共に、直列接続した第４，第５抵抗１６，１７を介して接地端子２に接続する。
【００２２】
また、第１ＮＰＮトランジスタ１５のコレクタを、電源端子１と一端を接続した第６抵抗１８の他端に接続すると共に、ソースを電源端子１に接続した第４Ｐ−ＭＯＳＦＥＴ１９のゲートと接続し、第４Ｐ−ＭＯＳＦＥＴ１９のドレインは第１Ｐ−ＭＯＳＦＥＴ６のゲートと接続する。
【００２３】
さらに、前記の構成に加え、第１Ｐ−ＭＯＳＦＥＴ６とゲート，ソースをそれぞれ共通接続した第５Ｐ−ＭＯＳＦＥＴ２０のドレインを第７抵抗２１を介して出力端子３に接続すると共に、第６Ｐ−ＭＯＳＦＥＴ２２のソースに接続する。さらに第６Ｐ−ＭＯＳＦＥＴ２２のゲートを出力端子３に、ドレインを第８抵抗２３を介して、第２増幅器５’を構成するカレントミラーに接続したＮＰＮトランジスタ２４のコレクタ、およびＮＰＮトランジスタ２５のベースと共通接続した接続点に接続する。
【００２４】
ＮＰＮトランジスタ２４，２５のエミッタはそれぞれ接地端子２に接続され、カレントミラーを構成するＮＰＮトランジスタ２５のコレクタを差動増幅回路を構成するＮチャンネルＭＯＳＦＥＴ（以下、Ｎ−ＭＯＳＦＥＴという）のＮ−ＭＯＳＦＥＴ２６，２７のソースに接続し、Ｎ−ＭＯＳＦＥＴ２６のプラス入力となるゲートを基準電圧源４に接続、Ｎ−ＭＯＳＦＥＴ２７のマイナス入力となるゲートを出力端子３と接続する。
【００２５】
そして、差動増幅回路を構成するＮ−ＭＯＳＦＥＴ２６のドレインを、アクティブ負荷を構成するＰ−ＭＯＳＦＥＴ２８のドレイン，ゲートの共通接続点に接続し、さらにＰ−ＭＯＳＦＥＴ２８のソースはＰ−ＭＯＳＦＥＴ２９のソースと共に電源端子１と接続する。Ｐ−ＭＯＳＦＥＴ２９のゲートは、Ｐ−ＭＯＳＦＥＴ２８のゲート，ドレインと接続され、Ｐ−ＭＯＳＦＥＴ２９のドレイン（第２増幅器５’の出力）は、Ｎ−ＭＯＳＦＥＴ２７のドレインに接続すると共に、直列接続した第４，第５抵抗１６，１７の接続点と接続する。
【００２６】
第１Ｐ−ＭＯＳＦＥＴ６と第２Ｐ−ＭＯＳＦＥＴ１２および第５Ｐ−ＭＯＳＦＥＴ２０はカレントミラーの関係にある。また、差動増回路を構成するＮ−ＭＯＳＦＥＴ２６，２７およびＰ−ＭＯＳＦＥＴ２９，２９により第２増幅器５’を構成している。
【００２７】
以上のような構成により、第１増幅器５のマイナス入力の電圧とプラス入力の電圧値が等しい値になるよう制御され出力電圧Ｖｏは、
【００２８】
【数２】
Ｖｏ＝Ｖref（Ｒ７＋Ｒ８）／Ｒ８
Ｖref：基準電圧源の電圧、Ｒ７：第１抵抗の抵抗値、Ｒ８：第２抵抗の抵抗値
となり、（数２）が成立する。
【００２９】
例えば、何らかの理由で出力端子３の電圧が低下した場合、直列接続の第１，第２抵抗７，８の接続点、つまり、第１増幅器５のプラス入力の電圧も低下することで、プラス入力の電圧がマイナス入力の電圧より低下して、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧が低下し、ソース，ゲート間電圧が大きくなる。これにより負荷電流を増大する方向に動作して、出力端子３の電圧が増加する。その結果、第１増幅器５のプラス入力の電圧も増加しプラス入力の電圧とマイナス入力電圧が等しくなるよう動作する。
【００３０】
前記の動作説明とは逆に、プラス入力の電圧が、マイナス入力の電圧より高くなった場合は、前記の説明とは逆方向に動作し、同様にプラス入力の電圧とマイナス入力の電圧が等しくなる動作が実行される。
【００３１】
さらに、負荷電流が増加して、第１Ｐ−ＭＯＳＦＥＴ６とカレントミラーを構成する第２Ｐ−ＭＯＳＦＥＴ１２のドレイン電流も増加し、第３抵抗１３の電圧降下が第３Ｐ−ＭＯＳＦＥＴ１４のゲート，ソース間閾値電圧ＶＴを超えると第３Ｐ−ＭＯＳＦＥＴ１４のドレイン電流が流れ、第４，第５抵抗１６，１７の電圧降下が、第１ＮＰＮトランジスタ１５のベース，エミッタ間電圧Ｖbeより大きくなると第１ＮＰＮトランジスタ１５のコレクタ電流が流れ、第６抵抗１８に電圧降下が発生し第４Ｐ−ＭＯＳＦＥＴ１９の閾値電圧ＶＴを超えるとドレイン電流が流れ、第１増幅器５および接続されている第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧を上昇させ、第１Ｐ−ＭＯＳＦＥＴ６のドレイン電流である負荷電流を制限する動作が実行される。
【００３２】
また、第１Ｐ−ＭＯＳＦＥＴ６とカレントミラーを構成する第５Ｐ−ＭＯＳＦＥＴ２０にもドレイン電流が流れ、第７抵抗２１の電圧降下が第６Ｐ−ＭＯＳＦＥＴ２２ののゲート，ソース間閾値電圧ＶＴを超えると第６Ｐ−ＭＯＳＦＥＴ２２にドレイン電流が流れ、ＮＰＮトランジスタ２４，２５のカレントミラーにより、差動増幅回路を構成するＮ−ＭＯＳＦＥＴ２６，２７のソース電流としてバイアス電流が供給される。
【００３３】
さらに負荷電流を増加すると、前記説明のように、負荷電流が制限されているため出力電圧が低下する。この出力電圧が基準電圧源４の電圧より低下するとＮ−ＭＯＳＦＥＴ２６，２７で構成する差動増幅回路のＮ−ＭＯＳＦＥＴ２６，Ｐ−ＭＯＳＦＥＴ２８がＯＮとなりＰ−ＭＯＳＦＥＴ２８，２９のカレントミラー構成によりＰ−ＭＯＳＦＥＴ２９のドレイン電流が、直列接続された第４，第５抵抗１６，１７の接続点に流れ第１ＮＰＮトランジスタ１５のベース電圧を上昇させて、コレクタ電流を増加させ、第４Ｐ−ＭＯＳＦＥＴ１９のドレイン電流が増加し、第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧を上昇させて、さらに負荷電流を減少させる。
【００３４】
ここで、第３Ｐ−ＭＯＳＦＥＴ１４およびバイアス電流供給用の第６Ｐ−ＭＯＳＦＥＴ２２が動作するまでは、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６とソース，ゲートが共通に接続されている（カレントミラーが構成される）第２，第５Ｐ−ＭＯＳＦＥＴ１２，２０ともドレインが出力端子３に接続されているため、すべて負荷電流として供給され、バイアス電流は増加せず、すべて無駄なく有効に供給される。
【００３５】
以上に説明した実施の形態１である電源レギュレータ回路の動作特性を図３の実線Ａで示す。従来の破線Ｃに比較して電流検出抵抗による損失が無いため、電源電圧を有効に使用でき、負荷電流を多く供給できる。また、出力電圧が電流制限で基準電圧以下に低下すると、さらに負荷電流を制限するため、負荷電流を大幅に減少でき消費電力の減少が可能となる。この機能は、負荷がショートした場合の保護に有効である。
【００３６】
なお、前記説明において、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６とカレントミラーを構成する第２，第５Ｐ−ＭＯＳＦＥＴ１２，２０のドレイン電流検出用の第３，第７抵抗１３，２１に接続し動作させる素子として、Ｐ−ＭＯＳＦＥＴを用いて説明したが、ＰＮＰトランジスタを用いても同様の効果が得られることは説明するまでもない。
【００３７】
図２は本発明の実施の形態２における電源レギュレータ回路の回路例を示す図である。本実施の形態２の電源レギュレータ回路の動作を図２を参照しながら説明する。
【００３８】
図２に示す本実施の形態２に係る電源レギュレータ回路について、前記した実施の形態１の図１と異なるところは、負荷電流の制限を検出する第１ＮＰＮトランジスタ１５のベースに、差動増幅回路を構成するＰ−ＭＯＳＦＥＴ３１，３２およびＮ−ＭＯＳＦＥＴ３３，３４の出力に相当するＰ−ＭＯＳＦＥＴ３１のドレインが接続され、また差動増幅回路のプラス入力であるＮ−ＭＯＳＦＥＴ３４のゲートが、定電流源３５の電流により第８抵抗２３の電圧降下部分（第８抵抗の他端）に接続されていることと、出力端子３の電圧が電流制限により低下した場合に、さらに負荷電流を減少させる第３増幅器３６のプラス入力に、基準電圧源４を第１１，第１０抵抗３７，３８で分割して入力されることが主な相違点である。
【００３９】
図２に示す電源レギュレータ回路の特徴は、電源電圧から第８抵抗２３の電圧降下分の電圧まで第９抵抗３９の電圧降下が発生しないと電流制限が動作しないことである。電源端子１より入力される電源電圧をＶinとし、出力端子３の出力電圧をＶｏとし、負荷電流をＩoutとすると、回路全体の消費電力Ｐｏはほぼ（数３）のようになる。
【００４０】
【数３】
Ｐｏ＝（Ｖin−Ｖｏ）・Ｉout
電源端子１の電源電圧と出力電圧の差が少ない場合は、消費電力が少なくなり電流制限の必要性も少なく、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６の電流能力を十分発揮する方が高性能な特性が得られる。第１Ｐ−ＭＯＳＦＥＴ６とゲートおよびドレインが共通に接続されている第７Ｐ−ＭＯＳＦＥＴ４０の大きさの比率であるＷ／Ｌを変えて、第１Ｐ−ＭＯＳＦＥＴ６を大きく、第７Ｐ−ＭＯＳＦＥＴ４０を小さく設定する。第１Ｐ−ＭＯＳＦＥＴ６は負荷電流供給用であるため当然大きくなり、第７Ｐ−ＭＯＳＦＥＴ４０は小さくてよいため、小さい面積でよいことから集積回路とした場合の面積効率が良くなる。
【００４１】
電源電圧と出力電圧の差が少ない場合、第７Ｐ−ＭＯＳＦＥＴ４０のドレイン電流は、第１Ｐ−ＭＯＳＦＥＴ６に比較して非常に少なく、差動増幅回路を構成するＮ−ＭＯＳＦＥＴ３３のゲート電圧が、Ｎ−ＭＯＳＦＥＴ３４のゲート電圧より低下せず、したがって電流制限の動作は行なわない。
【００４２】
以下に説明する回路動作において、第１増幅器５の動作は従来と同じなので省略する。負荷電流が増加していく場合、電流制限動作をしない限り負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６のゲート，ソース間電圧Ｖgsは大きくなる。
【００４３】
【数４】
Ｖgs＝Ｖbe４１＋ＶＴ４２
ここで、Ｖbe４１は第２ＮＰＮトランジスタ４１のベース，エミッタ間電圧、ＶＴ４２は第８Ｐ−ＭＯＳＦＥＴ４２の閾値電圧である。
【００４４】
第１Ｐ−ＭＯＳＦＥＴ６のゲート，ソース間電圧Ｖgsが大きくなり、第８Ｐ−ＭＯＳＦＥＴ４２の閾値電圧に達すると、第８Ｐ−ＭＯＳＦＥＴ４２にドレイン電流が流れ、第３増幅器３６にバイアス電流が流れて、動作状態に設定される。また、定電流源３０，３５においてもこのドレイン電流に基づき設定すれば、負荷電流が少ない場合にバイアスの大幅な低減が可能である。
【００４５】
さらに、負荷電流が増加し、第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧も低下して、電源電圧と出力電圧の差電圧がある程度発生している場合、第８Ｐ−ＭＯＳＦＥＴ４２のソースおよびドレイン電流も増加し、第９抵抗３９に電圧降下が発生し、この第９抵抗３９の電圧降下が、第８抵抗２３の電圧降下より大きくなれば、Ｎ−ＭＯＳＦＥＴ３３がＯＦＦ、Ｎ−ＭＯＳＦＥＴ３４がＯＮとなり、カレントミラーを構成するＰ−ＭＯＳＦＥＴ３１，３２にドレイン電流が流れ、第１ＮＰＮトランジスタ１５のベース，エミッタ間電圧Ｖbeが上昇し、約０．７Ｖ以上になるばコレクタ電流が流れ、第４Ｐ−ＭＯＳＦＥＴ１９のゲート電圧が低下してドレイン電流が流れ、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧が上昇し、負荷電流を減少する電流制限動作を実行する。さらに負荷電流を増加させると電流制限のため出力電圧が低下する。
【００４６】
出力端子３の電圧が第３増幅器３６のプラス入力の電圧、つまり基準電圧源４を第１１，第１２抵抗３７，３８で分割した電圧より低下すると、第３増幅器３６の出力が高くなり、第４抵抗１６を介して第１ＮＰＮトランジスタ１５のベース電圧が高くなり、第１ＮＰＮトランジスタ１５のコレクタ電流が増加し第４Ｐ−ＭＯＳＦＥＴ１９のゲート電圧をさらに下げることによりドレイン電流を増加させて、負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６のゲート電圧をさらに上昇させて、負荷電流をさらに減少させて制限する。
【００４７】
前記の説明では第１ＮＰＮトランジスタ１５のコレクタ電流により動作する素子として、第４Ｐ−ＭＯＳＦＥＴ１９を示して説明したが、これに代えてＰＮＰトランジスタとしても同様の動作を行って、同様の効果が得られることは説明するまでもない。
【００４８】
前記に説明した実施の形態２である電源レギュレータ回路の動作特性を図３の一点鎖線Ｂで示す。電源端子１の電源電圧と出力端子３の出力電圧との電圧差が少ない場合、電流制限回路が動作せず負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴ６の能力を十分に活かして、出力電圧が一定に制御できる負荷電流を大きく取ることができる。しかもバイアス電流は、本実施の形態の図１に示す回路例と同じで、無負荷時は、２０μＡ以下のわずかなバイアス電流で動作し、負荷電流供給用のＭＯＳＦＥＴ保護のための電流制限回路、さらに負荷ショート保護回路を追加しても増加せず、電源電圧と出力電圧の差が少ない場合は、負荷電流供給用のＭＯＳＦＥＴの能力を十分発揮できる電流制限回路を有する電源レギュレータ回路を実現できる。
【００４９】
【発明の効果】
以上説明したように、本発明によれば、無負荷時のバイアス電流が増加することなく、また電源電圧利用率が悪化することもなく、さらに負荷電流供給用の第１Ｐ−ＭＯＳＦＥＴが破壊するような過電流を制限することができ、負荷ショート時の負荷電流および消費電力を低減し、また破壊から保護できる。さらにまた、電源電圧と出力電圧の差が少ない場合は、過剰な電流制限が働かず、負荷供給用の第１Ｐ−ＭＯＳＦＥＴの能力を十分発揮でき、産業上の利用価値が大きな電流制限回路を有する電源レギュレータ回路が実現できるという効果を奏する。
【図面の簡単な説明】
【図１】本発明の実施の形態１における電源レギュレータ回路の回路例を示す図
【図２】本発明の実施の形態２における電源レギュレータ回路の回路例を示す図
【図３】電源レギュレータ回路の動作特性を示す図
【図４】従来の電源レギュレータ回路の回路例を示す図
【符号の説明】
１電源端子
２接地端子
３出力端子
４基準電圧源
５第１増幅器
５’ 第２増幅器
６Ｐ−ＭＯＳＦＥＴ
７第１抵抗
８第２抵抗
９抵抗
１０ＰＮＰトランジスタ
１１，３０，３１定電流源
１２第２Ｐ−ＭＯＳＦＥＴ
１３第３抵抗
１４第３Ｐ−ＭＯＳＦＥＴ
１５第１ＮＰＮトランジスタ
１６第４抵抗
１７第５抵抗
１８第６抵抗
１９第４Ｐ−ＭＯＳＦＥＴ
２０第５Ｐ−ＭＯＳＦＥＴ
２１第７抵抗
２２第６Ｐ−ＭＯＳＦＥＴ
２３第８抵抗
２４，２５ＮＰＮトランジスタ
２６，２７，３３，３４Ｎ−ＭＯＳＦＥＴ
２８，２９，３１，３２Ｐ−ＭＯＳＦＥＴ
３６第３増幅器
３７第１１抵抗
３８第１２抵抗
３９第９抵抗
４０第７Ｐ−ＭＯＳＦＥＴ
４１第２ＮＰＮトランジスタ
４２第８Ｐ−ＭＯＳＦＥＴ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power supply regulator circuit, and more particularly to a power supply regulator circuit having a current limiting circuit that prevents destruction due to excessive current.
[0002]
[Prior art]
The conventional power supply regulator circuit is configured as shown in the circuit diagram of FIG. 4, 1 is a power supply terminal, 2 is a ground terminal, 3 is an output terminal, 4 is a reference voltage source, 5 is an amplifier, 6 is a first P-channel MOSFET (hereinafter referred to as a P-MOSFET), 7, 8 is a first and second resistor for setting an output voltage, 9 is a resistor for detecting a load current, and 10 is a PNP transistor for detecting a current.
[0003]
In the power supply regulator circuit shown in FIG. 4, a first resistor 7 and a second resistor 8 are connected in series between the output terminal 3 and the ground terminal 2, and the voltage at the resistance dividing point and the voltage of the reference voltage source 4 are connected. Comparison is made by the first amplifier 5, the first P-MOSFET 6 is driven by this comparison output, and a load current is supplied to a load (not shown) connected to the output terminal 3. The output voltage Vo of the output terminal 3 is fed back to the positive input of the first amplifier 5 through a series circuit of the first amplifier 5, the first P-MOSFET 6 and the first resistor 7 and the second resistor 8. Stabilized by the loop.
[0004]
Here, if the voltage of the reference voltage source 4 is Vref, the resistance value of the first resistor 7 is R7, and the resistance value of the second resistor 8 is R8, the output voltage Vo can be expressed by the following (Equation 1). .
[0005]
[Expression 1]
Vo = Vref (R7 + R8) / R8
Next, a current limiting circuit composed of a PNP transistor 10 for current detection and a resistor 9 is provided to prevent the first P-MOSFET 6 that supplies the load current from being destroyed due to excessive load current. Yes. When the voltage drop of the resistor 9 becomes larger than the base-emitter voltage Vbe (about 0.7 V) of the PNP transistor 10, the PNP transistor 10 becomes conductive, and the voltage between the gate and source of the first P-MOSFET 6 is reduced, The 1P-MOSFET 6 is operated to turn off, and the load current is limited.
[0006]
Here, when the output voltage Vo = 2V is set, the operating characteristic of the conventional power supply regulator circuit is indicated by a broken line C in FIG.
[0007]
[Problems to be solved by the invention]
However, the power supply regulator circuit having such a configuration causes a voltage drop between the terminals of the resistor 9 when the resistor 9 is connected in series in order to detect the load current flowing through the first P-MOSFET 6 shown in FIG. Become. In order to detect the current when the load current is excessive and to prevent the voltage drop of the resistor 9 from being affected so much during normal operation, the resistance value of the resistor 9 needs to be selected to a small value.
[0008]
However, this causes the current limiting function to function at a large current value. When the load is short-circuited, most of the voltage of the power supply input is applied to the first P-MOSFET 6, and the allowable loss of the first P-MOSFET 6. And the first P-MOSFET 6 is destroyed.
[0009]
In addition, a voltage drop of the resistor 9 provided for current detection is inevitable, and there is a problem in that the power supply utilization efficiency is not always good.
[0010]
The present invention is directed to solving the above-described problems of the prior art, and restricts an excessive load current without connecting a current detection resistor in series with the output transistor, and the power supply voltage is efficiently used. An object is to provide a power supply regulator circuit.
[0011]
[Means for Solving the Problems]
To achieve this object, a power supply regulator circuit according to the present invention includes a first amplifier having a reference voltage source and a negative input connected thereto, an output and gate of the first amplifier, a power supply terminal and source, and an output terminal and drain. A first P-channel MOSFET for supplying a connected load current; and first and second resistors connected in series between an output terminal and a ground terminal. The first amplifier has a connection point between the first resistor and the second resistor. In a power supply regulator circuit to which a positive input is connected, a first P-channel MOSFET and a current mirror are configured, a second P-channel MOSFET having a drain connected to an output terminal via a third resistor, and a drain of the second P-channel MOSFET in the third resistor A third P-channel MOSFET having a source connected to the side and a gate connected to the output terminal, and a third P-channel MOS ET drain, ground terminal and base through fourth and fifth resistors, power supply terminal and collector through sixth resistor, ground terminal and emitter grounded first NPN transistor, and collector and gate of first NPN transistor A fourth P-channel MOSFET in which a power supply terminal and a source, a gate and a drain of the first P-channel MOSFET are connected , a reference voltage source and a positive input, an output terminal and a negative input, a connection point between a fourth resistor and a fifth resistor, and an output A second mirror connected to each other, a first P channel MOSFET and a current mirror, a fifth P channel MOSFET having a drain connected to an output terminal via a seventh resistor, and a drain side of the fifth P channel MOSFET in the seventh resistor A sixth P-channel MOSFET having a gate connected to the source and output terminals; Provided, characterized in that the drain current of the 6P-channel MOSFET and the bias current of the second amplifier.
[0014]
Further, a PNP transistor is used in place of the sixth P-channel MOSFET.
[0015]
A first amplifier connected to the reference voltage source and a negative input; an output and gate of the first amplifier; a first P-channel MOSFET for supplying a load current connecting the power supply terminal and source; and an output terminal and drain; and an output terminal. And a first resistor connected in series between the first and second resistors, and a positive input of the first amplifier is connected to the connection point of the first resistor and the second resistor. A second amplifier which is connected to a power supply terminal via a resistor and grounded via a constant current source, and whose negative input is connected to the power supply terminal via a ninth resistor, and a gate common to the gate and drain of the first P-MOSFET , Drain connected, seventh P-MOSFET connected to the negative input and source of the second amplifier, and base connected to the output of the second amplifier and connected in series Fourth, fifth through the resistor is grounded, a power supply terminal to the collector via a sixth resistor, a second 1NPN transistor emitter connected to the ground terminal through the 10th resistor, the first 1NPN transistor collector and gates A power terminal and source, a fourth P-MOSFET in which the gate and drain of the first P-MOSFET are connected, a second NPN transistor in which the power terminal is connected to the collector and the base and diode-connected, and an emitter and source in the second NPN transistor, 8th P-MOSFET which connected the gate of 1P-MOSFET, the connection point of the 11th and 12th resistance which connected the positive input in series with the reference voltage source, the negative input connected to the output terminal, and the output connected in series fourth, third and a amplifier that is connected to the connection point of the fifth resistor, the drain of the first 8P-MOSFET Characterized in that the flow was bias current of the third amplifier.
[0016]
Further, a PNP transistor is used in place of the fourth MOSFET.
[0017]
According to the above configuration, the bias current at no load does not increase, the power supply voltage utilization rate is not deteriorated, the overcurrent that the first P-MOSFET for supplying load current breaks can be limited, and the load current at load short-circuit In addition, the power consumption can be reduced and the device can be protected from destruction. Furthermore, when the difference between the power supply voltage and the output voltage is small, excessive current limitation does not work, and the capability of the first P-MOSFET for supplying the load can be sufficiently exhibited.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0019]
FIG. 1 is a diagram showing a circuit example of a power supply regulator circuit according to Embodiment 1 of the present invention. Here, components having the same functions corresponding to the components described in FIG. 4 showing the conventional example are denoted by the same reference numerals, and the same applies to the following drawings. The operation of the power supply regulator circuit according to the first embodiment will be described with reference to FIG.
[0020]
A constant current is supplied from the constant current source 11 connected to the power supply terminal 1 to the reference voltage source 4 to connect the reference voltage to the negative input of the first amplifier 5. The gate of the first P-MOSFET 6, which is an output transistor for supplying load current, is connected to the output of the first amplifier 5, and the source is connected to the power supply terminal 1. The drain is connected to the output terminal 3 and is connected to the positive input of the first amplifier 5 via the first resistor 7, and further, the positive input of the first amplifier 5 is connected to the ground terminal 2 via the second resistor 8. Connecting.
[0021]
The drain of the second P-MOSFET 12 connected to the current mirror having the gate and the source in common with the first P-MOSFET 6 is connected to the output terminal 3 through the third resistor 13 and to the source of the third P-MOSFET 14. . Further, the gate of the third P-MOSFET 14 is connected to the output terminal 3. The drain of the third P-MOSFET 14 is connected to the base of the first NPN transistor 15 whose emitter is connected to the ground terminal 2 and to the ground terminal 2 via the fourth and fifth resistors 16 and 17 connected in series. .
[0022]
In addition, the collector of the first NPN transistor 15 is connected to the other end of the sixth resistor 18 connected to the power supply terminal 1 and one end, and the source is connected to the gate of the fourth P-MOSFET 19 connected to the power supply terminal 1. The drain of the MOSFET 19 is connected to the gate of the first P-MOSFET 6.
[0023]
Further, in addition to the above-described configuration, the drain of the fifth P-MOSFET 20 having the gate and the source connected in common to the first P-MOSFET 6 is connected to the output terminal 3 via the seventh resistor 21 and is connected to the source of the sixth P-MOSFET 22. Connecting. Further, the gate of the sixth P-MOSFET 22 is connected to the output terminal 3, the drain is connected to the current mirror constituting the second amplifier 5 ′ via the eighth resistor 23, and the base of the NPN transistor 25 is shared. Connect to the connected connection point.
[0024]
The emitters of the NPN transistors 24 and 25 are respectively connected to the ground terminal 2, and the collector of the NPN transistor 25 constituting the current mirror is used as the N-MOSFET 26, N-MOSFET (hereinafter referred to as N-MOSFET) constituting the differential amplifier circuit. 27, the gate serving as the positive input of the N-MOSFET 26 is connected to the reference voltage source 4, and the gate serving as the negative input of the N-MOSFET 27 is connected to the output terminal 3.
[0025]
The drain of the N-MOSFET 26 constituting the differential amplifier circuit is connected to the common connection point of the drain and gate of the P-MOSFET 28 constituting the active load, and the source of the P-MOSFET 28 is a power source together with the source of the P-MOSFET 29. Connect to terminal 1. The gate of the P-MOSFET 29 is connected to the gate and drain of the P-MOSFET 28, and the drain of the P-MOSFET 29 (output of the second amplifier 5 ′) is connected to the drain of the N-MOSFET 27 and the fourth and fourth connected in series. Connect to the connection point of the fifth resistors 16 and 17.
[0026]
The first P-MOSFET 6, the second P-MOSFET 12, and the fifth P-MOSFET 20 are in a current mirror relationship. Further, the N-MOSFETs 26 and 27 and the P-MOSFETs 29 and 29 constituting the differential amplifier circuit constitute a second amplifier 5 ′.
[0027]
With the configuration as described above, the negative input voltage and the positive input voltage value of the first amplifier 5 are controlled to be equal to each other, and the output voltage Vo is
[0028]
[Expression 2]
Vo = Vref (R7 + R8) / R8
Vref is the voltage of the reference voltage source, R7 is the resistance value of the first resistor, R8 is the resistance value of the second resistor, and Equation 2 is established.
[0029]
For example, when the voltage of the output terminal 3 decreases for some reason, the connection point of the first and second resistors 7 and 8 connected in series, that is, the positive input voltage of the first amplifier 5 also decreases, so that the positive input Decreases from the negative input voltage, the gate voltage of the first P-MOSFET 6 for supplying the load current decreases, and the source-gate voltage increases. As a result, the load current increases, and the voltage at the output terminal 3 increases. As a result, the positive input voltage of the first amplifier 5 also increases, and the positive input voltage and the negative input voltage are made equal.
[0030]
Contrary to the above description of the operation, when the voltage of the positive input becomes higher than the voltage of the negative input, the operation is performed in the opposite direction to the above description. Similarly, the voltage of the positive input is equal to the voltage of the negative input. Is performed.
[0031]
Further, the load current increases, the drain current of the second P-MOSFET 12 constituting the current mirror with the first P-MOSFET 6 also increases, and the voltage drop of the third resistor 13 causes the threshold voltage VT between the gate and source of the third P-MOSFET 14. Exceeds the voltage Vbe between the base and emitter of the first NPN transistor 15, the collector current of the first NPN transistor 15 flows. When the voltage drop occurs in the sixth resistor 18 and exceeds the threshold voltage VT of the fourth P-MOSFET 19, the drain current flows, and the gate voltage of the first amplifier 5 and the connected first P-MOSFET 6 is increased, and the first P- An operation for limiting the load current which is the drain current of the MOSFET 6 is executed.
[0032]
Further, a drain current also flows through the fifth P-MOSFET 20 constituting the current mirror with the first P-MOSFET 6, and when the voltage drop of the seventh resistor 21 exceeds the threshold voltage VT between the gate and source of the sixth P-MOSFET 22, the sixth P- A drain current flows through the MOSFET 22, and a bias current is supplied as a source current of the N-MOSFETs 26 and 27 constituting the differential amplifier circuit by current mirrors of the NPN transistors 24 and 25.
[0033]
When the load current is further increased, as described above, the output voltage decreases because the load current is limited. When this output voltage falls below the voltage of the reference voltage source 4, the N-MOSFET 26 and P-MOSFET 28 of the differential amplifier circuit constituted by the N-MOSFETs 26 and 27 are turned ON, and the current mirror configuration of the P-MOSFETs 28 and 29 causes the P-MOSFET 29 to be turned on. The drain current flows to the connection point between the fourth and fifth resistors 16 and 17 connected in series to increase the base voltage of the first NPN transistor 15 to increase the collector current and increase the drain current of the fourth P-MOSFET 19. Then, the gate voltage of the first P-MOSFET 6 is increased to further reduce the load current.
[0034]
Here, until the third P-MOSFET 14 and the sixth P-MOSFET 22 for supplying bias current operate, the source and gate are connected in common to the first P-MOSFET 6 for supplying load current (a current mirror is configured). Since the drains of both the second and fifth P-MOSFETs 12 and 20 are connected to the output terminal 3, they are all supplied as a load current, the bias current does not increase, and they are all supplied effectively without waste.
[0035]
The operating characteristic of the power supply regulator circuit according to the first embodiment described above is shown by a solid line A in FIG. Since there is no loss due to the current detection resistor as compared with the conventional broken line C, the power supply voltage can be used effectively and a large amount of load current can be supplied. Further, when the output voltage drops below the reference voltage due to the current limit, the load current is further limited, so that the load current can be greatly reduced and the power consumption can be reduced. This function is effective for protection when the load is short-circuited.
[0036]
In the above description, the first P-MOSFET 6 for supplying the load current and the second and fifth P-MOSFETs 12 and 20 constituting the current mirror are connected to the third and seventh resistors 13 and 21 for detecting the drain current. Although the description has been given using the P-MOSFET as the element, it is needless to say that the same effect can be obtained even if the PNP transistor is used.
[0037]
FIG. 2 is a diagram showing a circuit example of a power supply regulator circuit according to the second embodiment of the present invention. The operation of the power supply regulator circuit according to the second embodiment will be described with reference to FIG.
[0038]
The power supply regulator circuit according to the second embodiment shown in FIG. 2 is different from the first embodiment shown in FIG. 1 in that a differential amplifier circuit is provided at the base of the first NPN transistor 15 that detects the limit of the load current. The drains of the P-MOSFETs 31 corresponding to the outputs of the P-MOSFETs 31 and 32 and the N-MOSFETs 33 and 34 are connected, and the gate of the N-MOSFET 34 that is the plus input of the differential amplifier circuit is the current of the constant current source 35. Is connected to the voltage drop portion of the eighth resistor 23 (the other end of the eighth resistor), and the third amplifier 36 further reduces the load current when the voltage at the output terminal 3 decreases due to current limitation. The main difference is that the reference voltage source 4 is divided and input by the eleventh and tenth resistors 37 and 38 to the plus input.
[0039]
A feature of the power supply regulator circuit shown in FIG. 2 is that the current limit does not operate unless a voltage drop of the ninth resistor 39 occurs from the power supply voltage to a voltage corresponding to the voltage drop of the eighth resistor 23. Assuming that the power supply voltage input from the power supply terminal 1 is Vin, the output voltage of the output terminal 3 is Vo, and the load current is Iout, the power consumption Po of the entire circuit is approximately (Equation 3).
[0040]
[Equation 3]
Po = (Vin−Vo) · Iout
When the difference between the power supply voltage of the power supply terminal 1 and the output voltage is small, the power consumption is small and the necessity of current limitation is small, and it is better to fully demonstrate the current capability of the first P-MOSFET 6 for supplying the load current. Characteristics are obtained. The first P-MOSFET 6 is set large and the seventh P-MOSFET 40 is set small by changing W / L, which is the ratio of the size of the first P-MOSFET 6 and the seventh P-MOSFET 40 whose gate and drain are connected in common. The first P-MOSFET 6 is naturally large because it is for supplying a load current, and the seventh P-MOSFET 40 may be small. Therefore, since the area may be small, the area efficiency of an integrated circuit is improved.
[0041]
When the difference between the power supply voltage and the output voltage is small, the drain current of the seventh P-MOSFET 40 is much smaller than that of the first P-MOSFET 6, and the gate voltage of the N-MOSFET 33 constituting the differential amplifier circuit is N-MOSFET 34. Therefore, the current limiting operation is not performed.
[0042]
In the circuit operation described below, the operation of the first amplifier 5 is the same as in the prior art, and is therefore omitted. When the load current increases, the gate-source voltage Vgs of the first P-MOSFET 6 for supplying the load current increases unless the current limiting operation is performed.
[0043]
[Expression 4]
Vgs = Vbe41 + VT42
Here, Vbe 41 is the base-emitter voltage of the second NPN transistor 41, and VT 42 is the threshold voltage of the eighth P-MOSFET 42.
[0044]
When the gate-source voltage Vgs of the first P-MOSFET 6 increases and reaches the threshold voltage of the eighth P-MOSFET 42, the drain current flows through the eighth P-MOSFET 42, the bias current flows through the third amplifier 36, and the operation state is reached. Is set. If the constant current sources 30 and 35 are also set based on the drain current, the bias can be greatly reduced when the load current is small.
[0045]
Further, when the load current increases, the gate voltage of the first P-MOSFET 6 decreases, and a difference voltage between the power supply voltage and the output voltage is generated to some extent, the source and drain currents of the eighth P-MOSFET 42 also increase, If a voltage drop occurs in the 9 resistor 39, and the voltage drop of the ninth resistor 39 becomes larger than the voltage drop of the eighth resistor 23, the N-MOSFET 33 is turned OFF and the N-MOSFET 34 is turned ON, thereby forming a current mirror. The drain current flows through the P-MOSFETs 31 and 32, the base-emitter voltage Vbe of the first NPN transistor 15 increases, the collector current flows when the voltage exceeds about 0.7V, and the gate voltage of the fourth P-MOSFET 19 decreases. The drain current flows, the gate voltage of the first P-MOSFET 6 for supplying the load current rises, and the load current is reduced. Executing the current limiting operation to low. When the load current is further increased, the output voltage decreases due to current limitation.
[0046]
When the voltage at the output terminal 3 falls below the positive input voltage of the third amplifier 36, that is, the voltage obtained by dividing the reference voltage source 4 by the eleventh and twelfth resistors 37 and 38, the output of the third amplifier 36 increases, The base voltage of the first NPN transistor 15 is increased via the four resistors 16, the collector current of the first NPN transistor 15 is increased, the gate voltage of the fourth P-MOSFET 19 is further lowered to increase the drain current, and the load current supply The gate voltage of the first P-MOSFET 6 is further increased, and the load current is further reduced and limited.
[0047]
In the above description, the fourth P-MOSFET 19 is shown and described as the element that operates by the collector current of the first NPN transistor 15, but instead, the same operation can be performed by using the same operation as the PNP transistor. Needless to explain.
[0048]
The operating characteristics of the power supply regulator circuit according to the second embodiment described above are indicated by a one-dot chain line B in FIG. When the voltage difference between the power supply voltage of the power supply terminal 1 and the output voltage of the output terminal 3 is small, the current limiting circuit does not operate and the output voltage is kept constant by fully utilizing the capability of the first P-MOSFET 6 for supplying load current. A load current that can be controlled can be increased. In addition, the bias current is the same as the circuit example shown in FIG. 1 of the present embodiment, and operates with a slight bias current of 20 μA or less when no load is applied, and a current limiting circuit for protecting the MOSFET for supplying the load current, Further, even if a load short-circuit protection circuit is added, the power regulator circuit does not increase, and when the difference between the power supply voltage and the output voltage is small, it is possible to realize a power supply regulator circuit having a current limiting circuit capable of fully exerting the load current supply MOSFET capability.
[0049]
【The invention's effect】
As described above, according to the present invention, the bias current at no load does not increase, the power supply voltage utilization rate does not deteriorate, and the load current supply first P-MOSFET is destroyed. Overcurrent can be limited, load current and power consumption when the load is short-circuited can be reduced, and protection from breakdown can be achieved. Furthermore, when the difference between the power supply voltage and the output voltage is small, excessive current limitation does not work, the capability of the first P-MOSFET for supplying the load can be fully exhibited, and a current limiting circuit having a large industrial utility value is provided. The power regulator circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit example of a power regulator circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing a circuit example of a power regulator circuit according to a second embodiment of the present invention. Diagram showing operating characteristics [Fig. 4] Diagram showing an example of a conventional power regulator circuit [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Ground terminal 3 Output terminal 4 Reference voltage source 5 1st amplifier 5 '2nd amplifier 6 P-MOSFET
7 First resistor 8 Second resistor 9 Resistor 10 PNP transistors 11, 30, 31 Constant current source 12 Second P-MOSFET
13 Third resistor 14 3rd P-MOSFET
15 1st NPN transistor 16 4th resistor 17 5th resistor 18 6th resistor 19 4th P-MOSFET
20 5th P-MOSFET
21 7th resistor 22 6th P-MOSFET
23 8th resistor 24, 25 NPN transistor 26, 27, 33, 34 N-MOSFET
28, 29, 31, 32 P-MOSFET
36 Third amplifier 37 11th resistor 38 12th resistor 39 9th resistor 40 7th P-MOSFET
41 2nd NPN transistor 42 8th P-MOSFET

Claims

A first amplifier connected to a reference voltage source and a negative input; an output and gate of the first amplifier; a first P-channel MOSFET for supplying a load current connected to a power supply terminal and a source; and an output terminal and a drain; and the output terminal And a first and second resistors connected in series between the ground terminal and a power supply regulator circuit in which a positive input of the first amplifier is connected to a connection point between the first resistor and the second resistor.
A second P-channel MOSFET that forms a current mirror with the first P-channel MOSFET and has a drain connected to the output terminal via a third resistor, a source on the drain side of the second P-channel MOSFET in the third resistor, and the output A third P-channel MOSFET having a gate connected to the terminal side; a drain of the third P-channel MOSFET; the ground terminal and base via fourth and fifth resistors; the power supply terminal and collector via a sixth resistor; A first NPN transistor having a ground terminal and an emitter connected; a collector and gate of the first NPN transistor; a power supply terminal and source; a fourth P channel MOSFET having a gate and drain connected to the first P channel MOSFET; and the reference voltage Source and positive input, said output A second amplifier in which a terminal and a negative input, and a connection point and an output of the fourth resistor and the fifth resistor are connected, and the first P-channel MOSFET and a current mirror are configured, and a drain is output via a seventh resistor. A fifth P-channel MOSFET connected to a terminal; and a sixth P-channel MOSFET having a source connected to the drain side of the fifth P-channel MOSFET in the seventh resistor and a gate connected to the output terminal side, the drain of the sixth P-channel MOSFET A power supply regulator circuit , wherein a current is a bias current of the second amplifier .

A power regulator circuit using a PNP transistor in place of the sixth P-channel MOSFET according to claim 1.

A first amplifier connected to a reference voltage source and a negative input; an output and gate of the first amplifier; a first P-channel MOSFET for supplying a load current connected to a power supply terminal and a source; and an output terminal and a drain; and the output terminal And a first and second resistors connected in series between the ground terminal and a power supply regulator circuit in which a positive input of the first amplifier is connected to a connection point between the first resistor and the second resistor.
A second amplifier having a positive input connected to the power supply terminal via an eighth resistor and grounded via a constant current source, and a negative input connected to the power supply terminal via a ninth resistor; and the first P-channel MOSFET A seventh P-channel MOSFET in which the gate and the drain are connected in common with each other, the negative input and source of the second amplifier are connected, and a base is connected in series with the output of the second amplifier. 4, grounded via a fifth resistor, a second 1NPN transistor connect to the ground terminal through the power supply terminal to the collector via a sixth resistor, the emitter 10 resistor, the collector of the first 1NPN transistor And a gate, a power supply terminal and a source, and a fourth P channel connecting the gate and drain of the first P-channel MOSFET. And MOSFET, the power supply terminal and the collector, a first 2NPN transistor connected to connect the base diode, and the emitter and the source of the 2NPN transistor, the 8P channel MOSFET connected to the gate and the gate of the first 1P channel MOSFET, plus A third amplifier having an input connected to a connection point of eleventh and twelfth resistors connected in series with the reference voltage source, a negative input connected to the output terminal, and a connection point of the fourth and fifth resistors connected in series to an output And the drain current of the eighth P-channel MOSFET is used as the bias current of the third amplifier .

A power regulator circuit using a PNP transistor instead of the fourth P-channel MOSFET according to claim 3.