JP3839005B2 - HDLC monitoring circuit and frame relay monitoring circuit - Google Patents

Description

  The present invention relates to error control of HDLC (High Level Data Link Control), which is a data link layer communication protocol, and FCS (Frame Check Sequence) used for error correction of frame relay.

  There is a seven-layer model of OSI as a schematic configuration of an information network. As a kind of data link layer protocol for exchanging data between terminals directly connected in this hierarchy, X. HDLC (High Level Data Link Control) and frame relay used in No. 25 are defined.

  FIG. 6 shows the HDLC message format and is a data structure diagram.

  The HDLC data 100 includes a start flag 101, an address 102, a control unit 103, actual data 104, an FCS (frame check sequence) 105, and an end flag 106.

  In HDLC, the start and end of data are identified using a flag sequence. That is, data is started by the start flag 101 represented by “01111110”, and the end of the data is represented by the end flag 106 which is also a bit string of “01111110”. Between the start flag 101 and the end flag 106, the actual data 104 used in the network layer and above is stored together with the address 102, the control unit 103, and the FCS 105, thereby forming a frame. Therefore, it is not allowed that the bit string “01111110” is generated between the start flag 101 and the end flag 106. Therefore, the HDLC protocol stipulates that “0” is forcibly inserted when five “1” s are consecutive in the address 102, the control unit 103, the actual data 104, and the FCS 105 (“0” insertion removal) ).

  The control unit 103 is in principle 8-bit data, and the configuration differs depending on the type of frame (information frame, monitoring frame, unnumbered frame). Therefore, the control unit 103 indicates the control information indicating the type of the frame, the transmission order number by modulo (information frame) or the type of command (monitor frame, unnumbered frame), and whether or not to request a response. A POLL / FINAL bit is included. The presence of the transmission sequence number gives the HDLC a feature that is significantly different from the basic procedure in which data can be transmitted without waiting for an ACK from the partner terminal. Note that the transmission order number is in modulo notation, and normally the remainder obtained by dividing by “8” is used, but “128” may be used as a divisor in satellite communication or the like.

  FIG. 7 is a flowchart showing an example of processing when receiving a conventional HDLC frame. This diagram will be described together with processing generally performed in HDLC processing.

  When data is received, if the start flag 101 is detected (step 901), the subsequent data is recorded in the buffer (step 903) until the end flag is recognized (step 902). At this time, “0” deletion processing for deleting “0” bits after five consecutive “1” s having so-called “0” insertions is also performed (step 904). When recording to this buffer, the start flag and end flag are generally excluded from the target of recording. This is to reduce the amount of data to be recorded. Therefore, here, the discussion proceeds on the assumption that the start flag and the end flag are not to be recorded.

  When the storage of data in the buffer is completed, the data of the address portion of the first 8 bits is extracted (step 905), and it is determined whether or not the data is transmitted to itself (step 906). At this time, if the data is not transmitted to itself, the data stored in the buffer is discarded.

  If the data is addressed to itself, the value of the FCS unit 105 is extracted. In HDLC, data is exchanged in units of frames, and if the received frame contains an error for some reason, a retransmission request is made to the data transmission source. In the HDLC protocol, a cyclic check code (hereinafter referred to as CRC) is used for error detection. As a result, the HDLC protocol is characterized in that it enables more powerful error detection and correction than the basic procedure, which is the same data link layer protocol.

  The CRC itself obtains a remainder polynomial representing a “remainder” obtained by dividing the transmission data by the generator polynomial common to the transmission side and the reception side, transmits the data with the remainder polynomial derived at the end of the transmission data, and transmits the data on the reception side. This is a method for confirming an error. The FCS unit 105 represents this remainder polynomial, and is attached to the end of the actual data 104 after the sender polynomial is derived.

  The receiving side compares the remainder obtained by dividing the address portion 102, the information portion 103, and the actual data 104 of the received data by the generator polynomial with the FCS portion 105 (step 907). The generator polynomial used in HDLC is often a 16-bit CRC-16 standardized by ITU-T, but a 32-bit one may be used.

  If the remainder of the division and the value of the FCS unit 105 match (step 908: No), the received data has no error and the processing in the higher layer and the response to the transmission source are prepared. On the other hand, if they do not match (step 908: Yes), a retransmission request is made to the transmission source on the assumption that invalid data has been received (REJ command for monitoring frame, etc.)

  There are various methods for resending this frame. In the standard HDLC specification, a REJ command for requesting a frame after the transmission order number requested for retransmission and a SREJ command for requesting a frame only for the requested transmission order number are employed. On the other hand, Japanese Patent Application Laid-Open No. 08-097880 and Japanese Patent Application Laid-Open No. 2000-083012 describe a technique in which retransmission requests are limited to frames having a certain range of transmission order numbers and frames in that range are retransmitted. ing.

Japanese Patent Laid-Open No. 08-097880 JP 2000-083012 A JIS X5104 (ISO 3309)

  In the above document, the correctness of a frame is judged only by the suitability of CRC. This judgment method is sufficient in general cases.

  However, if five “1” s are arranged at the end of the FCS 105 immediately before the end flag, the bit “... 11111001111110” is supposed to be “... 11111011111110” due to a random error due to noise or the like. there is a possibility. If it is applied, it should be a violation of the HDLC regulations. However, since there is no “0” to be removed, the value of the restored FCS 105 remains normal, and the CRC processing is properly performed. there is a possibility.

  An object of the present invention is to provide a circuit capable of handling an error when a CRC error does not occur due to a random error generated at the end of the FCS unit 105 but an HDLC standard violation is violated. .

The HDLC reception circuit according to the present invention includes a reception circuit, an FCS comparison circuit, a flag detection circuit, and an FCS monitoring circuit. The flag detection circuit performs a reception process after a start flag of HDLC data in the reception circuit and the FCS monitoring circuit. The receiver circuit removes “0” from the HDLC data based on the HDLC protocol, and then extracts the address part, the control part, the FCS and the actual data, performs CRC (cyclic redundancy check) code processing, and compares the FCS The circuit determines whether or not there is a CRC error depending on whether the FCS value of the HDLC data obtained by the receiving circuit matches the value obtained from the remainder polynomial, and the FCS monitoring circuit arranges the data string immediately before the end flag. whether or not Han but contrary to the HDLC protocol at whether or not it is "11111" Characterized in that it.

  Further, the HDLC reception circuit described above includes a control unit, and makes a retransmission request when either the CRC error or the HDLC error occurs.

  In addition, the HDLC reception circuit according to the present invention includes a reception circuit, an FCS comparison circuit, a flag detection circuit, a bit number count circuit, a “0” insertion circuit, and a data number comparison circuit. The flag detection circuit is provided after the start flag of HDLC data. Is received by the receiving circuit and the FCS monitoring circuit, and after removing “0” based on the HDLC protocol, the receiving circuit extracts the address part, the control part, the FCS, and the actual data to obtain CRC (cyclic redundancy). Check) code processing is performed, the bit count circuit counts the number of bits of HDLC data before “0” is removed, and the “0” insertion circuit again converts the HDLC protocol to HDLC data after the removal of “0”. Is inserted, and the number of bits of the data after the insertion of “0” is counted, and the data number comparison circuit It compared the counting result of the counting result and the "0" insertion circuit of the bit count circuit, characterized in that to check for HDLC error.

  Further, the HDLC receiving circuit according to the present invention includes a control unit, and makes a retransmission request when either the CRC error or the HDLC error occurs.

A frame relay reception circuit according to the present invention includes a reception circuit, an FCS comparison circuit, a flag detection circuit, and an FCS monitoring circuit. The flag detection circuit performs a reception process after a start flag of frame relay data in the reception circuit and the FCS monitoring circuit. The receiver circuit removes “0” based on the frame relay protocol, and then extracts the address part, the control part, the FCS, and the actual data, performs CRC (cyclic redundancy check) code processing,
In the FCS comparison circuit, the remainder polynomial of the data obtained by the receiving circuit is the FCS.
The FCS monitoring circuit determines whether there is a violation of the frame relay protocol based on whether the sequence of the data string immediately before the end flag is “11111”. Features.

  Further, a control unit may be included, and when either the CRC error or the frame relay error has occurred, the received frame relay data may be discarded.

  Another frame relay receiving circuit according to the present invention includes a receiving circuit, an FCS comparing circuit, a flag detecting circuit, a bit number counting circuit, a “0” insertion circuit, and a data number comparing circuit, and the flag detecting circuit is a frame relay. The reception process after the data start flag is notified to the reception circuit and the FCS monitoring circuit, and the reception circuit extracts “0” based on the frame relay protocol and then extracts the address part, the control part, the FCS, and the actual data. CRC (cyclic redundancy check) code processing is performed, the bit count circuit counts the number of bits of frame relay data before “0” removal, and the “0” insertion circuit performs “0” removal. Based on the frame relay protocol, “0” is inserted again into the frame relay data of “0” and the data after “0” is inserted Counting the Wattage, the number of data comparison circuit by comparing the count result of the count result and the "0" insertion circuit of the bit count circuit, characterized in that to check for frame relay errors.

  Further, the frame relay reception circuit further includes a control unit, and the control unit can discard the received data when either the CRC error or the frame relay error occurs.

  By taking the following configuration, the following effects are exhibited.

  That is, it is possible to transmit and receive more accurate data by determining whether or not the provisions regarding insertion of “0” in the HDLC protocol or the frame relay protocol are observed, as well as correctness of CRC data.

  In addition, even if there are no errors as a result, it is possible to maintain the reliability of the received data and reduce the load on the upper layer by making a retransmission request for data with doubtful reliability. It becomes possible to plan.

  FIG. 1 is a block diagram showing the configuration of an HDLC receiver circuit according to the first embodiment of the present invention. This HDLC reception circuit is composed of a CPU 1, a reception circuit 2, an FCS comparison circuit 3, a flag detection circuit 4 and an FCS monitoring circuit 5. The reception circuit 2 includes a “0” removal circuit 21 and a CRC calculation circuit 22.

  A CPU (control circuit) 1 is a block for processing data for processing after the network layer and processing itself after the network layer if the received HDLC data is normal. In the present embodiment, transmission processing by HDLC is also performed. The CPU 1 may use a DSP or the like as long as substitution is effective.

  The receiving circuit 2 extracts the address, control unit, FCS and actual data from the HDLC data received by the physical layer, removes “0”, is in compliance with the HDLC regulations, and contains data using FCS. It is a block to examine whether it is.

  The “0” removal circuit 21 is a block for deleting the next “0” in which five “1” s in the address 102, the control unit 103, the actual data 104, and the FCS (frame check sequence) 105 are consecutive.

  The CRC calculation circuit 22 is a block that divides the address 102 after removal of “0”, the control unit 103, and the actual data 104 by the generator polynomial. Since the binary division circuit can be generated by a shift register, it can be realized with a very simple configuration.

  The FCS comparison circuit 3 is a block that compares the calculation result of the CRC calculation circuit 22 with the FCS 105. If there is no error in the received data, the calculation result of the CRC calculation circuit 22 matches the FCS 105.

  The flag detection circuit 4 is a block for detecting a bit string “01111110” representing the start flag 101 and notifying the reception circuit 2 and the FCS monitoring circuit 5 of the detection result. The receiving circuit 2 starts and stops the operation with this notification as a trigger.

  The FCS monitoring circuit 5 is a block for checking the 5 bits immediately before the end flag 106, that is, the last 5 bits of the FCS 105. A 5-bit shift register that latches RXD data using RXCLK as a trigger is prepared, and if the registers are all 1 when a signal is received from the flag detection circuit 4, the CPU 1 is notified of a violation of HDLC regulations. However, the configuration is not limited to this.

  Next, what kind of processing is performed using this HDLC receiving circuit will be described with reference to FIGS.

  FIG. 2 shows the data structure of illegal HDLC data 200 that is planned to be detected by the present invention. 6 differs from FIG. 2 in that an illegal FCS unit 205 is included. The illegal FCS 205 scheduled to be detected by the present invention has five “1” s at the end thereof and data that does not have “0” originally inserted thereafter. Therefore, although the received data is essentially against the HDLC regulations, there is no “0” that is originally inserted and that is to be deleted, and there is a possibility that the data can be verified by CRC. It is data with.

  The flowchart shown in FIG. 3 shows how the illegal HDLC data 200 is handled in the first embodiment of the present invention. The processing of the embodiment of the present invention will be described based on this flowchart.

  When the flag detection circuit 4 detects the start flag 101 (step 301) and confirms reception of data, the received data is cached (step 303) until the FCS monitoring circuit 5 detects the end flag 106 (step 302). At this time, in the embodiment of the present invention, the start flag 101 and the end flag 106 are not to be cached.

  When the data cache is completed, the last 5 bits of the cached data are extracted (step 304). If the extracted 5-bit arrangement is “11111” (step 305: Yes), it is recorded as a violation of the HDLC rules (step 306).

  Regardless of whether or not there is a violation of the HDLC rules, the data “0” removed by the “0” removal circuit 21 is deleted (step 307), and the CPU 1 extracts the address unit 102 and the control unit 103 (step 308). When it is confirmed by the address unit 102 extracted by the CPU 1 that the received data is not addressed to itself (step 308: No), the data cached by the CPU 1 is discarded and the processing ends.

  If it is data addressed to itself (step 308: Yes), the CPU 1 checks whether there is a violation of the HDLC rules confirmed in step 305 (step 309), and if there is a violation of the HDLC protocol (step 309: Yes), Request retransmission. If there is no violation of the HDLC protocol (step 309: No), the FCS comparison circuit 3 compares the remainder polynomial derived by the FCS unit 105 and the CRC calculation circuit 22 (step 310) and examines whether there is a CRC error. (Step 311). If there is a CRC error, the CPU 1 makes a retransmission request, and if there is no error, a reception completion process is performed. The determination of the presence or absence of a CRC error is the same as in FIG. 7, and is omitted here.

  As described above, whether or not the HDLC protocol is violated is monitored regardless of the CRC error. If the HDLC standard is violated, the received data can be discarded, and a retransmission request can be sent to the transmission source. Data can be sent and received.

  Next, a second embodiment of the present invention will be described with reference to FIGS. The target illegal data is the same as in FIG. 2, but the method for determining whether or not it is appropriate is different from that of the first embodiment.

  FIG. 4 is a block diagram showing the configuration of an HDLC receiver circuit to which the second embodiment of the present invention is applied. This HDLC reception circuit is composed of a CPU 1, a reception circuit 2, an FCS comparison circuit 3, a flag detection circuit 4, a bit number count circuit 7, a “0” insertion circuit 8, and a data number comparison circuit 9. Hereinafter, these components will be described, but the description of the configuration that exhibits the same function as in FIG. 2 will be omitted.

  The bit number counting circuit 7 is a circuit that counts the number of bits of received data. Since the number of bits of the start flag 101 and the end flag 106 is fixed (each 8 bits), if the total number of bits can be derived, the number of bits of data to be inserted with “0” can be derived. In the present embodiment, the counting of the number of bits is completed by detecting the end flag 106 as in the FCS monitoring circuit 5.

  The “0” insertion circuit 8 is a circuit that inserts “0” once again from the data from which “0” has been removed by the “0” removal circuit 21 based on the HDLC protocol. If it is normal data, the data length before “0” removal by the “0” removal circuit 21 and the data length after “0” insertion by the “0” insertion circuit 8 should be the same. The data number comparison circuit 9 examines whether or not the data lengths are the same.

  The data number comparison circuit 9 is a circuit that compares the count result of the bit number count circuit 7 with the number of bits of data after the “0” insertion circuit 8 is processed. If both are the same number, the received data is data conforming to the HDLC protocol, and it can be determined that there is no error. On the other hand, if both values are different, it can be said that the received data is data that does not conform to the HDLC protocol, and its authenticity is doubtful.

  FIG. 5 is a flowchart showing how the illegal HDLC data 200 is handled in the second embodiment of the present invention. Based on this, the operation of the HDLC receiver circuit shown in FIG. 4 will be described.

  When the flag detection circuit 4 detects the start flag 101 (step 501) and confirms reception of data, the received data is cached in a memory (not shown) until the end flag 106 is detected (step 502) (step 503). As the start flag 101 is detected, the flag detection circuit 4 outputs a signal for counting the number of bits of the received data to the bit number counting circuit 7.

  When the reception data end flag 106 is received, the bit number counting circuit 7 finishes counting the number of bits of the received data (step 504). Whether the start flag 101 and the end flag 106 are included in the count target is a matter of design, but the start flag 101 and the end flag 106 are not recorded here.

  When the data cache is completed, the “0” removal circuit 21 performs a “0” removal process from the data excluding the start flag 101 and the end flag 106 (step 505), and the CPU 1 records it in a memory (not shown). At this time, the data after the “0” removal processing is also output to the “0” insertion circuit 8 for recording in the memory.

  Next, the “0” insertion circuit 8 again inserts “0” based on the HDLC protocol into the data after the removal of “0” (step 506), and counts the number of bits (step 507). . At this time, the number of bits of the data after reinsertion becomes a problem, and the data itself is not scheduled to be reused, and may or may not be saved in the memory.

  Both the count result of step 504 and the count result of step 507 are output to the data number comparison circuit 9, and the data number comparison circuit 9 determines whether or not the values are equal (step 508). If the values are different (step 508: No), the CPU 1 stores that there is an HDLC error (step 509).

  After that, the address unit 102 and the control unit 103 are extracted from the data after removing “0” recorded in the memory (step 510), and the CPU 1 checks whether the data is addressed to itself (step 510). If the data is not addressed to itself (step 511: No), the received data is discarded and the process is terminated. On the other hand, if the received data is data addressed to itself (step 511: Yes), the CRC arithmetic circuit 22 derives the remainder polynomial and the FCS comparison circuit 3 compares the remainder polynomial with the FCS, and notifies the CPU 1 of the result (step). 512). If there is a CRC error or an HDLC protocol error (step 513: Yes), the CPU 1 makes a retransmission request. If there is no error, the reception process is completed, and a process by a higher layer is executed.

  In the above example, only the application in the HDLC protocol has been described. However, the present invention can also be applied to a frame relay having almost the same frame configuration and performing the same CRC error detection. In this case, the above address unit 102 and control unit 103 are appropriately replaced. Further, since there is no retransmission processing in the frame relay, the retransmission request in FIG. 3 and FIG.

  The present invention provides an HDLC protocol and an X.264 including HDLC protocol as a data link layer. It is assumed to be used for a device conforming to the 25-packet exchange protocol and a device scheduled to be connected to the frame relay network. For example, an ISDN router or a frame relay switch.

1 is a block diagram illustrating a configuration of an HDLC data receiving circuit according to a first embodiment of the present invention. It is a block diagram showing the structure of the HDLC error data made into search object by this invention. 3 is a flowchart showing processing of the HDLC data receiving circuit according to the first embodiment of the present invention. It is a block diagram showing the structure of the HDLC data receiving circuit which is the 2nd Example of this invention. It is a flowchart showing the process of the HDLC data receiving circuit which is the 2nd Example of this invention. It is a block diagram showing the structure of normal HDLC data. It is a flowchart showing the process of the conventional HDLC data receiving circuit.

Explanation of symbols

1 CPU (control circuit)
2 receiving circuit 3 FCS comparison circuit 4 flag detection circuit 5 FCS monitoring circuit 7 bit number counting circuit 8 “0” insertion circuit 9 data number comparison circuit 100 HDLC packet

Claims (8)

An HDLC reception circuit that receives data (HDLC data) based on an HDLC (High Level Data Link Control) protocol including a reception circuit, an FCS comparison circuit, a flag detection circuit, and an FCS monitoring circuit,
The flag detection circuit notifies the reception circuit and the FCS monitoring circuit of reception processing after the start flag of the HDLC data,
The receiving circuit removes “0” from the HDLC data based on the HDLC protocol, and then extracts the address part, the control part, the FCS, and the actual data, performs CRC (cyclic redundancy check) code processing,
The FCS comparison circuit determines the presence or absence of a CRC error based on the FCS value of the HDLC data obtained by the reception circuit,
The FCS monitoring circuit, wherein the FCS monitoring circuit determines whether or not the HDLC protocol is violated by whether or not the arrangement of the data string immediately before the end flag is “11111” . Further including a control circuit,
The HDLC reception circuit according to claim 1 , wherein the control circuit issues a retransmission request when either the CRC error or the HDLC error occurs. An HDLC reception circuit that receives HDLC data including a reception circuit, an FCS comparison circuit, a flag detection circuit, a bit number count circuit, a “0” insertion circuit, and a data number comparison circuit,
The flag detection circuit notifies the reception circuit and the FCS monitoring circuit of reception processing after the start flag of the HDLC data,
The receiver circuit removes “0” based on the HDLC protocol and then extracts the address part, the control part, the FCS, and the actual data, performs CRC (cyclic redundancy check) code processing,
The bit number counting circuit counts the number of bits of HDLC data before removing “0”,
The “0” insertion circuit inserts “0” into the HDLC data after removing “0” again based on the HDLC protocol, counts the number of bits of the data after insertion of “0”,
The HDLC reception circuit, wherein the data number comparison circuit compares the count result of the bit number count circuit with the count result of the “0” insertion circuit to check whether there is an HDLC error. Further including a control circuit,
4. The HDLC receiving circuit according to claim 3, wherein the control circuit makes a retransmission request when either the CRC error or the HDLC error occurs. A frame relay receiving circuit for receiving data (frame relay data) based on a frame relay protocol including a receiving circuit, an FCS comparison circuit, a flag detection circuit, and an FCS monitoring circuit,
The flag detection circuit notifies the reception processing after the start flag of the frame relay data to the reception circuit and the FCS monitoring circuit,
The receiver circuit removes “0” based on the frame relay protocol, and then extracts the address part, the control part, the FCS, and the actual data, performs CRC (cyclic redundancy check) code processing,
The FCS comparison circuit determines whether the remainder polynomial of the data obtained by the receiving circuit has a CRC error based on the FCS value;
The FCS monitoring circuit determines whether or not the frame relay protocol is not violated by whether or not the arrangement of the data string immediately before the end flag is “11111” . Further including a control circuit,
6. The frame relay receiving circuit according to claim 5 , wherein the control circuit discards the received frame relay data when either the CRC error or the frame relay error occurs. A frame relay receiving circuit for receiving frame relay data including a receiving circuit, an FCS comparing circuit, a flag detecting circuit, a bit number counting circuit, a “0” insertion circuit and a data number comparing circuit;
The flag detection circuit notifies the reception processing after the start flag of the frame relay data to the reception circuit and the FCS monitoring circuit,
The receiver circuit removes “0” based on the frame relay protocol, and then extracts the address part, the control part, the FCS, and the actual data, performs CRC (cyclic redundancy check) code processing,
The bit number counting circuit counts the number of bits of the frame relay data before removing “0”,
The “0” insertion circuit inserts “0” into the frame relay data after removing “0” again based on the frame relay protocol, counts the number of bits of the data after insertion of “0”,
The data number comparison circuit compares the count result of the bit number count circuit with the count result of the “0” insertion circuit, and confirms the presence or absence of a frame relay error. Further including a control circuit,
8. The frame relay receiving circuit according to claim 7, wherein the control circuit discards received data when either the CRC error or the frame relay error occurs.

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