JP3841082B2 - Active matrix liquid crystal display device and driving method thereof - Google Patents

Description

  The present invention relates to an active matrix liquid crystal display device and a driving method thereof.

  Various driving methods for the active matrix type liquid crystal display device are known, and there are various driving circuit configurations for realizing the driving method. Among them, the drive circuits which are currently mainstream are roughly classified into a point sequential method and a line sequential method. They are distinguished by the difference in timing of writing a signal to the liquid crystal. A signal in which signals are simultaneously written in a plurality of liquid crystals whose write-hold state is controlled on one scanning line is referred to as a line sequential method, and a signal in which signals are sequentially written in the plurality of liquid crystals is referred to as a dot sequential method. The dot-sequential drive circuit is often used mainly for small liquid crystal display devices with a diagonal of 10 cm or less, and the line-sequential drive circuit is used for medium to large-sized liquid crystal display devices with a diagonal of 10 cm or more. There are many. The line-sequential driving circuit is described in, for example, the flat panel display 1991 “The problem of the driver LSI is solved by using a low-voltage single power source” (Nikkei BP, published on November 26, 1991, p168 to p172). .

  FIG. 2 shows a configuration example of an active matrix liquid crystal display device using a line sequential driving circuit as a signal line driving circuit. The TFT-LCD panel 201 includes a signal line driving circuit 206, a scanning line driving circuit 207, and a pixel matrix 202. Further, the signal line driving circuit includes a shift register SRX, a level shifter LSX, and a sample / hold circuit SH, and the scanning line driving circuit 207 includes a shift register SRY and a level shifter LSY. Further, the pixel matrix 202 includes thin film transistor elements 203 at intersections of the n scanning lines G1, G2,... Gn, the m signal lines S1, S2,. A liquid crystal element 204 and a storage capacitor 205 are provided. The signal line driving circuit 206 is provided for the purpose of inputting the video signal VIDEO to the signal lines S1, S2,... Sm, and the scanning line driving circuit 207 is a thin film transistor element 203 connected to the scanning lines G1, G2,. It is provided for the purpose of controlling the conduction-non-conduction state.

  An example of a method for driving the liquid crystal display device illustrated in FIG. 2 will be described. First, the first signal XIN is sequentially transferred to the outputs Bit1, Bit2,... Bitm by the shift register SRX synchronized with the first clock XCLK. Signals output in time series to the output Bit1, Bit2,... Bitm are subjected to voltage level shift by the level shifter LSX, and used as a signal for controlling the timing of sampling of the video signal VIDEO in the sample and hold circuit SH. The video signal is once sampled in time series by the sample and hold circuit SH and then written to the signal lines S1, S2,... Sm simultaneously with the output of the output enable signal ENBL. At this time, the scanning line driving circuit 207 is connected to a certain scanning line, for example, the scanning line G1, by the shift register SRY synchronized with the second clock CLY and the level shifter LSY for level-shifting the output voltage of the shift register. A selection signal for turning on only the thin film transistor group is output. The thin film transistor group in the conductive state transmits the video signal output from the signal line driver circuit 206 to the signal lines S1, S2,... Sm to a liquid crystal element and a storage capacitor provided for each pixel. Thereafter, by repeating this for the scanning lines G2... Gn, the video signal can be written in the liquid crystal element of each pixel. An arbitrary display screen can be obtained by using the above method and further utilizing the electro-optical characteristics of the liquid crystal element.

  The shift registers SRX and SRY used in this liquid crystal display device are constituted by, for example, a circuit shown in FIG. FIG. 5 (a) uses a D-flip flop, and FIG. 5 (b) uses a clocked inverter and an AND gate. In the former shift register using the D-flip flop, a shift operation of 1 bit is performed with one clock CLKa, and in the latter shift register, a shift operation of 1 bit is performed with 1/2 clock of the clock CLKb. Is called. The former configuration is often used when the shift registers SRX and SRY are composed of MOSFETs, and the latter configuration is often used when the shift registers are composed of thin film transistors.

  Now, each control signal or video signal necessary for driving the TFT-LCD panel 201 of FIG. 2 is obtained or modulated in the TFT-LCD unit 309 shown in FIG. An external clock signal ECLK, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, and an original video signal 310 are input to the TFT-LCD unit 301. The output enable signal ENBL is generated by the ENBL generation circuit 305 using the horizontal synchronization signal HSYNC and the first clock XCLK. The ENBL generation circuit, for example, resets with the horizontal synchronization signal, and then outputs a pulse signal when the counter circuit that counts the number of pulses of the first clock XCLK reaches the set value. And a pulse output circuit. The reset signal RST necessary for the reset operation of the sample and hold circuit is also generated in the same manner as the output enable signal.

  Here, the signal line driving circuit is extracted from the liquid crystal display device having the above configuration, and the operation will be further described. FIG. 4 is a diagram for explaining the configuration of the signal line driver circuit 206. In synchronization with the first clock XCLK, the first signal XIN is output by the shift register SRX that sequentially transfers the first signal XIN to the output Bit1, Bit2,... Bitm, and the level shifter LSX that shifts the voltage level of the output of the shift register. The signal controls the conduction state of the analog switches ASW1,1, ASW2,1... ASWm, 1. At this time, by sequentially turning on and off the analog switch, the video signal VIDEO corresponding to each of the signal lines S1, S2,... Sm can be taken into the sample capacitor CSPL. After that, when a selection pulse is output to the output enable signal ENBL, the analog switch group ASW1,2, ASW2,2,... ASWm, 2 whose conduction state is controlled by the output enable signal becomes conductive, and the sample The video signal sampled in the capacity is transferred to the hold capacity CHLD. At this time, since the transfer of the video signal from the sample capacitor to the hold capacitor is performed by capacitive coupling, accurate transfer cannot be performed if the voltage of the hold capacitor before transfer differs for each signal line unit. Therefore, in order to reset the hold capacitor before transfer, all the hold capacitors are set to a fixed voltage such as a ground voltage by reset switch groups RSW1, RSW2,. Is applied in advance. Next, the analog buffers B1, B2,... Bm buffer and output the video signal transferred to the hold capacitor. As the output of the selection pulse ends, the analog switch group is turned off, so that the hold capacitor and the sample capacitor are electrically insulated. From this state, the video signal is sampled to the sample capacity again. Thereafter, by repeating this, an arbitrary video signal can be supplied to each signal line.

  By using such a driving method, it is possible to use almost all of one horizontal scanning period except for the period during which the selection pulse of the output enable signal is output for writing the video signal to the signal line. As a result, the driving capability of the signal line driving circuit with respect to the load of the signal line or the pixel is improved, and a large area TFT-LCD having a display diagonal of 30 cm or more can be realized.

  In a conventional active matrix liquid crystal display device, latch signals such as output enable signals are delayed by an electrostatic protection circuit formed on the same substrate as the pixel matrix, and the timing may not be determined accurately. The electrostatic protection circuit is clearly an obstacle from the viewpoint of the time accuracy of the signal, but it protects the scanning line drive circuit, signal line drive circuit, etc. formed on the same substrate as the pixel matrix from electrostatic discharge damage. This is extremely effective in terms of points. When the electrostatic protection circuit is not provided, the yield in the manufacturing process is significantly reduced.

  Therefore, conventionally, a latch signal such as an output enable signal has been obtained using a signal source having a large load driving capability. Many of these signal sources have increased current driving capability, which increases the power consumption of the apparatus. Further, if the driving capability is increased unnecessarily, the signal waveform is distorted, causing a malfunction due to overshoot. Therefore, in the latest active matrix type liquid crystal display device, it is becoming difficult to guarantee the temporal accuracy of latch signals such as output enable signals.

  The present invention solves the above problems.

In order to solve the above problems, the present invention provides an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, wherein the signal line driver circuit includes a shift register, the shift register A plurality of sample switches for sampling signals in accordance with latch signals sequentially generated by the register; a plurality of hold capacitors for holding signals sampled by the plurality of sample switches; and a first control signal for resetting the plurality of hold capacitors And a second control circuit that generates a second control signal for controlling transfer of signals from the plurality of sample switches to the plurality of hold capacitors, the first control circuit comprising: The signal transferred in the shift register is inputted and transferred to generate the first control signal, and the second control Road is characterized in that to transfer by inputting a signal transferred in the first control circuit is formed by generating the second control signal.
Furthermore, the signal line driving circuit further includes a plurality of buffers for outputting the signal held by the hold capacitor to each of the plurality of signal lines,
The first control signal resets the plurality of hold capacitors and resets output terminals of the plurality of buffers.
Further, the first and second control circuits have the same circuit configuration as the shift register.
Further, the first and second control circuits have a count circuit that counts clock signals supplied to the shift register, and the signals transferred in the shift register according to the timing controlled by the count circuit Is input and transferred.
According to another aspect of the present invention, in order to solve the above problems, a latch signal is sequentially generated by a shift register in a driving method of an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate A signal is sequentially sampled by a plurality of sample switches in response to the latch signal, and a signal transferred in the shift register is input and transferred to generate a first control signal for resetting a plurality of hold capacitors; After the first control signal is generated, the signal transferred in the shift register is input and transferred, and the second control signal for holding the signals sampled by the plurality of sample switches by a plurality of hold capacitors is generated. Features.
Further, the signal line driving circuit further includes a plurality of buffers for outputting signals held by the hold capacitors to each of the plurality of signal lines, and the first control signal resets the plurality of hold capacitors. At the same time, the output ends of the plurality of buffers are reset.
Further, the time th required for the plurality of hold capacitors to hold the signals sampled by the plurality of sample switches and the time tr required for resetting the plurality of hold capacitors have a relationship of th> tr. It is characterized by that.

  Further, in an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by a sampling unit that sequentially samples video signals, and the sampling unit. An active matrix liquid crystal display comprising: holding means for holding the video signal; buffer means for amplifying or buffering the video signal held by the hold means; and first control means for controlling the hold means. The above problems are solved by using an apparatus.

  Further, in an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by a sampling unit that sequentially samples video signals, and the sampling unit. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means The above problem is solved by using an active matrix liquid crystal display device having first control means for controlling the second control means and second control means for controlling the reset means.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, the sampling means Sample latch generating means for generating a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and sampling the video signal based on the latch signal Sample switching means for sampling to the holding means, Control means solves the above problem by using an active matrix type liquid crystal display device is composed of a generally equivalent means and the sample latches generating means.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and intermittently receiving the video signal amplified or buffered by the buffer means in the pixel matrix. The above problem is solved by using an active matrix type liquid crystal display device having signal line output means for supplying signal lines.

  Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit holds at least the sampling means for sequentially sampling the video signal and the video signal sampled by the sampling means. Holding means, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, and the sampling means Sample / latch generating means for generating a latch signal for defining a sampling timing from a clock signal, sample holding means for holding the video signal to be sampled, and sampling the video signal into the sample capacity based on the latch signal Active matrix liquid crystal display composed of sample switching means However, the frequency of the clock signal is variable, and the timing signal for controlling the holding means solves the above problem by using an active matrix liquid crystal display device generated from the clock signal by the first control means. To do.

  Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit sequentially samples at least the video signal, and holds the video signal sampled by the sample unit. In an active matrix type liquid crystal display device driving method comprising: means, buffer means for amplifying or buffering the video signal held by the hold means, and reset means for resetting the hold means. An active matrix type liquid crystal characterized in that when a time required to hold a video signal is th and a time required to reset the hold means by the reset means is tr, a relationship of at least th> tr holds. By using the display device drive method Solve the above problems.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting the hold means, and timing for ending the reset operation of the reset means The above problem is solved by using an active matrix type liquid crystal display device having a delay means for controlling the length of time from the start of the hold means to the start timing of the hold operation.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first counting means for controlling the hold means, the sampling means and The above-mentioned problem is solved by using an active matrix liquid crystal display device to which a control clock having a constant frequency is input as the first counting means.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means A first counting means for controlling the resetting means and a second counting means for controlling the resetting means, and the sampling means, the first counting means, and the second counting means have a constant frequency control. By using an active matrix liquid crystal display device to which a clock is input, To resolve.

  Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the reset means A delay means for controlling a time length from a timing at which the reset operation of the hold means to a timing at which the hold operation of the hold means is started, a first counting means for controlling the hold means, and a second for controlling the reset means. Counting means and a third meter for controlling the delay means And an active matrix liquid crystal display device to which a control clock having a constant frequency is input is used for the sample means, the first counting means, the second counting means, and the third counting means. To solve the above problem.

Action

In an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate,
The signal line driving circuit has active means having sampling means for sequentially sampling video signals, holding means for holding the video signals sampled by the sampling means, and first control means for controlling the holding means. By using a matrix type liquid crystal display device,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by the sample unit that sequentially samples video signals and the sample unit. An active matrix liquid crystal display comprising: holding means for holding the video signal; buffer means for amplifying or buffering the video signal held by the hold means; and first control means for controlling the hold means. By using the device
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by the sample unit that sequentially samples video signals and the sample unit. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means By using an active matrix liquid crystal display device having first control means for controlling the second control means and second control means for controlling the reset means,
The signal delay from the first control means to the hold means and the signal delay from the second control means to the reset means are smaller than those of the prior art.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, the sampling means Sample latch generating means for generating a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and sampling the video signal based on the latch signal Sample switching means for sampling to the holding means, Control means, by using the active matrix type liquid crystal display device is composed of a generally equivalent means and the sample latches generating means,
The minimum arrangement of the signal line driver circuit is possible.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and intermittently receiving the video signal amplified or buffered by the buffer means in the pixel matrix. By using an active matrix type liquid crystal display device having signal line output means for supplying signal lines,
A high frequency component other than the video signal is not given to the signal line.

Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit holds at least the sampling means for sequentially sampling the video signal and the video signal sampled by the sampling means. Holding means, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, and the sampling means Sample / latch generating means for generating a latch signal for defining a sampling timing from a clock signal, sample holding means for holding the video signal to be sampled, and sampling the video signal into the sample capacity based on the latch signal Active matrix liquid crystal display composed of sample switching means In location, the clock signal is a frequency variable, by using the active matrix type liquid crystal display device produced from the clock signal by the timing signal said first control means for controlling said hold means,
The time required for the hold means to hold the video signal can be arbitrarily changed externally.

Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit sequentially samples at least the video signal, and holds the video signal sampled by the sample unit. In an active matrix type liquid crystal display device driving method comprising: means, buffer means for amplifying or buffering the video signal held by the hold means, and reset means for resetting the hold means. A driving method of an active matrix type liquid crystal display device in which at least a relation of th> tr is satisfied, where t is a time required to hold a video signal and t r is a time required to reset the hold means by the reset means. By using
The horizontal blanking period can be effectively used to maximize the time during which the buffer means amplifies or buffers the video signal on the signal line.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting the hold means, and timing for ending the reset operation of the reset means By using an active matrix type liquid crystal display device having a delay means for controlling a length of time from the hold means to the timing to start the hold operation of the hold means,
The reset operation and the hold operation do not overlap in time.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first counting means for controlling the hold means, the sampling means and By using an active matrix liquid crystal display device to which a control clock having a constant frequency is input as the first counting means,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means A first counting means for controlling the resetting means and a second counting means for controlling the resetting means, and the sampling means, the first counting means, and the second counting means have a constant frequency control. By using an active matrix liquid crystal display device to which a clock is input,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the reset means A delay means for controlling a time length from a timing at which the reset operation of the hold means to a timing at which the hold operation of the hold means is started, a first counting means for controlling the hold means, and a second for controlling the reset means. Counting means and a third means for controlling the delay means An active matrix type liquid crystal display device to which a control clock having a constant frequency is input is used for the sample means, the first counting means, the second counting means, and the third counting means. By
The scale of the circuit that generates the control clock can be reduced.

  Embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram for explaining an example of a signal line driving circuit of an active matrix panel constituting the active matrix type liquid crystal display device using the first embodiment. The signal line driver circuit is formed on the same substrate as the pixel matrix.

  The shift register SR transfers the selection signal XIN to each bit output of Bit1, Bit2,... Bitm, and turns on / off the sample switch groups SW1,1, SW2,1. Provide for. A level shifter LS is interposed between the shift register and the sample switch group. The level shifter controls the voltage level or the current level of the bit output of the shift register so that the sample switch group performs an on / off operation. Used to pull up or down to a level sufficient to do. However, if the bit output of the shift register is at a level sufficient to turn on and off the sample switch group, the level shifter is unnecessary. The video signal VIDEO is sequentially sampled into sample capacities C1,1, C2,1,... Cm, 1 as the sample switch group is turned on and off in time series, and the sample capacity depends on the video signal. Each voltage value is held. At this time, hold switch groups SW1,2, SW2,2... SWm, 2 provided between the sample capacitors and the hold capacitors C1,2, C2,2... Cm, 2 are hold switch control circuits. Is turned off based on the control signal from. The voltage value held in the sample capacity is finally amplified or buffered by the analog buffers B1, B2,... Bm and output to the signal lines S1, S2,. There is a great difference between the prior art and the present invention.

  According to the prior art shown in FIG. 4, as the output enable signal ENBL supplied from outside the TFT-LCD panel is input, the voltage value held in the sample capacitor CSPL is transferred to the hold capacitor CHLD, The analog buffers B1, B2,... Bm amplify or buffer the voltage value transferred to the hold capacitor and output it to the signal line. On the other hand, in the present invention, a signal corresponding to the output enable signal ENBL can be generated inside the active matrix panel without requiring a complicated circuit configuration. Hereinafter, the description of the present invention will be continued using FIG. 1 again.

  As described above, it is assumed that the sample capacitors C1,1, C2,1,... Cm, 1 continue to hold voltage values corresponding to the video signals. The control clock CLK for controlling the shift operation of the shift register SR is simultaneously input to the output switch control circuit 101, the reset switch control circuit 102, and the hold switch control circuit 103, and the timing of the output signals of these three control circuits is determined. I have control. These three control circuits have a circuit configuration equivalent to the shift register, and further have a circuit configuration in which arithmetic circuits and the like are combined as necessary. Specific circuit configurations of these three control circuits will be described later. The shift register transfers the selection signal XIN to each bit output of Bit1, Bit2,... Bitm in synchronization with the control clock CLK, and then transfers the selection signal to the output switch control circuit 101. At this time, the output switch control circuit outputs a control signal for turning off the output switch groups SW1,3, SW2,3... SWm, 3, and the output terminals of the analog buffers B1, B2. The signal lines S1, S2,... Sm are electrically insulated.

  Next, the selection signal is transferred from the output switch control circuit to the reset / switch control circuit 102 in synchronization with the control clock CLK. At this time, from the reset switch control circuit, the first reset switch group SW1,4, SW2,4... SWm, 4 and the second reset switch group SW1,5, SW2,5. , 5 is output as a control signal. The first reset switch group is provided to control a conduction state between the reset signal line RS and the hold capacitor and the input terminal of the analog buffer. The second reset switch group is provided so as to control a conduction state between the reset signal line and the output terminal of the analog buffer. When the first reset switch group is turned on, the voltage value applied to the reset signal line is written into the hold capacitor almost instantaneously, and the hold capacitor is reset to the voltage value. At the same time, the input terminal of the analog buffer directly connected to the hold capacitor is also reset to the voltage value. When the second reset switch group is turned on, the voltage value applied to the reset signal line is written to the output terminal of the analog buffer, and the output terminal of the analog buffer is reset to the voltage value. Is done. The reason why the output terminal as well as the input terminal of the analog buffer is reset is to stabilize the output at a speed higher than the slew rate of the analog buffer.

  After the hold capacitor and the input / output terminal of the analog buffer are reset, the selection signal is transferred from the reset switch control circuit 102 to the hold switch control circuit 103 in synchronization with the control clock. . At the same time, the reset switch control circuit outputs a control signal for turning off the first reset switch group and the second reset switch group. The hold switch control circuit outputs a control signal for turning on the hold switch groups SW1,2, SW2,2... SWm, 2. Accordingly, the hold switch group becomes conductive, and the voltage value held in the sample capacitors C1,1, C2,1... Cm, 1 becomes the hold capacitors C2,1, C2,2. Transfer to 2 almost instantaneously. The voltage value transferred to the hold capacitor is amplified or buffered by the analog buffer and output from the analog buffer.

  Next, the selection signal is transferred from the hold switch control circuit to the output switch control circuit in synchronization with the control clock. At this time, the hold switch control circuit outputs a signal for turning off the hold switch group, and ends the transfer of the voltage value from the sample capacitor to the hold capacitor. On the other hand, the output switch control circuit outputs a control signal for turning on the output switch group. As a result, the output terminal of the analog buffer and the signal line are connected, and the voltage value amplified or buffered by the analog buffer is output to the signal line. A period until the output switch control circuit outputs an OFF control signal again, that is, the shift register transfers a new selection signal XIN to each bit of Bit1, Bit2,... Bitm, and a new video signal VIDEO. In this period, the output terminal of the analog buffer and the signal line are kept in an electrically connected state until the sampling of the signal into the sample capacity is completed, and the signal writing to the signal line is continued. . By repeating the above operation, an arbitrary video signal can be transferred to each signal line, and a video can be displayed on the active matrix liquid crystal display device.

  By using the present invention, there is no need to create a control signal corresponding to the output enable signal ENBL for controlling the timing of transferring the voltage value from the sample capacitor to the hold capacitor outside the TFT-LCD panel. For this reason, since the number of mounting terminals used for connecting the TFT-LCD panel and an external circuit can be reduced, there are advantages such as a reduction in the number of mounting processes and an improvement in yield during mounting. The output switch control circuit, the reset switch control circuit, and the hold switch control circuit have a circuit configuration equivalent to the shift register or include many parts having an equivalent circuit configuration. Above, most of these three control circuits can be designed simply by increasing the number of bits of the shift register. Therefore, the circuit layout area can be minimized, and the TFT-LCD panel can be narrowed. In addition, since design addition is greatly reduced as compared with the addition of a special circuit configuration, the cause of a design error can be eliminated in advance. Further, in the conventional method of supplying the output enable signal from the mounting terminal, an electrostatic protection circuit for preventing circuit destruction due to static electricity is often provided in the vicinity of the mounting terminal on the TFT-LCD panel, but the electrostatic protection circuit is extremely large. Usually, it has a parasitic capacitance, and this unavoidably delays the output enable signal. On the other hand, according to the present invention, since an electrostatic protection circuit is unnecessary, an output enable signal without delay can be obtained. As a result, the timing of signal transfer from the sample capacity to the hold capacity is accurately determined, and erroneous signals can be reliably prevented from being captured.

In the present invention, the output of the analog buffer is intermittently applied to the signal line using the output switch group and the output switch control circuit.
This is provided so that the voltage of the reset signal line is not applied to the signal line when the output of the analog buffer is reset by the second reset switch group. In the case of a conventional signal line driving circuit, the signal line is also reset, so that an originally unnecessary high frequency is superimposed on the signal line. In the present invention, since only the video signal can be applied to the signal line by the function of the output switch group and the output switch control circuit, it is possible to suppress the occurrence of domain due to abnormal alignment of liquid crystal sealed in the vicinity of the signal line, An active matrix type liquid crystal display device having a high contrast ratio without light leakage from the domain can be realized. Further, the signal line output means can prevent wasteful charge and discharge of the capacitance parasitic on the signal line by the buffer means, so that the power consumption of the signal line driver circuit can be reduced.

  Hereinafter, the first embodiment of the present invention will be described more specifically. First, the case where the shift register SR of FIG. 1 is constituted by the D-flip flop shown in FIG. 5A will be described. FIG. 6 is a diagram illustrating an example of a specific circuit configuration of the portion 106 in FIG. The terminal 601 is a terminal for inputting a selection signal transferred from the shift register SR of FIG. The wiring 602 controls the first reset switch groups SW1,4, SW2,4... SWm, 4 and the second reset switch groups SW1,5, SW2,5. Wiring connected to the terminal. The wiring 603 is a wiring connected to the control terminals of the hold switch groups SW1,2, SW2,2,... SWm, 2 in FIG. The wiring 604 is a wiring connected to the control terminals of the output switch groups SW1,3, SW2,3... SWm, 3 in FIG. Note that a level shifter LS may be interposed between the wirings 602, 603, and 604 and each switch group to raise or lower the voltage level or current level. The output switch control circuit 101 includes D-flip flops 605 and 607, a resettable D-flip flop 606, and a NOR gate 608. The reset switch control circuit 102 and the hold switch control circuit 103 are constituted by D-flip flops themselves. In this embodiment, D-flip-flops synchronized with the control clock CLK are arranged in the order of 605 → 102 → 103 → 607, and this circuit configuration is equivalent to the circuit configuration of the shift register in FIG. it is obvious.

  Next, the operation of the circuit of FIG. 6 will be described with reference to the timing chart shown in FIG. In the following description, FIG.

  First, in a period excluding the horizontal blanking period 802 in the horizontal scanning period 801, the shift register SR of FIG. 1 sequentially outputs a selection pulse to each bit of Bit1, Bit2... Bitm in synchronization with the control clock CLK. . At this time, as described above, the signal corresponding to the video signal is sampled in the sample capacity provided for each bit. On the other hand, the selection pulse output to the mth bit Bitm is also input to the terminal 601 at the same time.

  [Period 803] Upon receiving the selection pulse, the output terminal Q (point P61) of the D-flip flop 605 outputs a high level voltage for the next one clock of the control clock. This is input to the clock terminal CK of the D-flip flop 606, and the output terminal Q (point P65) of the D-flip flop 606 changes from the low level to the high level. Here, since the D-flip flop 606 constitutes a 1-bit counter, a pulse signal is input again to the clock terminal CK (point P61), or a high level signal is input to the reset terminal R. This state will be maintained until it is done. The NOR gate 608 receives the high level signal at the point P65 and outputs a low level signal to the wiring 604 (point P66). Thus, in the period 803, the output switch groups SW1,3, SW2,3... SWm, 3 for controlling the conduction state between the output terminals of the analog buffer group and the signal lines in FIG. -Prevent the output signal of the buffer group from being transmitted to the signal line.

  [Period 804] During the next one clock of the control clock, the output terminal Q (point P62) of the D-flip flop also serving as the reset switch control circuit 102 and the wiring 602 become high level, and the first reset switch The groups SW1,4, SW2,4... SWm, 4 and the second reset switch groups SW1,5, SW2,5. Thus, in the period 804, the input / output terminals of the analog buffer group and the hold capacitors C1,2, C2,2,... Cm, 2 are reset to the voltage level of the reset signal line RS. Simultaneously with the end of the period 804, the output terminal Q of the D-flip flop also serving as the reset switch control circuit 102 becomes low level, and the first reset switch group and the second reset switch group are in a non-conductive state. It becomes.

  [Period 805] During the next one clock of the control clock, the output terminal Q (point P63) of the D-flip flop that also serves as the hold switch control circuit 103 and the wiring 603 are at the high level, and the hold switch group SW2, 1, SW2,2... SWm, 2 become conductive. As a result, signals are transferred from the sample capacitors C1,1, C2,1... Cm, 1 to the hold capacitor, and each analog buffer amplifies or buffers the signal and outputs it from the output terminal. Thus, in the period 805, a signal is written to the hold capacitor, and the output of the analog buffer is stabilized. Simultaneously with the end of the period 805, the output terminal Q of the D-flip flop also serving as a hold switch control circuit becomes a low level, and the hold switch group becomes non-conductive. As a result, the sample capacitor and the hold capacitor are electrically insulated, and the hold capacitor continues to hold the voltage value at the end of the period 805 until the first reset switch group is opened again.

  [Period 806] During the next one clock of the control clock, the output terminal Q (point P64) of the D-flip flop 607 goes high, and the resettable D flip-flop 606 connected to the output terminal is reset. Since a high level is input to the terminal R, the resettable D-flip flop is reset and the output terminal Q (point P65) outputs a low level. At this time, the two input terminals of the NOR gate, point P64 and point P65, are at the high level and the low level, respectively, and the output (point P66) is still at the low level. Remains.

  At the same time as the next clock of the control clock is input, the output terminal Q (point P64) of the D-flip flop becomes low level, and the two input terminals of the NOR gate both become low level and output. (Point P66) is at a high level. As a result, the output switch group becomes conductive, and the signal held in the Hall capacitance is amplified or buffered and output from the analog buffer to the signal line.

  When the above series of operations is completed and the horizontal blanking period 802 is completed, the series of operations starting from the sampling of the video signal by the shift register is repeated. As described above, a latch signal for controlling each switch group can be obtained inside the signal line driving circuit of the active matrix liquid crystal display device.

  In the timing chart of FIG. 8, the lengths of the periods 803 to 806 are different. This is because the time required to complete the operation performed in each period is different. In a general video signal, the horizontal blanking period 802 has only about 20% of the time of the horizontal scanning period 801. Therefore, it is necessary to effectively distribute each of the above periods within the horizontal blanking period. In the period 804, the input / output capacitor and the hold capacitor of the analog buffer are charged / discharged to the voltage level applied to the reset signal line, so the period 804 takes the longest time among these periods 803 to 806. . Next, a period 805 requires time, and in the period 805, the video signal is transferred from the sample capacity to the hold capacity. Since the transfer is performed by capacitive coupling through the hold switch group, it can be at least shorter than the period 804. If the period 805 is too short, the transfer is not performed sufficiently, which may cause a problem in accuracy. Therefore, a certain amount of time is required depending on the required accuracy. On the other hand, in the period 803, only the time to turn off the output switch group is required, and in the period 806, only the time to turn on the output switch group is required. The period 803 and the period 806 may be shorter than the period 805 because a margin may be provided for the delay of the output switch control circuit. Accordingly, at least the relationship of period 804> period 805 is satisfied, and further, the relationship of period 804> period 805> period 803≈period 806 is satisfied. This relationship is not an absolute condition, but can be considered as a condition that minimizes the time allocated to the periods 803 to 806. In other words, that the above condition is satisfied means that the output switch is on for the longest time. This has an advantage that the analog buffer group can sufficiently write to the signal line.

  Now, the time of each period is different for each active matrix liquid crystal display device having different specifications. Here, the timing of each period is variably controlled by changing the frequency of the control clock. In this way, only the circuit that generates the control clock needs to be variable, and the versatility of the external circuit is enhanced, and the manufacturing cost of the active matrix liquid crystal display device is reduced.

  Next, the case where the shift register SR of FIG. 1 is configured by a clocked inverter and an AND gate shown in FIG. 5B will be described. FIG. 9 is a diagram illustrating an example of a specific circuit configuration of the portion 106 in FIG. A terminal 901 is a terminal that receives a transfer signal from the shift register SR. The wiring 902 is a wiring that connects the reset switch control circuit 102 to the control terminals of the first reset switch group and the second reset switch group. The wiring 903 is a wiring that connects the hold switch control circuit 103 and the control terminal of the hold switch group. The wiring 904 is a wiring that connects the output switch control circuit 101 and the control terminal of the output switch group. Reference numerals 905 and 906 denote N-type thin film transistors. All the clocked inverters in the figure operate as inverters only when the control signal is at a high level. In the example of FIG. 9, these three control circuits are mainly composed of clocked inverters, and among them, the reset switch control circuit and the hold switch control circuit are the same as those of the shift register shown in FIG. It can be seen that the circuit configuration is equivalent. Functionally, it is almost the same as the circuit shown in FIG.

  Next, the circuit operation will be briefly described with reference to the timing chart shown in FIG. In order to drive the clocked inverter type shift register and the control circuit as shown in FIG. 9, a control clock CLK and a control clock CLK * having an exclusive logic relationship with the control clock are required. Here, it is assumed that an exclusive logic of the control clock CLK is obtained in advance using an inverter or the like to obtain the control clock CLK *.

  First, immediately before the horizontal blanking period 802 is entered, the selection signal of the mth bit Bitm is input to the terminal 901.

[Period 121] In the horizontal scanning period 802, the control clock CLK becomes high level, the clocked inverter controlled by the control clock CLK operates, and the selection signal is transferred to the point P91 and the point P92. The Point P92 goes high, causing clocked inverter 908 to operate as an inverter. At this time, since the point P92 is at the high level, the N-type thin film transistor 905 is in a conductive state, and the point P99 is fixed to the ground voltage (low level). Since the point P91 is at a low level, the clocked inverter 907 does not function as an inverter.
Therefore, the point P98 that is the output terminal of the clocked inverter 903 is at a high level. Since the point P98 connected to the input terminal of the NOR gate 909 is at a high level, the NOR gate outputs a low level. As a result, the output switch group connected to the wiring 904 is turned off.

  [Period 122] Next, when the control clock CLK becomes low level, the reset switch control circuit 102 outputs a high level to the point P93, and the first reset switch group and the second switch group are turned on. It becomes. Thus, as described above, the hold capacitor and the output terminal of the analog buffer group are applied to the voltage of the reset signal line and reset.

  [Period 123] Next, when the control clock CLK becomes high level again, the hold switch control circuit 103 outputs a high level to the point P94, and the hold switch group is turned on. At the same time, the first reset switch group and the second reset switch group are turned off, and the voltage value held in the sample capacitor is transferred to the hold capacitor. On the other hand, in the output switch control circuit, since the point P91 becomes a high level, the clocked inverter 907 starts the inverter operation. Since both the clocked inverters 907 and 908 are operating as inverters, the input / output terminals P98 and P99 are stabilized at a high level and a low level, respectively.

  [Period 124] Next, when the control clock CLK becomes low level again, the point P95 becomes low level, so that the gate terminal of the N-type thin film transistor 906 becomes high level, and the N-type thin film transistor becomes conductive. At this time, since the clocked inverter 908 does not function as an inverter at the same time, the point P98 is fixed to the ground voltage (low level). At this time, since the input terminal (point P96) of the NOR gate 909 is at the high level, the output (point P97) of the NOR gate remains at the low level.

  Next, when the control clock CLK becomes high level again, the point P95 becomes high level and the point P96 becomes low level. When the point P95 becomes high level, the clocked inverter 908 starts the inverter operation, and continues to fix the point P98 to low level. Since the two input terminals of the NOR gate 909, the point P96 and the point P98, are both at a low level, the NOR gate outputs a high level to the wiring 904 (point P97). Thus, the output switch group is turned on, and the output of the analog buffer group can be written to the signal line.

  An arbitrary video signal can be written to each signal line by performing the above series of operations for each horizontal scanning period.

  Here, the high level / low level used in the description of the text means a voltage level corresponding to the correctness / incorrectness of the circuit logic operation. In addition, the plurality of switch groups described above are in a conductive state (ON) when the control signal is at a high level, and are in an insulating state (OFF) when the control signal is at a low level. Is assumed.

  Next, a specific circuit configuration will be described for the portion 107 in FIG. 1 including each switch group, analog buffer, and the like. FIG. 7 is a diagram illustrating a specific configuration of the portion 107 in FIG. In the figure, the sample switch groups SW1,1, SW2,1,..., The hold switch groups SW1,2, SW2,2,... And the output switch groups SW1,3, SW2,3. It consists of a double complementary transfer gate. In the figure, the first reset switch group SW1,4, SW2,4... And the second reset switch group SW1,5, SW2,5... Are composed of analog switches made of N-type thin film transistors. Has been. The sample switch group, the hold switch group, the first reset switch group, the second reset switch group, and the output switch group are either a complementary transfer gate, an N-type thin film transistor, or a P-type thin film transistor. You may comprise. Any of these may be constituted by a rectifying element such as a thin film diode.

  In the description of the first embodiment, the shift register, the sample switch group, and the sample capacitor are shown as the sample means, the hold switch group and the hold capacitor are shown as the hold means, and the sample means and the hold means are An output switch control circuit, a hold switch control circuit, and a sample switch control circuit are shown as control means for controlling. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driver circuit are formed on the same substrate, the signal line driver circuit sequentially samples the video signal, and the sample unit samples It can be said that the present invention has a holding means for holding the video signal and a first control means for controlling the holding means.

  In the description of the first embodiment, the analog buffer is shown as the buffer means. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driver circuit are formed on the same substrate, the signal line driver circuit sequentially samples the video signal, and the sample unit samples And holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means. It can be said that this is a feature of the invention.

According to the present invention, the control signal generated by the control means is transmitted to the hold means and the sampling means with almost no delay, so that erroneous signals can be prevented from being taken in. The control signal is generated on the same substrate by the control means and does not need to be supplied from the outside of the same substrate, so the number of mounting terminals can be reduced.
This has the effect of reducing the number of mounting processes and improving the yield in the mounting process.

In the description of the first embodiment, the reset switch group and the reset signal line are shown as the reset means. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driver circuit are formed on the same substrate, the signal line driver circuit sequentially samples the video signal, and the sample unit samples A hold means for holding the video signal, a buffer means for amplifying or buffering the video signal held by the hold means, a reset means for resetting at least one of the hold means or the buffer means, and the hold It can be said that the present invention is characterized by having first control means for controlling the means and second control means for controlling the reset means.
According to the present invention, the control signal generated by the control means is transmitted to the sample means, the hold means, and the reset means with almost no delay, so that erroneous signals can be prevented from being taken in. Conventionally, the control signal of the reset unit and the control signal of the hold unit may overlap in time due to the delay of the control signal, and the reset signal leaks to the video signal transferred to the hold unit. There was a thing. In the present invention, since there is almost no delay of the control signal, it is possible to prevent the reset signal from leaking.

  In the description of the first embodiment, the shift register is shown as sample / latch generating means for generating a latch signal for defining the timing for sampling the video signal, and the sample holding for holding the sampled video signal. A sample capacity is shown as a means, and a dual complement transfer gate is shown as a sample switching means for sampling the video signal to the sample holding means based on the latch signal. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least a sampling unit that sequentially samples video signals, and the sampling unit. Hold means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means; Means for generating a latch signal for defining a timing for sampling the video signal; sample holding means for holding the video signal to be sampled; and the video signal based on the latch signal. It consists of sample switching means to sample to sample holding means It said first control means can be said to consist of roughly equivalent means and the sample latches generating means is a feature of this invention. According to the present invention, the control means can be configured only by increasing the number of output bits of the sample / latch generating means, so that the circuit layout area can be minimized, and hence the active matrix type liquid crystal display device can be reduced. . In addition, there is an advantage that the cause of design errors can be reduced as compared with the case where the control unit is designed with a completely different configuration from the sample latch generation unit.

  In the description of the first embodiment, the output switch group and the output switch are used as signal line output means for intermittently supplying the video signal amplified or buffered by the buffer means to the signal lines of the pixel matrix. Control circuit is shown. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least a sampling unit that sequentially samples video signals, and the sampling unit. Hold means for holding the sampled video signal; buffer means for amplifying or buffering the video signal held by the hold means; and the pixel matrix intermittently for the video signal amplified or buffered by the buffer means It can be said that it is a feature of the present invention to have signal line output means for supplying to the signal line. According to the present invention, since a high frequency component other than the video signal is not given to the signal line, the alignment state of the liquid crystal sealed in the vicinity of the signal line is not changed unnecessarily. Accordingly, generation of a liquid crystal domain due to abnormal alignment can be suppressed and light leakage due to the domain can be prevented, so that an active matrix liquid crystal display device with high image quality can be realized. Further, the signal line output means can prevent unnecessary parasitic charge and discharge on the signal line by the buffer means, so that the power consumption of the active matrix liquid crystal display device can be reduced. .

  In the description of the first embodiment, the sample / latch signal output from the sample control circuit is shown as a timing signal for controlling the sample means, and the hold control circuit is used as a timing signal for controlling the hold means. The hold latch signal to be output is shown. Accordingly, the pixel matrix and at least the signal line driving circuit are formed on the same substrate, and the signal line driving circuit includes at least sampling means for sequentially sampling the video signal, and the video signal sampled by the sampling means. Hold means for holding, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, the sampling means comprising the video signal Sample / latch generating means for generating a latch signal that defines the timing for sampling the video signal from the clock signal, sample holding means for holding the sampled video signal, and the video signal to the sample capacity based on the latch signal Active matrix type liquid comprising sample switching means for sampling In the display device, the clock signal is a frequency variable, it can be said that the timing signal for controlling the holding means by the first control means to be generated from the clock signal, which is a feature of the present invention. According to the present invention, the holding timing can be made variable only by changing the frequency of the clock signal. When the signal line driver circuit of the present invention is used, the external circuit can be shared by the active matrix liquid crystal display devices having different specifications, so that the manufacturing cost of the external circuit can be reduced. In addition, even in an active matrix liquid crystal display device of the same specification, a timing shift due to characteristic variations can be compensated by an external circuit, and a defective product can be relieved.

  In the description of the first embodiment, the period 805 and the period 123 are set as the time th required for holding the video signal by the hold means, and the time required for resetting the hold means by the reset means. A period 804 and a period 122 are shown as tr. Accordingly, the pixel matrix and at least the signal line driving circuit are formed on the same substrate, and the signal line driving circuit holds at least the video signal sampled by the sampling means and the sampling means for sequentially sampling the video signals. In a driving method of an active matrix liquid crystal display device, comprising: a holding unit; a buffer unit that amplifies or buffers the video signal held by the holding unit; and a reset unit that resets the holding unit. Driving an active matrix type liquid crystal display device in which at least a relationship of th> tr is established, where t is a time required to hold the video signal and t r is a time required to reset the hold means by the reset means. It can be said that the method is a feature of the present invention. The According to the present invention, the horizontal blanking period can be effectively used, and the time for the buffer means to amplify or buffer the video signal to the signal line can be maximized. Therefore, the video signal is sufficiently written to the signal line, and a high contrast active matrix liquid crystal display device can be realized.

(Second embodiment)
FIG. 11 is a diagram for explaining an example of a signal line driving circuit of an active matrix panel constituting the active matrix type liquid crystal display device using the second embodiment. FIG. 11 shows a circuit corresponding to the portion 106 of FIG. Therefore, in the second embodiment, only the portion 106 in FIG. 1 is replaced with the circuit in FIG. 11, and FIG. The signal line driver circuit is formed on the same substrate as the pixel matrix.

  In this figure, a delay circuit 112 is provided between the reset switch control circuit 102 and the hold switch control circuit 103. In the delay circuit, the reset switch group and the hold switch group are turned on simultaneously, the voltage level applied to the reset signal line continues to leak to the hold capacitor, and the transfer of the video signal from the sample capacitor to the hold capacitor is prevented. It is provided to prevent the phenomenon that it is not performed accurately. When the circuit described in the first embodiment functions as designed, the reset switch group and the hold switch group do not turn on at the same time, but such a phenomenon rarely occurs. For example, when the control signal output from the reset switch control circuit is delayed due to variations in the characteristics of the thin film transistors constituting the reset switch control circuit, the timing at which the reset switch group is turned off and the Since the timing when the hold switch group is turned on is almost the same, these timings may overlap. In addition, this phenomenon is also observed when the delay from the reset switch control circuit to the reset switch group is larger than the delay from the hold switch control circuit to the hold switch group. Therefore, in the second embodiment, by providing the delay circuit 112, at least the reset switch group and the hold switch group are prevented from being turned on at the same time.

  In FIG. 11, the delay circuit is controlled by the control clock CLK, but it is not necessarily controlled by the control clock. For example, when a CR integration circuit is used as the delay circuit, it is not necessary to connect the control clock.

  Next, an example of a specific circuit configuration of the second embodiment will be described with reference to FIGS. FIG. 12 is a diagram illustrating a specific circuit configuration of the delay circuit 112 when a D-flip flop is used as the shift register (see FIG. 5A). FIG. 13 is a timing chart for explaining the operation of FIG. The delay circuit 112 shown in FIG. 12 is composed of a D-flip-flop, and has a configuration substantially equivalent to the shift register, reset switch control circuit, hold switch control circuit, and output switch control circuit. From the circuit configuration of the shift register in units of output bits, it can be seen that the delay circuit can be realized by adding only one bit to the circuit of FIG. For this reason, the signal line drive circuit can be narrowed as in the first embodiment. Further, there is no increase in load at the design stage caused by adding a delay circuit, and factors such as design errors can be removed in advance. From the viewpoint of operation, as can be understood by comparing FIG. 13 and FIG. 8, the period 323 in which the reset switch group is in the ON state (corresponding to the period 804 in FIG. 8) and the hold switch group A delay period 324 by the delay circuit is provided between the period 325 in which the signal is on (corresponding to the period 805 in FIG. 8). When the delay period 324 is sufficiently longer than the time for the reset switch group to transition from the on state to the off state, the reset switch group and the hold switch group do not turn on at the same time. Thereby, since the video signal is accurately transferred from the sample capacitor to the hold capacitor, a highly accurate signal line driving circuit can be realized.

Further, an example of a specific circuit configuration of the second embodiment will be described with reference to FIGS. FIG. 14 is a diagram illustrating a specific circuit configuration of the delay circuit 112 when a clocked inverter is mainly used as a shift register (see FIG. 5B). FIG. 15 is a timing chart for explaining the operation of FIG.
The delay circuit 112 in FIG. 14 is mainly composed of a clocked inverter, and has a configuration substantially equivalent to the shift register, reset switch control circuit, hold switch control circuit, and output switch control circuit. From the configuration of the output bit unit of the shift register, it can be seen that the delay circuit is realized by adding only one bit to the circuit of FIG. For this reason, the signal line drive circuit can be narrowed as in the first embodiment. Further, there is no increase in load at the design stage caused by adding a delay circuit, and factors such as design errors can be removed in advance. From the viewpoint of operation, as can be understood by comparing FIG. 15 and FIG. 10, the period 513 in which the reset switch group is in the ON state (corresponding to the period 122 in FIG. 10) and the hold switch group A delay period 514 by the delay circuit is provided between a period 515 in which is turned on (corresponding to a period 123 in FIG. 10). When the delay period 514 is sufficiently longer than the time for the reset switch group to transition from the on state to the off state, the reset switch group and the hold switch group do not turn on at the same time. Thereby, since the video signal is accurately transferred from the sample capacitor to the hold capacitor, a highly accurate signal line driving circuit can be realized.

  In the description of the second embodiment, the delay circuit is shown as the delay means. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least a sampling unit that sequentially samples video signals, and the sampling unit. A hold means for holding the sampled video signal, a buffer means for amplifying or buffering the video signal held by the hold means, a reset means for resetting the hold means, and a reset operation of the reset means are terminated. It can be said that it is a feature of the present invention to have delay means for controlling the length of time from the timing to the start timing of the hold operation of the hold means. According to the present invention, the period during which the reset unit performs the reset operation and the period during which the hold unit performs the hold operation do not overlap, and the video signal can be transferred from the sample unit to the hold unit with high accuracy. An active matrix liquid crystal display device having excellent gradation resolution display capability can be realized.

(Third embodiment)
FIG. 16 is a diagram for explaining an example of a signal line driving circuit of an active matrix panel constituting an active matrix type liquid crystal display device using the third embodiment. FIG. 16 shows a circuit corresponding to the portion 106 in FIG. Therefore, in the third embodiment, only the portion 106 in FIG. 1 is replaced with the circuit in FIG. 16, and FIG. The signal line driver circuit is formed on the same substrate as the pixel matrix.

  The main part of the circuit configuration is the same as in FIG. 11 used in the description of the second embodiment, but the control signal for setting the reset switch control circuit, the delay circuit and the hold switch control circuit is set to the control clock CLK. It is supplied from count circuits 610, 611, and 612 that count the number. In the first and second embodiments, the operation time of each control circuit is controlled by changing the frequency of the control clock. In the third embodiment, the control clock CLK is used as the shift register. The operation frequency of each control circuit is controlled by counting the set number of control clocks by the count circuit. The count end set number of the count circuit can be obtained by, for example, a method in which a ROM of several bits is provided in the count circuit or a method in which data for several bits is supplied from an external circuit through a mounting terminal. In the figure, an arrow on the upper side of the count circuits 610, 611, and 612 represents a count start signal, and an arrow on the right side represents a reset signal.

  By providing the count circuit between the control clock and each control circuit, the control clock need not be variable. Since the clock generation circuit of the external circuit only needs to be an oscillation circuit having a constant frequency, the circuit configuration becomes simpler, so that a highly accurate control clock can be generated. In addition, cost reduction and power saving can be achieved by reducing the circuit scale around the clock generation circuit.

  Next, an example of a specific circuit configuration of the third embodiment will be described. FIG. 17 is a diagram for explaining a specific circuit configuration of the portion 106 in FIG. 16 when a D-flip-flop is used for the shift register (see FIG. 5A). FIG. 18 is a diagram for explaining the operation of the circuit of FIG. The count circuit 610 receives the high level output of the D-flip flop 715 of the output switch control circuit 101 and starts to count the control clock CLK. The count circuit 610 counts the control clock until the set number is reached, and then outputs a clock to the clock terminal CK of the D-flip-flop that functions as the reset switch control circuit 102. The reset switch control circuit 102 resets A high level signal for turning on the switch group is output to the wiring 712. Similarly, the output from the count circuit 611 is input to the clock terminal CK of the D-flip flop that functions as the delay circuit 112, and the output from the count circuit 612 is the output of the D-flip flop that functions as the hold switch control circuit 103. Input to clock terminal CK. Thus, the period 813 during which the reset switch control circuit turns on the reset switch group, the period 814 delayed by the delay circuit, and the period 815 during which the hold switch control circuit turns on the hold switch group. Can be controlled by the set count numbers of the count circuits 610, 611, and 612.

  In the third embodiment, the counting circuit 612 is shown as the first counting means, the counting circuit 610 is shown as the second counting means, and the counting circuit 611 is shown as the third counting means. Accordingly, in the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least a sampling unit that sequentially samples video signals, and the sampling unit. Hold means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first counting means for controlling the hold means, the sampling means In addition, it can be said that it is a feature of the present invention to use an active matrix liquid crystal display device to which a control clock having a constant frequency is input as the first counting means.

  Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means A first counting means for controlling the resetting means and a second counting means for controlling the resetting means, and the sampling means, the first counting means, and the second counting means have a constant frequency control. It is possible to use an active matrix liquid crystal display device to which a clock is input. It can be said to be a butterfly.

  Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the reset means A delay means for controlling a time length from a timing at which the reset operation of the hold means to a timing at which the hold operation of the hold means is started, a first counting means for controlling the hold means, and a second for controlling the reset means. Counting means and a third means for controlling the delay means An active matrix type liquid crystal display device to which a control clock having a constant frequency is input is used for the sample means, the first counting means, the second counting means, and the third counting means. This is a feature of the present invention.

  According to the present invention, the scale of the circuit that generates the control clock can be reduced, and a highly accurate clock can be obtained. Further, power consumption of the active matrix liquid crystal display device can be reduced by reducing the circuit scale.

(Fourth embodiment)
19, 20 and 21 are diagrams for explaining an example of a signal line driving circuit of an active matrix panel constituting an active matrix type liquid crystal display device using the fourth embodiment. The signal line driver circuit is formed on the same substrate as the pixel matrix.

  In FIG. 19, only the reset switch control circuit 921 and the hold switch control circuit 922 are added to the rear part of the mth bit of the shift register SR. The difference from the first embodiment is that there is no output switch group and there is no output switch control circuit for controlling it. In the first embodiment, the output switch group and the output switch control circuit are provided for the purpose of controlling the conduction state between the analog buffer groups B1, B2,... Bm and the signal lines S1, S2,. It was. However, a small active matrix liquid crystal display device has a large area limitation, and the output switch group and the output switch control circuit may not be arranged. That is, in order to arrange a circuit for controlling the sample switch group, the reset switch group, and the hold switch group on the same substrate as the pixel matrix with a minimum area, the signal line driver circuit portion 920 has a reset switch control. It is optimal to configure the circuit and a hold switch control circuit. Note that the frequency of the control clock CLK in FIG. 19 is variable.

  In FIG. 20, the frequency of the control clock in FIG. 19 is changed to a constant frequency, and the reset switch control circuit 921 and the hold switch control circuit 922 are controlled by the count circuits 925 and 926, respectively. This effect is the same as that of the third embodiment. Since the output switch control circuit and the output switch group are not provided, the total circuit area is smaller than that of the third embodiment.

  In FIG. 21, a delay circuit 927 is provided between the reset switch control circuit 921 and the hold switch control circuit 922. This effect is the same as in the second embodiment. Since the output switch control circuit and the output switch group are not provided, the total area of the circuit is smaller than that of the second embodiment.

  From the description of the fourth embodiment, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit samples the video signal sequentially. Hold means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means It can be said that it is a feature of the present invention. In the active matrix liquid crystal display device in which the pixel matrix and at least the signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by the sampling means for sequentially sampling the video signal, and the sampling means. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means It can be said that it is a feature of the present invention to use an active matrix type liquid crystal display device having first control means for controlling the second control means and second control means for controlling the reset means.

  According to the present invention, since the control signals generated by the first control means and the second control means are transmitted to the hold means and the sample means with almost no delay, erroneous signals can be captured in advance. Is prevented. The control signal is generated by the first control means and the second control means and does not need to be supplied from outside the same substrate, so that the number of mounting terminals can be reduced. In addition, since the total area of the signal line driver circuit is reduced, the active matrix liquid crystal display device can be reduced in size.

In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line driving circuit are formed on the same substrate, the signal line driving circuit includes a sampling means for sequentially sampling video signals, and the sampling means sampled by the sampling means. By using an active matrix type liquid crystal display device having a hold means for holding a video signal and a first control means for controlling the hold means,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by the sample unit that sequentially samples video signals and the sample unit. An active matrix liquid crystal display comprising: holding means for holding the video signal; buffer means for amplifying or buffering the video signal held by the hold means; and first control means for controlling the hold means. By using the device
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit is sampled by the sample unit that sequentially samples video signals and the sample unit. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means By using an active matrix liquid crystal display device having first control means for controlling the second control means and second control means for controlling the reset means,
Since the control signals generated by the first control means and the second control means are transmitted to the hold means and the sample means with almost no delay, erroneous signals can be prevented from being taken in beforehand. The control signal is generated by the first control means and the second control means and does not need to be supplied from outside the same substrate, so that the number of mounting terminals can be reduced. This has the effect of reducing the number of mounting processes and improving the yield in the mounting process. Conventionally, the control signal of the reset unit and the control signal of the hold unit may overlap in time due to the delay of the control signal, and the reset signal leaks to the video signal transferred to the hold unit. However, in the present invention, since there is almost no delay of the control signal, it is possible to prevent the reset signal from leaking.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, the sampling means Sample latch generating means for generating a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and sampling the video signal based on the latch signal Sample switching means for sampling to the holding means, Control means, by using the active matrix type liquid crystal display device is composed of a generally equivalent means and the sample latches generating means,
Since the first control means can be configured only by increasing the number of output bits of the sample / latch generation means, the circuit layout area can be minimized, and consequently, the active matrix liquid crystal display device can be reduced in size. . In addition, there is an advantage that design load and design error factors can be reduced as compared with the case where the control unit is designed with a completely different configuration from the sample latch generation unit.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and intermittently receiving the video signal amplified or buffered by the buffer means in the pixel matrix. By using an active matrix type liquid crystal display device having signal line output means for supplying signal lines,
Since no high frequency components other than the video signal are given to the signal line, the alignment state of the liquid crystal sealed in the vicinity of the signal line is not changed unnecessarily. Accordingly, generation of a liquid crystal domain due to abnormal alignment can be suppressed and light leakage due to the domain can be prevented, so that an active matrix liquid crystal display device with high image quality can be realized. Further, the signal line output means can prevent unnecessary parasitic charge and discharge on the signal line by the buffer means, so that the power consumption of the active matrix liquid crystal display device can be reduced. .

A high frequency component other than the video signal is not given to the signal line.

Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit holds at least the sampling means for sequentially sampling the video signal and the video signal sampled by the sampling means. Holding means, buffer means for amplifying or buffering the video signal held by the hold means, and first control means for controlling the hold means, and the sampling means Sample / latch generating means for generating a latch signal for defining a sampling timing from a clock signal, sample holding means for holding the video signal to be sampled, and sampling the video signal into the sample capacity based on the latch signal Active matrix liquid crystal display composed of sample switching means In location, the clock signal is a frequency variable, by using the active matrix type liquid crystal display device produced from the clock signal by the timing signal said first control means for controlling said hold means,
The holding timing can be made variable simply by changing the frequency of the clock signal. When the signal line driver circuit of the present invention is used, the external circuit can be shared by the active matrix liquid crystal display devices having different specifications, so that the manufacturing cost of the external circuit can be reduced. Further, even in an active matrix liquid crystal display device having the same specifications, it is possible to compensate for a timing shift due to a variation in characteristics, and it is possible to relieve what has been a defective product in the past.

Further, the pixel matrix and at least the signal line driver circuit are formed on the same substrate, and the signal line driver circuit sequentially samples at least the video signal, and holds the video signal sampled by the sample unit. In an active matrix type liquid crystal display device driving method comprising: means, buffer means for amplifying or buffering the video signal held by the hold means, and reset means for resetting the hold means. A driving method of an active matrix type liquid crystal display device in which at least a relation of th> tr is satisfied, where t is a time required to hold a video signal and t r is a time required to reset the hold means by the reset means. By using
The horizontal blanking period can be effectively used to maximize the time during which the buffer means amplifies or buffers the video signal on the signal line. Therefore, the video signal is sufficiently written to the signal line, and a high contrast active matrix liquid crystal display device can be realized.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting the hold means, and timing for ending the reset operation of the reset means By using an active matrix type liquid crystal display device having a delay means for controlling a length of time from the hold means to the timing to start the hold operation of the hold means,
The period during which the reset unit performs the reset operation and the period during which the hold unit performs the hold operation do not overlap, and the transfer of the video signal from the sample unit to the hold unit can be performed with high accuracy, and gradation separation display is performed. An active matrix liquid crystal display device with excellent capability can be realized.

Further, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sampling unit that sequentially samples video signals, and a sample unit that samples the video signal. Holding means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, and first counting means for controlling the hold means, the sampling means and By using an active matrix liquid crystal display device to which a control clock having a constant frequency is input as the first counting means,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the hold means A first counting means for controlling the resetting means and a second counting means for controlling the resetting means, and the sampling means, the first counting means, and the second counting means have a constant frequency control. By using an active matrix liquid crystal display device to which a clock is input,
Alternatively, in an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate, the signal line driver circuit includes at least a sample unit that sequentially samples video signals and a sample unit that samples the video signal. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means or the buffer means, and the reset means A delay means for controlling a time length from a timing at which the reset operation of the hold means to a timing at which the hold operation of the hold means is started, a first counting means for controlling the hold means, and a second for controlling the reset means. Counting means and a third means for controlling the delay means An active matrix type liquid crystal display device to which a control clock having a constant frequency is input is used for the sample means, the first counting means, the second counting means, and the third counting means. By
The scale of the circuit that generates the control clock can be reduced, and a highly accurate clock can be obtained. Further, power consumption of the active matrix liquid crystal display device can be reduced by reducing the circuit scale.

1 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a first embodiment of the present invention. The figure explaining the structure of the conventional TFT-LCD panel. The figure explaining the structure of the conventional TFT-LCD module. FIG. 6 illustrates a conventional signal line driver circuit. FIG. 6 illustrates a circuit configuration of a shift register. FIG. 4 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a first embodiment of the present invention. FIG. 4 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a first embodiment of the present invention. 8 is a timing chart illustrating an example of a method for driving the signal line driver circuit illustrated in FIG. 7. FIG. 4 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a first embodiment of the present invention. 10 is a timing chart illustrating an example of a method for driving the signal line driver circuit illustrated in FIG. 9. FIG. 6 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a second embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a second embodiment of the present invention. 14 is a timing chart illustrating an example of a method for driving the signal line driver circuit illustrated in FIG. 13. FIG. 6 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a second embodiment of the present invention. FIG. 15 is a timing chart illustrating an example of a method for driving the signal line driver circuit illustrated in FIG. 14. FIG. FIG. 10 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a third embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a specific circuit configuration of a signal line driver circuit of an active matrix liquid crystal display device using a third embodiment of the present invention. 18 is a timing chart illustrating an example of a method for driving the signal line driver circuit illustrated in FIG. 17. FIG. 10 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a fourth embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a fourth embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a signal line driver circuit of an active matrix liquid crystal display device using a fourth embodiment of the present invention.

Explanation of symbols

CLK ... Control clock XIN ... Selection signal VIDEO ... Video signal SR ... Shift register LS ... Level shifter SW1,1, SW2,1 ... SWm, 1 ... Sample switch group SW1 , 2, SW2, 2... SWm, 2 ... Hold switch group SW1,3, SW2,3 ... SWm, 3 ... Output switch group SW1,4, SW2,4 ... SWm, 4 ... 1st reset switch group SW1,5, SW2,5 ... SWm, 5 ... 2nd reset switch group Bit1, Bit2 ... Bitm ... Bit output RS ... Reset signal lines B1, B2 ... Bm ... Analog buffers C1,1, C2,1 ... Cm, 1 ... Sample capacities C1,2, C2,2 ... Cm, 2 ... Hold capacitor 101 ... Output switch control circuit 102 ... Reset switch control circuit 1 03 ... Hold switch control circuit 104, 105 ... Output switch control circuit part 106, 107 ... Signal line drive circuit part 201 ... TFT-LCD panel 202 ... n rows x m columns Pixel matrix 203 ... thin film transistor 204 ... liquid crystal 205 ... holding capacitor 206 ... signal line driving circuit 207 ... scanning line driving circuit S1, S2 ... Sm ... signal lines G1, G2 ... Gn ... Scanning line SRX ... X-side shift register LSX ... X-side level shifter SRY ... Y-side shift register LSY ... Y-side level shifter SH ... Sample-and-hold circuit COM ...・ Opposite voltage XCLK ... X side clock XIN ... X side selection signal VIDEO ... Video signal RST ... Reset Signal ENBL ... Output enable signal YIN ... Y side selection signal YCLK ... Y side clock 301 ... Counter voltage COM generation circuit 302 ... Video signal VIDEO modulation circuit 303 ... X side clock XCLK generation Circuit 304 ... X side selection signal XIN generation circuit 305 ... Output enable signal ENBL generation circuit 307 ... Y side selection signal YIN generation circuit 308 ... Y side clock YCLK generation circuit 309 ... TFT-LCD Unit 310 ... Original video signal 311 ... Reset signal RST generation circuit ECLK ... External clock HSYNC ... Horizontal synchronization signal VSTNC ... Vertical synchronization signal ASW1,1, ASW2,1 ... ASWm, 1 ... Analog switch group ASW1,2, ASW2,2 ... ASWm, 2 ... Analog switch group SW1, RSW2 ... RSWm ... Reset switch group CSPL ... Sample capacitance CHLD ... Hold capacitance 501 ... D-flip flop 502 ... Clocked inverter 503 ... Inverter 504 AND gates CLKa, CLKb, CLKb * ... clock DIN ... selection signal 601 ... terminals 602, 603, 604 ... wiring 605, 607 ... D-flip flop 606 ... resettable D -Flip-flop 608 ... NOR gates P61 to P66 ... points P61 to P66
701, 702 ... Wiring from the bit output 703 ... Wiring from the hold switch control circuit 704 ... Wiring from the reset switch control circuit 705 ... Wiring 706, 707 from the output switch control circuit .. Wiring to signal line 801... Horizontal scanning period 802... Horizontal blanking period 803, 804, 805, 806... Period 901... Terminal 902. Wiring 903 to the second reset switch group ... Wiring to the hold switch group 904 ... Wiring to the output switch group 905, 906 ... N-type thin film transistors 907, 908 ... Clocked inverter 909 ... NOR gates P91 to P99 ... Points P91 to P99
CLK, CLK * ... control clock 121, 122, 123, 124 ... period 111 ... terminal 112 ... delay circuit 211 ... terminal 212, 213, 214 ... wiring 215, 217 ... D-flip flop 216 Resettable D-flip flop 218 NOR gates P21 to P26 Points P21 to P26
320 ... Horizontal scanning period 321 ... Horizontal blanking period 322, 323, 324, 325 ... Period 401 ... Terminals 402, 403, 404 ... Wiring 405, 406 ... Clocked inverter 407, 408 ... N-type thin film transistor 409 ... Inverters P41 to P49 ... Points P41 to P49
510 ... Horizontal scanning period 511 ... Horizontal blanking period 512, 513, 515, 516 ... Period 514 ... Delay periods 610, 611, 612 ... Count circuit 711 ... Terminals 712, 713 , 714 ... Wiring 715, 717 ... D-flip flop 716 ... Resettable D-flip flop 718 ... NOR gates P71 to P77 ... Points P71 to P77
810 ... Horizontal scanning period 811 ... Horizontal blanking period 812, 813, 815, 816 ... Period 814 ... Delay period 920 ... Part 921 ... Reset switch control circuit 922 ... Hold switch control circuit 925, 926 ... Count circuit 927 ... Delay circuit

Claims (7)

In an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driver circuit are formed on the same substrate,
The signal line driver circuit includes: a shift register; a plurality of sample switches that sample signals according to latch signals sequentially generated by the shift register; and a plurality of hold capacitors that hold signals sampled by the plurality of sample switches. A first control circuit that generates a first control signal that resets the plurality of hold capacitors; and a second control signal that generates a second control signal that controls transfer of signals from the plurality of sample switches to the plurality of hold capacitors. A control circuit,
The first control circuit receives and transfers the signal transferred in the shift register to generate the first control signal,
The active matrix liquid crystal display device, wherein the second control circuit receives and transfers the signal transferred in the first control circuit to generate the second control signal. The signal line driving circuit further includes a plurality of buffers for outputting the signal held by the hold capacitor to each of the plurality of signal lines,
2. The active matrix liquid crystal display device according to claim 1, wherein the first control signal resets the plurality of hold capacitors and resets output terminals of the plurality of buffers. 3.   The active matrix liquid crystal display device according to claim 1, wherein the first and second control circuits have the same circuit configuration as the shift register. The first and second control circuits include a count circuit that counts clock signals supplied to the shift register,
4. The active matrix liquid crystal display device according to claim 1, wherein a signal transferred in the shift register is input and transferred according to a timing controlled by the count circuit. 5. . In a driving method of an active matrix liquid crystal display device in which a pixel matrix and at least a signal line driving circuit are formed on the same substrate,
A latch signal is sequentially generated by a shift register, and a signal is sequentially sampled by a plurality of sample switches according to the latch signal,
Input and transfer the signal transferred in the shift register, and generate a first control signal for resetting a plurality of hold capacitors;
After generating the first control signal, inputting and transferring the signal transferred in the shift register, and generating a second control signal for holding the signals sampled by the plurality of sample switches by a plurality of hold capacitors; A driving method for an active matrix liquid crystal display device. The signal line driving circuit further includes a plurality of buffers for outputting the signal held by the hold capacitor to each of the plurality of signal lines,
6. The driving method for an active matrix liquid crystal display device according to claim 5, wherein the first control signal resets the plurality of hold capacitors and resets output terminals of the plurality of buffers. The time th required for the plurality of hold capacitors to hold the signals sampled by the plurality of sample switches and the time tr required for resetting the plurality of hold capacitors have a relationship of th> tr. 6. A method for driving an active matrix type liquid crystal display device according to claim 5, wherein:

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