JP3841683B2 - Information playback device - Google Patents

Description

Technical field
The present invention relates to an information reproducing apparatus or a disk drive apparatus that reproduces information from a signal having alternating polarity of a rising polarity pulse and a falling polarity pulse, and is applied to, for example, reproduction of run-length encoded channel data in a magnetic storage device. Related to effective technology.
Background art
In a magnetic storage device such as a hard disk drive device, user data is encoded into channel data as run-length encoded data, and recorded as magnetic transitions on the disk. In recording magnetic transitions, the run length is defined using a fixed frequency clock signal period. A read signal of recorded information by the magnetic head is a signal having alternating characteristics of rising polarity pulses and falling polarity pulses having a plurality of types of pulse intervals defined in advance. In order to reproduce the channel data from the read signal, the clock signal is reproduced based on the read signal, and the channel data is reproduced based on the relationship between the phase of the reproduced clock signal and the pulse width of the read signal. .
A PLL circuit can be used to reproduce the clock signal. That is, a read signal from the magnetic head is supplied to the PLL circuit to reproduce the clock signal. For example, in a magnetic storage device, a PLL pull-in pattern such as 101010... Is written at the top in several bytes for each sector (512-byte read data block unit), so that the phase of the PLL circuit can be easily pulled in. Has been.
However, there is a limit to the noise resistance of the PLL circuit, and the PLL circuit is unlocked in a noisy signal state. The loss of lock of the PLL circuit is called a burst error, and the read channel outputs all incorrect data from the point of the burst error. Normally, in a hard disk device, data output from a read channel can be corrected by an ECC (Error Check and Correct) circuit. However, this can only correct a few bytes of error in one sector, resulting in a burst error. There is no function to correct data. For this reason, the sector in which the burst error has occurred must be read again by retrying, which degrades the data access performance in the hard disk device.
In addition, if information recording density and track density of a recording disk in an information reproducing apparatus such as a hard disk device are increased and considering high-speed access thereof, it is considered that a PLL circuit that operates from 500 MHz to 1 GHz or more is necessary in the future. It is expected that it will be difficult to design such a high-speed PLL circuit.
If the noise resistance of the PLL circuit is low, a Viterbi decoder of PRML (Partial Response Maximum Likelihood) format that determines the logical value 1/0 of the sampling data in synchronization with the clock signal at the subsequent stage is an S / N (Signal / Noise) decoder. Even if high performance is realized in which data can be correctly judged even under bad conditions, the possibility of occurrence of a burst error due to data input accompanied by large noise cannot be avoided.
Japanese Patent Application Laid-Open No. 9-120463 discloses a data recovery circuit with improved resistance to jitter. In this method, peak detection is performed on a signal, an interval between peaks is measured, a 1, 0 pattern corresponding to the measured value is obtained from a lookup table, and run-length encoded data is reproduced. . Although this technique does not use a PLL circuit, peak detection must be performed on a signal to be reproduced. In this peak detection, if the signal frequency is high, the noise is likely to be regarded as a peak. In this respect, it is considered that there is a limit to noise resistance.
An object of the present invention is to provide an information reproducing apparatus capable of detecting a pulse interval of an input signal without using a recovered clock signal by a PLL circuit and without performing peak detection for the input signal.
Another object of the present invention is to improve noise resistance of an information reproducing apparatus that reproduces information from a signal having alternating polarity of a rising polarity pulse and a falling polarity pulse.
Still another object of the present invention is to provide an information reproducing apparatus capable of accurately reproducing channel data that has been run-length encoded for a signal having a high data rate.
Another object of the present invention is to provide an information reproducing apparatus in which a burst error hardly occurs.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Disclosure of the invention
An information reproducing apparatus or semiconductor device according to the present invention is an apparatus for reproducing channel data of a bit string corresponding to a pulse interval from an information signal having a plurality of types of pulse intervals in which rising polarity pulses and falling polarity pulses are alternated. This information reproducing apparatus has ideal waveform data output means for outputting ideal waveform data for representing an ideal waveform related to the rising polarity pulse and an ideal waveform related to the falling polarity pulse for each pulse interval. The clock signal for sampling of the converting means that samples and quantizes the information signal is a clock signal having a period corresponding to the sampling point pitch of the ideal waveform data, for example. This clock signal may be asynchronous with the information signal, and need not be a clock signal regenerated from the information signal, and does not require a PLL circuit for clock recovery. The pulse interval of the alternating pulse included in the information signal is detected by selecting an ideal waveform closest to the waveform of the information signal. That is, an ideal waveform that approximates the pulse waveform or pulse interval of the information signal based on the difference between the data converted by the conversion means and each ideal waveform data output from the ideal waveform data output means is obtained by the waveform detection means. Determine sequentially. Therefore, it is not necessary to detect the peak of the information signal. The waveform detection means outputs a bit string corresponding to the pulse interval of the ideal waveform determined sequentially. This bit string is cut into channel data of a predetermined number of bits by the channel data output means and output to the subsequent stage.
When determining the presence / absence of a pulse for each unit time or for each bit with respect to the pulse, it is necessary to increase the accuracy of the sampling point by the PLL circuit. Since the pulse interval of the alternating pulse included in the information signal is detected by selecting the waveform, it is not essential to increase the accuracy of the sampling point. For this reason, it is not necessary to use a PLL circuit for reproducing the synchronous clock from the information signal.
A clock signal asynchronous with the information signal causes an error in terms of frequency and phase with respect to a recovered clock signal reproduced from the information signal, and it is desirable to configure the waveform detection means so as to compensate for the influence of the error. .
First, the waveform detection means can be constituted by a data input buffer, a calculation means, a correlation data buffer, and a tracking control means. The data input buffer includes in series latch circuits having two or more stages larger than the maximum number of pulse intervals. Each latch circuit performs a latch operation in synchronization with a clock signal, and the data converted by the conversion means in the first stage. Enter. If the number of stages of the latch circuit is two or more larger than the maximum number of pulse intervals, the sampling data continuous over the range in which the pulse polarity can be determined for the input data of the maximum pulse interval is stored in the data input buffer. A plurality of latch circuits can be latched and output in parallel. The arithmetic means is configured to output each ideal waveform for the pulse waveform of the information signal based on a difference between each ideal waveform data output from the ideal waveform data output means and latch data output in parallel from the plurality of latch circuits. Correlation data indicating the approximate state is calculated in synchronization with the clock signal. The correlation data buffer is capable of sequentially shifting and holding the correlation data calculated by the calculation means by the number of clock signal cycles corresponding to at least the maximum value of the pulse interval. For example, if the maximum value of the pulse interval is m, the correlation data buffer having m correlation data continuous with respect to each ideal waveform has correlation data in the closest state for each pulse interval held by the information signal. Will appear. From this point of view, the tracking control means corresponds to the process of extracting the correlation data indicating the closest state among the correlation data relating to the pulse of one polarity held in the correlation data buffer, and the extracted correlation data. The correlation data buffer is shifted by the pulse interval of the ideal waveform to be processed, and the correlation data indicating the most approximate state among the correlation data related to the pulse of the other polarity is extracted. Follow the correlation data in the closest state. Extraction of correlation data by the tracking control means can be performed within a predetermined range around the time in the correlation data buffer, so even if there is the frequency error between the asynchronous clock signal and the recovered clock signal. It has no substantial effect on the extraction of the most approximate ideal waveform data.
Secondly, the ideal waveform data output means separately outputs data in which the sample points of the ideal waveform data are shifted from each other by a half pitch for each pulse interval of the rising polarity and the falling polarity. Since the maximum phase difference of the asynchronous clock signal with respect to the recovered clock signal is 180 °, if the ideal waveform data is prepared taking this into consideration, the phase difference between the recovered clock signal and the recovered clock signal is set. Even if it occurs, it does not substantially affect the extraction of the most approximate ideal waveform data.
The conversion means is an A / D conversion circuit that converts the information signal into a digital signal in synchronization with a clock signal, or a sample and hold circuit that samples and holds the information signal in synchronization with the clock signal. In the former case, the waveform detecting means may be constituted by a digital circuit. A digital signal processor may be used as the digital circuit. In the latter case, the waveform detecting means may be constituted by an analog circuit.
When the information signal is a read signal from a disk, if it has a frequency synthesizer that generates a synchronization signal of information to be written to the disk, it is preferable to use the one output from the frequency synthesizer as the clock signal. Thereby, the frequency error between the asynchronous clock signal and the recovered clock signal can be easily reduced.
The information reproducing apparatus can be applied not only to an apparatus that reproduces a read signal from a disk, such as a hard disk apparatus, but also to an apparatus for communication control that receives the information signal from a transmission medium.
As one means for reducing the error rate of information reproduction, an ECC circuit that enables error check and correction on the channel data output from the channel data output means may be provided.
Since the conversion means asynchronously samples the information signal, even if the data converted by the conversion means is stored in the buffer memory in a relatively large unit such as one sector, the data will not be wasted later. When the PLL circuit is used, if the PLL circuit is unlocked, the data cannot be used at all afterwards even if the data is stored in the buffer.
If a buffer memory for storing the data converted by the converting means is provided and the data read from the buffer memory is supplied to the waveform detecting means, the processing conditions in the waveform detecting means are changed and the processing is performed a plurality of times. The error correction capability can be improved by performing the above. For example, the ideal waveform data output means has a plurality of types of ideal waveform data determined under different usage conditions, and the type of ideal waveform data to be output is an error that cannot be corrected by the ECC circuit with respect to channel data. Switchable when is detected. At this time, it is not necessary to re-read the information signal from the disk, the memory access to the buffer memory may be performed, and the reprocessing time can be shortened.
In order to cancel the memory access time at that time, it is only necessary to provide a plurality of waveform detection means having different conditions such as ideal waveform data in advance, operate them in parallel, and select an output according to the error situation. That is, a plurality of processing means including at least the ideal waveform data output means, calculation means, data buffer, tracking control means, and channel data output means are provided so as to be able to operate in parallel. Further, a selector that selects the channel data output means included in each of the processing means and selects the output of the selected channel data output means, and the channel data output from the channel data output means selected by the selector If error checking and correction are possible, an ECC circuit is provided. The selector is made switchable when an uncorrectable error for channel data by the ECC circuit is detected.
The ideal waveform output by the ideal waveform data output means included in each of the processing means is different data determined under the assumption of different use conditions relating to, for example, the use atmosphere temperature and pressure.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 illustrates a hard disk device to which the information reproducing apparatus according to the present invention is applied and its read channel.
The hard disk device includes a magnetic disk 1 on which information is recorded, a head 2 that performs writing / reading on the magnetic disk 1, a read / write integrated into a semiconductor integrated circuit that controls signals from the head 2 and signals to the head 2 The semiconductor integrated circuit includes an amplifier 3, a read channel 4 formed as a semiconductor integrated circuit for performing signal processing for writing and reading, and an ECC circuit 5 capable of performing error check and error correction of data reproduced by the read channel 4. A hard disk controller (HDC) 6, work memory 7, drive system control circuit 8, and power transistor circuit (COMBO) 11 that drives the disk motor 9 and the head motor 10 of the head assembly under the control of the drive system control circuit 8. Composed of etc. The hard disk controller 6 is interfaced with a host device (not shown).
At the time of writing to the magnetic disk 1, the user data output from the hard disk controller 6 is encoded into channel data as run-length encoded data by the encoding circuit 13 of the read channel 4, and magnetically passes through the read amplifier 3 and the head 2. Written on the disk 1 as magnetic transitions. When writing a magnetic transition, the run length is defined using a fixed frequency clock signal period, and the clock signal is a synchronization signal of the encoding circuit 13. For example, what is generated as the clock signal 24 by the frequency synthesizer 14 of the read channel 4 is used.
At the time of reading, the read waveform signal read from the disk 1 by the head 2 and amplified by the read / write amplifier 3 is converted into the original data by the read channel 4 and output to the hard disk controller 6. That is, the recording information read signal by the head 2 has alternating characteristics of a rising polarity (hereinafter referred to as positive polarity) pulse and a falling polarity (hereinafter also referred to as negative polarity) pulse having a plurality of predetermined pulse intervals. Is a signal having The read channel 4 reproduces channel data from the read signal. At this time, the read channel 4 does not reproduce the clock signal from the read signal using the PLL circuit. An error occurring in the read channel 4 can be corrected by the ECC circuit 5. The drive system control circuit 8 controls the rotation of the magnetic disk 1 and the position of the head 2.
In addition to the coding circuit 13 and the frequency synthesizer 14, the read channel 4 includes an auto gain controller (AGC) 16, a filter 17, an A / D conversion circuit (ADC) 18, a detection gate circuit 19, a decoder 20, and code decoding. A circuit 21 and a servo circuit 22 are included.
The AGC 16 controls the amplitude of the reproduced waveform signal output from the read / write amplifier 3 to be constant, and the filter 17 narrows the frequency spectrum to the Nyquist frequency, cuts high frequency noise components, and the like. The ADC 18 asynchronously samples and quantizes the output of the filter. The number of quantization bits is 6 bits, for example. Asynchronous here means that a clock signal is not regenerated from a signal input to the ADC 18 using a PLL circuit or the like, and sampling is not performed in synchronization with the regenerated clock signal. The sampling clock signal of the ADC 18 is, for example, the same clock signal 24 as the clock signal used for coding generated by the frequency synthesizer 14.
Since the reproduction waveform signal is an alternating waveform signal of a positive polarity pulse and a negative polarity pulse, the output data 27 of the ADC 18 quantized by the asynchronous sampling becomes a data string whose value increases and decreases for each pulse. The detection gate circuit 19 detects and analyzes the vertical relationship of the data string, and does not perform processing for accurately obtaining the position of the pulse by detecting the peak of each pulse.
The detection gate 19 and the decoder 20 are input to the information signal (here, the ADC 18) based on the difference between the data sampled and quantized by the ADC 18 and the ideal waveform data of the positive polarity pulse and the negative polarity pulse. Realizes a waveform detection means that sequentially determines the ideal waveform that 26 pulse waveforms (or pulse intervals) are closest to and forms a bit string corresponding to the determined ideal waveform pulse interval. To do. That is, the waveform detection means detects the pulse interval of the alternating pulse included in the information signal 26 by selecting an ideal waveform that is closest to the waveform of the information signal 26. The detection gate 19 generates correlation data every cycle in synchronization with the clock signal 24 as a measure for indicating which ideal waveform the pulse waveform or pulse interval of the information signal 26 is closest to. The decoder 20 shifts the correlation data for each ideal waveform for a plurality of cycles of the clock signal 24 and holds it in the correlation data buffer, and extracts the smallest one while tracing the held correlation data for each pulse polarity. Then, a bit string corresponding to the pulse interval of the ideal waveform sequentially extracted is output as channel data (decoder output) 28. The code decoding circuit 21 decodes the channel data 28 supplied from the decoder 20 into a user data format.
FIG. 2 shows a specific example of the detection gate circuit 19. Here, the pulse interval included in the information signal 26 is 1 to 5 in each polarity, and 10 types in total. This is assumed in the following specific examples. The detection gate circuit 19 includes a data input buffer 30 and waveform detection circuits WD1 to WD10.
The data input buffer 30 has two or more stages, for example, eight stages of latches FF1 to FF8 in series larger than the maximum number of pulse intervals (= 5), and each latch FF1 to FF8 is synchronized with the clock signal 24. Then, the latch operation is performed, and the data 27 converted by the ADC 18 is input to the first stage. Although the data is shown as 1 bit in the figure, as described above, the data 27 is 6 bits, and it should be understood that each component has a configuration corresponding to 6-bit parallel processing. Here, the number of stages of the latch circuits FF1 to FF8 is 8 stages, which is 3 larger than the maximum number of pulse intervals (= 5). This corresponds to the fact that the number of data of the ideal waveform data at the pulse interval 5 (the number of sample points with respect to the ideal waveform) is eight. If the number of stages of the latch circuits FF1 to FF8 is two or more larger than the maximum number of pulse intervals (= 5), it continues over the range in which the pulse polarity can be determined for the input data of the maximum pulse interval. This is because sampling data can be latched in a plurality of latch circuits of the data input buffer 30 and output in parallel.
The waveform detection circuits WD1 to WD10 include ideal waveform data buffers DB1a to DB10a and DB1b to DB10b as ideal waveform data output means, and arithmetic circuits EX1 to EX10.
The ideal waveform data buffers DB1a to DB10a and DB1b to DB10b separately hold the ideal waveform data of the positive polarity pulse and the negative polarity pulse every pulse interval and with the sample points of the ideal waveform data shifted from each other by a half pitch. . The sampling point pitch of each ideal waveform data is substantially coincident with the period of the clock signal 24. In other words, the ADC 18 quantizes the information signal 26 in synchronization with the clock signal 24 having a period corresponding to the sampling point pitch of the ideal waveform data.
An example of the ideal waveform data is shown in FIG. 3 and FIG. 4, and (A) to (E) in the figure sequentially show the ideal waveform and its data with pulse intervals of 1 to 5. The points marked with ○ on the ideal waveform discretely indicate the ideal waveform data. The left column of (A) to (E) shows the data of the positive pulse, the right column shows the data of the negative pulse, and the sample pitch is a half pitch in the upper and lower columns of (A) to (E), respectively. It is shifted (180 °). The pits shown in FIGS. 3 and 4 are pulse intervals. Although not particularly limited, each ideal waveform data is data having two sampling points before and after the point included in the range of the pulse interval, and the ideal waveform data relating to the ideal waveform of the pulse interval 1 has four points of data. Then, every time the pulse interval is sequentially increased, one data point is increased.
The reason why data having a sample pitch shifted by a half pitch is prepared as ideal waveform data. Since the phase difference of the asynchronous clock signal 24 with respect to the regenerated clock signal reproducible from the information signal is 180 ° at the maximum, if the above ideal waveform data is prepared in consideration of this, the asynchronous clock signal 24 becomes This is because even if a phase difference occurs with the reproduced clock signal, it does not substantially affect the extraction of the ideal waveform data that is most approximated.
The ideal waveform data buffers DB1a to DB10a and DB1b to DB10b output the corresponding ideal waveform data shown in FIG. 3 and FIG. 4 in parallel in the arrangement of each sampling point. For example, the ideal waveform data buffer DB1a outputs ideal waveform data D1 to D4 in parallel as illustrated in FIGS.
The arithmetic circuits EX1 to EX10 calculate the difference between the ideal waveform data output from the ideal waveform data buffers DB1a to DB10a and DB1b to DB10b and the latch data output in parallel from the latch circuits FF1 to FF8 of the data input buffer 30. Based on this, correlation data S (1) to S (10) indicating the approximate state of each ideal waveform with respect to the pulse waveform of the information signal is calculated. For example, in the arithmetic circuit EX1 whose details are exemplified, on the ideal waveform data buffer DB1a side, there are four subtractors SUBa and subtracters SUBa for calculating the difference between the output and the outputs of the corresponding latch circuits FF1 to FF4, respectively. There are four squarers MULa that square the outputs, and three adders ADDa that sequentially add the outputs of the squarers MULa. Similarly, on the ideal waveform data buffer DB1b side, four subtracters SUBb for calculating the difference between the output and the outputs of the corresponding latch circuits FF1 to FF4, respectively, and four squarers MULb that square the outputs of the subtractor SUBb. And three adders ADDb for sequentially adding the outputs of the squarer MULb. According to this example, the smaller the value of the addition result by the adders ADDa and ADDb, the closer the input is to an ideal waveform. The conversion result by the adder ADDa and the addition result by the adder ADDb are compared by the comparator CMP, the smaller addition result is selected by the selector SEL based on the comparison result, and the selected addition result is the correlation data S ( 1) is output. Although details of the other arithmetic circuits EX2 to EX10 are not particularly shown, inputs from the data input buffer 30 are sequentially increased one by one with respect to the arithmetic circuit EX1, and in accordance therewith, subtraction circuits SUBa and SUBb, and a square unit MULa , MULb and adder circuits ADDa and ADDb are sequentially increased in pairs.
FIG. 5 shows a detailed example of the decoder 20. The decoder 20 includes a correlation data buffer RDB, a minimum path tracking control circuit LPS, and a channel data output circuit SRB.
The correlation data buffer RDB inputs the correlation data S (1) to S (10) calculated by the detection gate 19 to the first stage and sequentially shifts and holds the data while synchronizing with the clock signal 24. It has 10 shift registers configured by ~ ff5. The correlation data buffer RDB sequentially holds the correlation data S (1) to S (10) calculated by the detection gate 19 for five cycles of the clock signal 24 corresponding to the maximum value 5 of the pulse interval. be able to.
The correlation data held in the correlation data buffer RDB is expressed as S (1,1) to S (10,5) as illustrated in FIG. Since the correlation data buffer RDB has five correlation data continuous for five cycles of the clock signal 24 for each ideal waveform, a minimum value is set in the correlation data buffer RDB according to the pulse interval of the information signal at that time. The correlation data to be collected will always appear. In short, since the maximum value of the pulse interval of the information signal is 5, the correlation data S (1, 1) to S (10, 5) for 5 clock cycles always includes data that should be minimized. Is stored in the correlation data buffer RDB.
As shown in FIG. 5, the minimum path tracking control circuit LPS inputs 50 correlation data S (1, 1) to S (10, 5) held in the correlation data buffer RDB in parallel. .
FIG. 7 schematically shows a processing procedure by the minimum path tracking control circuit LPS. The minimum path tracking control circuit LPS extracts the correlation data indicating the smallest value among the correlation data regarding the pulses of one polarity held in the correlation data buffer RDB. For example, the correlation data S (m, n) in FIG. 7 is extracted. Since it can be considered that the ideal waveform corresponding to the extracted correlation data S (m, n) is included in the information signal at that time, the number of pulse intervals (detection pulse intervals) of the ideal waveform corresponding to the correlation data After a minute clock cycle, it is possible to specify the ideal pulse waveform for the next polarity reversal. Accordingly, after the correlation data is shifted in the correlation data buffer RDB by the detection pulse interval of the ideal waveform corresponding to the extracted correlation data S (m, n), The process of extracting the correlation data S (i, j) having the smallest value is performed. The minimum value correlation data is traced by repeating the process of extracting the minimum value correlation data. Since the extraction of the correlation data by the minimum path tracking control circuit LPS is performed within a data range of three clock cycles (3 cyc) that are temporally mixed in the correlation data buffer RDB, between the asynchronous clock signal and the recovered clock signal. Even if there is a frequency error, the extraction of ideal waveform data that is most approximate is not substantially affected.
The minimum path tracking control circuit LPS outputs a bit string corresponding to the pulse interval of the ideal waveform sequentially determined as described above. The bit string is determined in advance according to the pulse interval of the ideal waveform, and is not particularly limited. However, as illustrated in FIG. 3 and FIG. 4, the case of pulse interval 1 is “1”, and the case of pulse interval 2 Is “01”, the pulse interval is “001”, the pulse interval is “0001”, and the pulse interval is “00001”. In short, the number of logical values “0” inserted before the logical value “1” is determined according to the pulse interval.
FIG. 8 shows a specific example of processing by the minimum path tracking control circuit LPS. First, since there is no previous value in the initial state, it is necessary to decide where to start. Therefore, the smallest one of the 5 × 10 state correlation data stored in the correlation data buffer RDB is searched. In the example of FIG. 8, correlation data 1 (S (2, 2) of FIG. 6) is extracted as illustrated in FIG. Since this correlation data 1 is correlation data with a positive pulse interval 2, a corresponding bit string “01” is output, and further waiting for the correlation data to be shifted twice in the right direction (B, C). .
Next, as illustrated in FIG. 8C, 15 pieces of correlation data on the negative polarity side including one column before and after the column of correlation data S (x, 2) shifted by a pulse interval of 2 are included. Select the minimum value from. As described above, in order to allow an error of ± 1 clock, the correlation data of 1 bit before and after the bit is also searched for the minimum data. In the example shown in the figure, correlation data 3 (S (9, 2) in FIG. 6) is extracted. The extracted position becomes the starting point of the next bit. Since the extracted correlation data 3 is the correlation data of the negative pulse interval 4, the corresponding bit string “0001” is output. Further, in order to extract the next correlation data, first, it waits for the correlation data to be shifted four times in the right direction (D, E, F, G).
Next, as illustrated in FIG. 8 (G), 15 pieces of correlation data on the positive polarity side including one column before and after the column of correlation data S (x, 2) shifted by the pulse interval 4 are used. Select the minimum value from. In the example shown in the figure, correlation data 2 (S (1, 2) in FIG. 6). Since this correlation data 2 is correlation data with a positive pulse interval 1, a corresponding bit string “1” is output, and it is waited for the correlation data to be shifted once in the right direction (H).
Next, as illustrated in FIG. 8H, 15 pieces of correlation data on the negative polarity side including one column before and after the column of correlation data S (x, 2) shifted by a pulse interval of 1 are included. Select the minimum value from. In the example shown in the figure, this is correlation data 3 (S (6, 2) in FIG. 6). Since this correlation data 3 is correlation data with a negative pulse interval 2, a corresponding bit string “01” is output, and further waiting for the correlation data to be shifted twice in the right direction (I, J). .
Then, as illustrated in FIG. 8J, 15 correlation data on the positive polarity side including one column before and after the column of the correlation data S (x, 2) shifted by the pulse interval 2 are obtained. Select the minimum value from the medium. In the example shown in the figure, the correlation data is 2 (S (3, 2) in FIG. 6). Since this correlation data 2 is correlation data with a positive pulse interval 3, a corresponding bit string “001” is output. Hereinafter, although illustration is omitted, the extraction of the minimum correlation data is continued by repeating the same processing as described above.
FIG. 9 shows an operation example of the channel data output circuit SRB. The channel data output circuit SRB is composed of a shift register that sequentially shifts and inputs a bit string output from the minimum path tracking control circuit LPS according to the pulse interval of the ideal waveform, and when the input becomes 8 bits or more. 8 bits are cut out and output as channel data, and the remaining bits are right-justified. According to the example of FIG. 8, the minimum path tracking control circuit LPS sequentially outputs bit strings “01”, “0001”, “1”, “01”, and channel data output circuit SRB that serially inputs these. Cuts out an 8-bit bit string “01000110” and the surplus bit “1” is shifted to the beginning of the channel data to be output next time.
According to the read channel 4 described above, the following operational effects can be obtained.
[1] When reproducing channel data 28 of a bit string corresponding to a pulse interval from an information signal 26 in which a positive pulse and a negative pulse are alternated and having a plurality of types of pulse intervals, the data quantized by the ADC 18 and the ideal waveform are reproduced. Based on the difference from each ideal waveform data output from the data output means, an ideal waveform that most closely approximates the pulse waveform or pulse interval of the information signal is detected. That is, the pulse interval of the alternating pulse included in the information signal is detected by selecting an ideal waveform closest to the waveform of the information signal. Therefore, it is not necessary to detect the peak of the information signal.
Furthermore, when determining the presence / absence of a pulse every unit time or one bit with respect to the pulse, it is necessary to increase the accuracy of the sampling point by the PLL circuit. Since the pulse interval of the alternating pulse included in the information signal 26 is detected by selecting a near ideal waveform, it is not essential to increase the accuracy of the sampling point. For this reason, it is not necessary to use a PLL circuit for regenerating the synchronous clock from the information signal 26.
Since there is no need to use a PLL circuit, it is possible to prevent the possibility of burst errors with respect to an increase in recording density and track density on the magnetic disk and an increase in data transfer rate due to high-speed access.
[2] The data quantized by the ADC 18 is input to a data input buffer having in series two or more latch stages larger than the maximum number of pulse intervals. Since the number of latch stages is two or more larger than the maximum number of pulse intervals, continuous sampling data over the range in which the pulse polarity can be determined for the input data of the maximum pulse interval is stored in the data input buffer. A plurality of latch circuits can be latched and output in parallel.
[3] The correlation data buffer RDB can sequentially hold and hold the correlation data detected by the waveform detection circuits WD1 to WD10 by at least the number of clock signal cycles corresponding to the maximum value of the pulse interval. If the maximum value of the pulse interval is 5, the correlation data in the closest state is stored in the correlation data buffer RDB having five correlation data continuous for each ideal waveform for each pulse interval held by the information signal. Therefore, the correlation data extraction process by the minimum path tracking control circuit LPS that inputs all the correlation data held in the correlation data buffer RDB in parallel is a predetermined time that is before and after the RDB in the correlation data buffer. Can be done within range. Therefore, even if there is the frequency error between the asynchronous clock signal and the recovered clock signal, the extraction of the ideal waveform data that is most approximate is not affected.
[4] Since the ideal waveform data buffers DB1a to DB10b separately output data in which the sample points of the ideal waveform data are shifted from each other by a half pitch at every positive and negative pulse intervals, they are asynchronous with respect to the reproduced clock signal. In consideration of the fact that the phase difference of the clock signal is 180 ° at the maximum, even if the asynchronous clock signal has a phase difference with the reproduced clock signal, it has a substantial effect on the extraction of the most approximate ideal waveform data. Not give.
[5] According to the above [3] to [4], the clock signal 24 asynchronous with the information signal 26 causes an error in terms of frequency and phase with the reproduction clock signal reproducible from the information signal 26. The influence can be compensated, and relatively high accuracy can be realized in the reproduction of channel data.
FIG. 10 shows an example in which the reproduction circuit portion of the channel data is mainly composed of an analog circuit. Instead of the ADC 18, a sample / hold circuit 18A that samples and holds the information signal 26 in synchronization with the clock signal 24 is employed. At the subsequent stage, an analog detection gate 19A and an analog decoder 20A configured by analog circuits are arranged. The analog detection gate 19A and the analog decoder 20A reproduce the channel data by the same algorithm as the detection gate 19 and the decoder 20. This example is an example that makes it possible to reduce power consumption when the power consumption of the ADC 18 is particularly high.
FIG. 11 shows an example in which the channel data reproduction circuit portion is configured to be capable of software processing. That is, a detection gate function 19B and a decoder function 20B based on the same processing algorithm as the detection gate 19 and decoder 20 are realized by a digital signal processor (DSP) 40 that executes a digital signal processing program. Although not shown in particular, the function of the code decoding circuit 21 is also realized by the DSP 40.
At this time, a buffer memory 41 for storing the data 27 converted by the ADC 18 is provided, and the data read from the buffer memory 41 is supplied to the DSP 40. According to this, the error correction capability using the ECC circuit 5 can be improved by performing the reproduction processing a plurality of times while changing the processing conditions included in the detection gate function 19B. For example, the ideal waveform data buffer is provided with a plurality of types of ideal waveform data determined under different usage conditions, and the ideal waveform data that is output when an uncorrectable error with respect to channel data is detected by the ECC circuit. The type of can be switched. Switching may be performed by software processing. At this time, it is not necessary to re-read the information signal from the magnetic disk 1, the memory access to the buffer memory 41 may be performed, and the reprocessing time can be shortened. The plurality of types of ideal waveforms are different data determined under the assumption of different use conditions regarding, for example, the use atmosphere temperature and pressure.
Efficient use of the buffer memory 41 is ensured by not using a PLL circuit for reproducing channel data. That is, since the information signal 26 is asynchronously sampled, even if the sampled data is stored in the buffer memory 41 in a relatively large unit such as one sector, the data is not wasted later. When the PLL circuit is used, if the PLL circuit is unlocked, the data cannot be used at all afterwards even if the data is stored in the buffer.
The configuration having the buffer memory is not limited to the case where the DSP 40 is used. Of course, the present invention can also be applied to the configuration described so far based on FIG.
FIG. 12 shows still another example having a buffer memory. In the configuration of FIG. 11, in order to cancel the memory access time of the buffer memory 41 at the time of reprocessing, a pair of DSPs 40A and 40B similar to the DSP 40 are provided, they are operated in parallel, and an output is selected according to an error situation. do it. That is, a selector 42 is provided that selects the output of the DSPs 40A and 40B and supplies it to the ECC circuit 5A. The selector 42 is switched to a selected state when an uncorrectable error is detected in the channel data by the ECC circuit 5A.
FIG. 13 shows an example in which the configuration for reproducing the channel data is applied to a communication control apparatus that receives the information signal from a transmission medium. A major difference from FIG. 1 is that the input of the reproduction waveform is supplied from the transmission medium 46. The transmission data is supplied to the AGC 16 via the code conversion circuit 44, the transmitter 45, and the transmission medium 46. The clock signal 24 is generated by a frequency synthesizer or reference clock generation circuit 14A. In this case as well, there is no need to generate a reproduction clock signal synchronized with data by the PLL circuit and quantize the transmission signal as in the hard disk device. Other configurations are the same as those in FIG. 1 and the like, and detailed description thereof is omitted.
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.
For example, the type of pulse interval included in the information signal is not limited to the above example and can be changed as appropriate. Accordingly, the type of ideal waveform data, the number of ideal waveform data, and the like can be changed. In addition, the number of latch stages of the data input buffer 30 and the correlation data buffer RDB can be appropriately changed within a range that satisfies the necessary conditions. Further, the calculation for detecting the minimum value of the correlation data is not limited to the square sum of the differences.
Industrial applicability
The present invention can be widely applied to reproduction of run-length encoded channel data in a magnetic storage device such as a hard disk device or a communication control device.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a read channel of a hard disk device to which an information reproducing apparatus according to the present invention is applied.
FIG. 2 is a logic circuit diagram showing a specific example of the detection gate circuit.
FIG. 3 is an explanatory diagram showing an example of ideal waveform data together with FIG.
FIG. 4 is an explanatory diagram showing an example of ideal waveform data together with FIG.
FIG. 5 is a logic circuit diagram showing a specific example of a decoder that receives the output of the detection gate.
FIG. 6 is an explanatory diagram illustrating the expression format of correlation data held in the correlation data buffer.
FIG. 7 is a flowchart schematically showing a processing procedure by the minimum path tracking control circuit.
FIG. 8 is a flowchart showing a specific example of processing by the minimum path tracking control circuit.
FIG. 9 is an explanatory diagram showing an operation example of the channel data output circuit.
FIG. 10 is a block diagram showing an example in which the reproduction circuit portion of channel data is mainly composed of an analog circuit.
FIG. 11 is a block diagram showing an example in which the reproduction circuit portion of the channel data is configured so that software processing is possible.
FIG. 12 is a block diagram showing an example having a buffer memory for storing quantized data.
FIG. 13 is a block diagram showing an example applied to a communication control apparatus that receives an information signal from a transmission medium.

Claims (13)

An information reproducing apparatus for reproducing channel data of a bit string corresponding to a pulse interval from an information signal having a plurality of types of pulse intervals in which rising polarity pulses and falling polarity pulses are alternated,
Ideal waveform data output means for outputting ideal waveform data for representing the ideal waveform related to the rising polarity pulse and the ideal waveform related to the falling polarity pulse for each pulse interval;
Conversion means for sampling or quantizing the information signal in synchronization with a clock signal having a period corresponding to the sampling point pitch of the ideal waveform data;
Waveform detection means for sequentially determining an ideal waveform that approximates the pulse waveform of the information signal based on the difference between the data converted by the conversion means and each ideal waveform data output from the output means;
An information reproducing apparatus comprising: channel data output means for forming a bit string corresponding to a pulse interval of an ideal waveform sequentially determined by the waveform detection means and outputting the bit data as the channel data. The waveform detection means includes
A data input for inputting in a first stage the data converted by the conversion means in the first stage, each latch circuit performing a latch operation in synchronization with a clock signal, having a latch circuit of two or more stages larger than the maximum number of pulse intervals. Puffer,
Correlation data indicating the approximate state of each ideal waveform with respect to the pulse waveform of the information signal based on the difference between each ideal waveform data output from the ideal waveform data output means and the latch data of the plurality of latch circuits. A calculation means for calculating in synchronization with the clock signal;
A correlation data buffer capable of sequentially shifting and holding the correlation data calculated by the calculation means by the number of clock signal cycles corresponding to at least the maximum value of the pulse interval;
Processing for extracting correlation data indicating the closest state among correlation data relating to pulses of one polarity held in the correlation data buffer, and correlation data corresponding to the pulse interval of the ideal waveform corresponding to the extracted correlation data Waiting for the correlation data to be shifted in the buffer, and extracting the correlation data indicating the most approximate state among the correlation data related to the other polarity pulse, and tracing the correlation data in the most approximate state 2. An information reproducing apparatus according to claim 1, further comprising tracking control means. 2. The ideal waveform data output means separately outputs data in which sample points of ideal waveform data are shifted from each other by a half pitch for each pulse interval of rising polarity and falling polarity. Or the information reproduction apparatus of 2. The conversion means is an A / D conversion circuit that converts the information signal into a digital signal in synchronization with a clock signal, or a sample and hold circuit that samples and holds the information signal in synchronization with the clock signal. The information reproducing apparatus according to claim 1 or 2, characterized in that The information signal is a read signal from a disk, and has a frequency synthesizer that generates a synchronization signal of information to be written to the disk, and the clock signal is output from the frequency synthesizer. Item 3. The information reproducing apparatus according to Item 1 or 2. 3. The information reproducing apparatus according to claim 1, wherein the information signal is received from a transmission medium. 3. The information reproducing apparatus according to claim 1, further comprising an ECC circuit that enables error checking and correction on channel data output from the channel data output means. 8. An information reproducing apparatus according to claim 7, further comprising a buffer memory for storing data converted by said converting means, wherein data read from said buffer memory is supplied to said waveform detecting means. . The ideal waveform data output means has a plurality of types of ideal waveform data determined on the assumption of different use conditions, and the type of ideal waveform data to be output detects an uncorrectable error with respect to channel data by an ECC circuit. 9. The information reproducing apparatus according to claim 8, wherein the information reproducing apparatus is capable of being switched when it is set. A plurality of processing means including at least the ideal waveform data output means, calculation means, data buffer, tracking control means, and channel data output means so as to be able to operate in parallel;
A selector for selecting the channel data output means included in each of the processing means and selecting the output of the selected channel data output means;
An ECC circuit is provided to enable error checking and correction for the channel data output from the channel data output means selected by the selector,
3. The information reproducing apparatus according to claim 2, wherein the selector is configured so that a selection state can be switched when an uncorrectable error with respect to channel data by the ECC circuit is detected. 11. The information reproducing apparatus according to claim 10, wherein the ideal waveform output from the ideal waveform data output means included in each of the processing means is different data determined under the assumption of different use conditions. A semiconductor device for reproducing channel data of a bit string corresponding to a pulse interval from an information signal having a plurality of types of pulse intervals in which a rising polarity pulse and a falling polarity pulse are alternated,
Ideal waveform data output that outputs ideal waveform data for representing the ideal waveform related to the rising polarity pulse and the ideal waveform related to the falling polarity pulse for each pulse interval, and the sample point pitch of the ideal waveform data is shifted by a half pitch. Means,
Conversion means for sampling or quantizing the information signal in synchronization with a clock signal having a period corresponding to the sample point pitch;
Waveform detection means for sequentially determining an ideal waveform that approximates the pulse interval of the information signal based on the difference between the data converted by the conversion means and each ideal waveform data output from the output means;
And a channel data output means for forming a bit string corresponding to the pulse interval of the ideal waveform sequentially determined by the waveform detection means and outputting as the channel data. A semiconductor device for reproducing channel data of a bit string corresponding to a pulse interval from an information signal having a plurality of types of pulse intervals in which a rising polarity pulse and a falling polarity pulse are alternated,
Ideal waveform data output means for outputting ideal waveform data for representing the ideal waveform related to the rising polarity pulse and the ideal waveform related to the falling polarity pulse for each pulse interval;
Conversion means for sampling or quantizing the information signal in synchronization with a clock signal;
A data input for inputting in a first stage the data converted by the conversion means in the first stage, each latch circuit performing a latch operation in synchronization with a clock signal, having a latch circuit of two or more stages larger than the maximum number of pulse intervals. A buffer,
Based on the difference between each ideal waveform data output from the output means and the latch data of the plurality of latch circuits, correlation data indicating the approximate state of each ideal waveform with respect to the pulse waveform of the information signal is used as the clock signal. Calculation means for calculating synchronously;
A correlation data buffer capable of sequentially shifting and holding the correlation data calculated by the calculation means by at least the number of clock signal cycles corresponding to the maximum value of the pulse interval;
Processing for extracting correlation data indicating the closest state among correlation data relating to pulses of one polarity held in the correlation data buffer, and correlation data corresponding to the pulse interval of the ideal waveform corresponding to the extracted correlation data Waiting for the correlation data to be shifted in the buffer, and extracting the correlation data indicating the most approximate state among the correlation data related to the other polarity pulse, and tracing the correlation data in the most approximate state Tracking control means,
Channel data output means for converting a bit string corresponding to the pulse interval of the ideal waveform corresponding to the correlation data sequentially extracted by the tracking control means into a predetermined bit format and outputting it as the channel data is formed on the semiconductor chip. An information reproducing apparatus characterized by being a thing.

Images