JP3843791B2 - COMPOUND SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, LIGHT EMITTING DEVICE, LAMP AND TRANSISTOR - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a boron phosphide containing silicon (Si) single crystal (silicon) having a specific plane orientation as a substrate and boron (B) and phosphorus (P) as constituent elements formed on the surface of the substrate. The present invention relates to a compound semiconductor device including a (BP) -based semiconductor layer.
[0002]
[Prior art]
As one type of III-V compound semiconductor, a boron phosphide (BP) III-V compound semiconductor (boron phosphide-based semiconductor) containing boron (B) and phosphorus (P) as constituent elements is known. (Satoshi Teramoto, “Introduction to Semiconductor Devices” (March 30, 1995, published by Baifukan Co., Ltd., first edition, pages 26-28) Boron phosphide (BP) has a Philips ionic bond degree of zero. .006 (Philips, "Semiconductor Bonding Theory" (July 25, 1985, published by Yoshioka Shoten Co., Ltd., 3rd edition, p. 51), a substance consisting almost of covalent bonds. Since it is a (zinc-blend) type cubic crystal, it has a degenerate valence band structure (Toshiaki Ikoma and Hideaki Ikoma, “Introduction to Basic Physical Properties of Compound Semiconductors” (September 10, 1991, Inc.) Culture Original publication), see 14 to 17 pages). Therefore, in the boron phosphide is provided the advantage of easily acquire the conductive layer of the p-type.
[0003]
2. Description of the Related Art Conventionally, various boron phosphide-based compound semiconductor elements in which a silicon (Si) single crystal is used as a substrate and a boron phosphide (BP) -based semiconductor layer is provided thereon are configured. For example, a heterobipolar transistor (HBT) using a p-type boron phosphide layer is known (see J. Electrochem. Soc., 125 (4) (1978), pages 633-637). In addition, there is a solar cell using a boron phosphide layer as a window layer (see J. Electrochem. Soc. Above). Also disclosed is a technology for constructing a blue band or green band light emitting diode (LED) or laser diode (LD) by utilizing boron phosphide and mixed crystals thereof (Japanese Patent No. 1 ▼ 2809690). (2) No. 2,809,691, (3) No. 2,809,692 and (4) US Pat. No. 6,069,021).
[0004]
Monomeric boron phosphide (BP) has a lattice constant of about 4.538 （(see “Introduction to Semiconductor Devices” above, page 28). On the other hand, a silicon (Si) single crystal used as a substrate is the same cubic zinc-blend type crystal and has a lattice constant of about 5.431Å (see “Semiconductor Device Overview” above). ", Page 28). Therefore, when the degree of mismatch (mismatch) of the lattice is expressed by the ratio of the difference of the lattice constant of both crystals (= 0.893Å) to the lattice constant of the silicon single crystal (= 5.431Å), the magnitude is about 16.6%. To reach. In order to prevent peeling of the boron phosphide layer from the Si substrate surface due to this large degree of lattice mismatch, a low-temperature buffer layer made of polycrystalline boron phosphide containing amorphous material grown at a relatively low temperature is formed on Si. Technical means provided on the substrate surface is disclosed (see US Pat. No. 6,069,021).
[0005]
[Problems to be solved by the invention]
In the prior art, the boron phosphide-based semiconductor layer has a surface of {1.0.0. } Or {1.1.1. } A silicon single crystal having a crystal plane is formed as a substrate (see US Pat. No. 6,069,021 above). Further, the boron phosphide-based semiconductor layer was arranged substantially parallel to the substrate surface {1.1.0. } It tends to be mainly composed of crystal planes. For example, boron phosphide (BP) {1.1.0. } The crystal plane spacing of the crystal planes is about 3.209 mm. On the other hand, a conventional single-crystal silicon single crystal {1.0.0. }, {1.1.0. } Or {1.1.1. } The crystal plane spacing of the crystal planes is about 4.541Å, 3.840Å, and about 3.136Å, respectively. Even when other crystal planes of the silicon single crystal are taken into consideration, boron phosphide (BP) {1.1.0. } Although there is no crystal plane having an interval that matches the crystal plane, the {111} crystal plane interval of the silicon single crystal is {1.1.0. } Closest to the crystal plane spacing.
[0006]
The crystal plane forming the surface of the silicon single crystal substrate or the interval between the crystal planes intersecting the surface and the boron phosphide {1.1.0. } Since the distance with the crystal plane does not match, the conventional {1.0.0. }, {1.1.0. } Or {1.1.1. The problem is that the boron phosphide layer formed on the silicon single crystal substrate having the crystal plane as a surface becomes a poor crystal layer containing a large amount of crystal defects such as dislocations or stacking faults. The present invention provides {1.1.1. On the surface of a silicon single crystal as a substrate. } The crystal plane spacing is {1.1.0. } This is based on the consideration that the crystallinity of the boron phosphide semiconductor layer composed of crystal faces has a significant effect. In particular, the boron phosphide-based semiconductor layer {1.1.0. } Crystalline spacing and silicon {1.1.0. } Intersects the crystal plane {1.1.1. } It can be suitably used to obtain a boron phosphide-based semiconductor layer having further excellent crystallinity, which has been made in view of the fact that the distance from the crystal plane is approximate, {1.1.0. } It is an invention relating to a structure of a silicon single crystal substrate having a crystal plane as a surface.
[0007]
[Means for Solving the Problems]
The present invention is intended to solve the above-described problems of the prior art by specifying the crystal plane orientation of the surface of the silicon single crystal substrate.
That is, the present invention
(1) A boron phosphide (BP) -based semiconductor layer containing boron (B) and phosphorus (P) as constituent elements provided on the surface of a substrate made of silicon (Si) single crystal (silicon) is provided. In the compound semiconductor device, [1.0.0. ] Tilted at an angle of 9 degrees (°) or more and 15 degrees (°) or less in the crystal orientation {1.1.0. } A compound semiconductor device characterized in that a silicon single crystal having a crystal plane as a surface is used as a substrate.
(2) [1.0.0. ] Tilted at an angle of 11 degrees (°) or more and 13 degrees (°) or less in the crystal orientation {1.1.0. The compound semiconductor device according to (1), wherein a silicon single crystal having a crystal plane as a surface is used as a substrate.
(3) [1.0.0. ] Tilted in the crystal orientation in the range of 12.2 ± 0.5 degrees (°) {1.1.0. The compound semiconductor device according to (1), wherein a silicon single crystal having a crystal plane as a surface is used as a substrate.
It is.
[0008]
The present invention also provides
(4) [1.0.0. ] Tilted at an angle of 9 degrees (°) or more and 15 degrees (°) or less in the crystal orientation {1.1.0. } A silicon single crystal having a crystal plane as a surface is used as a substrate, and a boron phosphide (BP) based semiconductor layer containing boron (B) and phosphorus (P) as constituent elements is provided on the surface of the substrate. A method for producing a compound semiconductor device.
(5) [1.0.0. ] Tilted at an angle of 11 degrees (°) or more and 13 degrees (°) or less in the crystal orientation {1.1.0. The method for producing a compound semiconductor element according to (4) above, wherein a silicon single crystal having a crystal plane as a surface is used as a substrate.
(6) [1.0.0. ] Tilted in the crystal orientation in the range of 12.2 ± 0.5 degrees (°) {1.1.0. The method for producing a compound semiconductor element according to (4) above, wherein a silicon single crystal having a crystal plane as a surface is used as a substrate.
It is.
[0009]
The present invention also provides
(7) A light emitting device comprising the compound semiconductor device according to any one of (1) to (3) above.
(8) A lamp using the light-emitting element according to (7) above (9) A transistor comprising the compound semiconductor element according to any one of (1) to (3) above.
It is.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In order to explain the content of the present invention, the surface 2 is not accurately tilted in any crystal orientation {1.1.0. } A cross-sectional schematic diagram of a silicon single crystal 1 having a crystal plane ({1.1.0} -Si) 3a is illustrated in FIG. In the cubic zinc blende type, {1.1.0. } Perpendicular to the crystal plane {1.1.1. } There is a crystal plane. Therefore, in the silicon single crystal 1, the surface 2 is formed {1.1.0. } The crystal plane 3a is orthogonal {1.1.1. } There is a crystal plane 3b. Further, the crystal plane is expressed by Miller index {h. k. l. } (H, k, l are all positive integers), in a silicon single crystal, {h. k. l. } The distance between crystal planes (= d ₀ : unit Å) is obtained by the following equation (1).
d ₀ (Å) = 5.431 / (h ² + k ² + l ² ) ^1/2 (formula (1))
Therefore, {1.1.1. } The spacing between crystal planes is about 3.136 mm, for example, {1.1.0. Of boron phosphide (BP). } The difference in distance from the crystal plane (= 3.209 mm) is about 0.073 mm. That is, {1.1.1. } The ratio (= 0.073 間隔 /3.136Å) of the difference in the crystal plane spacing (= 0.073Å) to the crystal face reaches about 2.3%.
[0011]
On the other hand, [1.0.0. ] Inclined in the crystal direction at an angle of θ degrees (°) {1.1.0. } In the surface 2 composed of crystal faces, {1.1.1. } The distance between the crystal planes 3b (= d: unit Å) and {1.1.1. } The relationship between the crystal plane spacing (= d ₀ : Å) of the crystal plane is schematically shown in FIG. [1.0.0. ] Tilted in the crystal direction {1.1.0. } On the crystal surface, {1.1.1. } The distance between crystal planes (= d) is extended from d ₀ (≈3.136 cm). [1.0.0. ] Θ ° (0 ° <θ <90 °) in the crystal direction {1.1.0. } Intersects the crystal surface 2 {1.1.1. } The distance (= d) between the crystal planes 3b is given by the following equation (2).
d (Å) = d _{0 /} cos θ = 3.136 / cos θ (Formula (2))
As θ is increased, d is expanded.
[0012]
According to the above equation (2), if θ = 9 ° (cos (9 °) = 0.9877), d = 3.175%, for example, boron nitride phosphide mixed crystal (BN _0.05 P _0.95 ) {1.1.0. } It matches the crystal plane spacing of crystal planes. If θ = 15 ° (cos (15 °) = 0.9659), d = 3.247 Å, for example, B _0.96 In _0.04 P {1.1.0. } At a distance that matches the crystal plane spacing, {1.1.0. } Intersects the crystal surface 3a {1.1.1. } With crystal face 3b {1.1.0. } The crystal plane 3a can be obtained. Therefore, as the first embodiment of the present invention, <0.1. > Zinc (Zn) -doped boron phosphide / indium mixed crystal on a boron (B) -doped p-type Si single crystal substrate with a crystal plane inclined at 15 ° in the crystal orientation (1.1.0.) ( _1.1.0.B ) through a low-temperature buffer layer made of B _0.95 In _0.04 P). } A compound semiconductor element composed of a laminated structure including a magnesium (Mg) -doped p-type B _0.96 In _0.04 P layer composed of a crystal plane is _exemplified .
[0013]
Further, if θ = 11 ° (cos (11 °) = 0.9816), d = 3.195Å from the above equation (2), and, for example, a boron nitride arsenide mixed crystal (BN _0.22 As _0.78 ) { 1.1.0. } It matches the crystal plane spacing of crystal planes. If θ = 13 ° (cos (13 °) = 0.743), d = 3.218 、, for example, {1.1.0. } Si- {1.1.0. With a distance substantially coincident with the crystal plane spacing (= 3.209 mm). } Si- {1.1.1. Intersecting the crystal surface 3a. } Si- {1.1.0. With crystal face 3b. } The crystal plane 3a can be obtained. Therefore, as a second embodiment of the present invention, an antimony (Sb) -doped n-type Si single crystal having a (−1.1.0) crystal plane inclined by 11 ° in the <−1.0.0> crystal orientation is the surface. {1.1.0. Through a low-temperature buffer layer made of silicon (Si) -doped boron phosphide (BP) on a crystal substrate. } An example of forming a compound semiconductor element from a laminated structure including silicon (Si) -doped n-type BN _0.22 As _0.78 layers composed of crystal planes is given.
[0014]
If θ is 12.2 ° (cos (12.2 °) = 0.9774), d = 3.209２０ from the above formula (2), and the monomer boron phosphide (BP) {1.1.0. } It matches the crystal plane spacing of crystal planes. If θ is stored within the range of 12.2 ° ± 0.5 °, d falls within the range of 3.203 to 3.215 °, and accordingly, {1.1.0. } The difference between the distance between crystal planes (= 3,209 と) and d of BP {1.1.0. } The ratio to the crystal plane spacing (so-called lattice mismatch) can be as low as about 0.18%. This small degree of lattice mismatch is comparable to the small degree of lattice mismatch (≈0.13%) between gallium arsenide (GaAs) and aluminum arsenide (AlAs). Therefore, θ is set to 12.2 ± 0.5 ° {1.1.0. } On the Si single crystal substrate having the crystal plane as the surface, it is rich in crystallinity {1.1.0. } A boron phosphide layer having a crystal plane can be formed.
[0015]
As a third embodiment of the present invention, <1.0.0. > On an undoped p-type Si single crystal substrate whose surface is a (1.-1.0) crystal plane inclined by 12 ° in the crystal orientation, via a low-temperature buffer layer made of undoped boron phosphide (BP), { An example of forming a compound semiconductor element from a laminated structure including an oxygen (O) -doped high-resistance BP layer having a 110} crystal plane is given.
[0016]
[Action]
[1.0.0. ] Tilted in the crystal orientation {1.1.0. } A silicon (Si) single crystal substrate having a crystal plane as a surface depends on the angle of inclination, and {1.1.0. } Intersects the crystal plane {1.1.1. } Since the spacing between crystal planes can be changed, {1.1.0. } At intervals matching the crystal plane, {1.1.1. } Crossed the crystal lattice {1.1.0. } A Si single crystal substrate having a crystal plane as a surface can be provided.
[0017]
【Example】
(First embodiment)
<-1.0.0> In the case where a light-emitting element is formed using a silicon (Si) single crystal having a (-1.1.0) crystal plane inclined at 15.0 ° as an angle in the crystal direction as a substrate The present invention will be specifically described with reference to FIG. FIG. 3 shows a schematic sectional view of a light emitting diode (LED) 1A according to the first embodiment.
[0018]
A laminated structure 1B for constituting the LED 1A is formed on a silicon single crystal (silicon) substrate 101 having a p-type (−1.1.0.) Surface doped with boron, according to the following items (1) to (4). The functional layers described below were sequentially deposited. The surface of the substrate 101 is <-1.0.0. > Because the crystal plane was inclined by 15.0 ° in the direction (−1.1.0.), It intersects at the surface {1.1.1. } The distance (= d) between crystal planes (d ₀ = 3.136 Å) was 3.246 Å.
[0019]
(1) Polycrystalline mainly composed of amorphous material grown at 350 ° C. by atmospheric pressure MOCVD method using triethylboron ((C ₂ H ₅ ) ₃ B) / phosphine (PH ₃ ) / hydrogen (H ₂ ) system Low temperature buffer layer 102 made of zinc (Zn) doped boron phosphide (BP)
(2) Beryllium (Be) doped p-type grown at 850 ° C. using (C ₂ H ₅ ) ₃ B / trimethylindium ((CH ₃ ) ₃ In) / PH ₃ / H ₂ system atmospheric pressure MOCVD means A lower barrier layer 103 made of a boron phosphide / indium mixed crystal (B _0.96 In _0.04 P) layer. Diethyl beryllium ((C ₂ H ₅ ) ₂ Be) was used as a beryllium doping source.
(3) Cubic silicon (Si) -doped n-type Ga _0.83 In grown at 850 ° C. using trimethylgallium ((CH ₃ ) ₃ Ga) / ammonia (NH ₃ ) / H ₂ atmospheric pressure MOCVD means _A light emitting layer 104 (carrier concentration≈4 × 10 ¹⁷ cm ⁻³ , layer thickness≈150 nm) mainly composed of _0.17 N layer (lattice constant = 4.590 Å).
(4) Silicon-doped n-type boron phosphide having a forbidden band width of about 3.1 eV grown at 400 ° C. by a (C ₂ H ₅ ) ₃ B / PH ₃ / H ₂ system atmospheric pressure MOCVD means An upper barrier layer 105 mainly composed of an amorphous material made of (BP).
[0020]
The boron phosphide / indium mixed crystal (B _0.96 In _0.04 P) layer constituting the lower barrier layer 103 is {1.1.0. } A crystal layer composed of crystal planes was obtained. Moreover, the {1.1.0. } {1.1.1. Of Si intersecting at a distance matching the crystal plane spacing (d = 3.246 Å). } Since it is formed on a (−1.1.0.) Si crystal plane having a lattice plane, the boron phosphide / indium mixed crystal (B _0.96 In _0.04 P) layer constituting the lower barrier layer 103 has a cross-section Even when the crystal structure was observed by the TEM technique, no increase in the density of dislocations or stacking faults was observed.
[0021]
In the center of the upper barrier layer 105, an ohmic surface electrode 106 made of a gold / tin (Au / Sn) circular electrode (diameter = 120 μm) was provided. Further, an ohmic back electrode 107 made of aluminum (Al) was provided on substantially the entire back surface of the p-type Si substrate 101 to configure the LED 1A.
[0022]
The configured blue LED 1A exhibited the characteristics described in the following items (a) to (d).
The effect was manifested as improved brightness.
(A) Emission center wavelength: 450 nm
(B) Luminance: 6 millicandela (mcd)
(C) Forward voltage: 3.0 volts (V) (forward current = 20 mA)
(D) Reverse voltage: 6 V (reverse current = 10 μA)
In the first embodiment, [1.0.0. ] 15.0 ° tilted in the crystal orientation {1.1.0. } The crystal plane is the surface {1.1.0. } Since a Si single crystal is used as the substrate 101, {1.1.0. } -B _0.96 In _0.04 P lower barrier layer 103 and Ga _0.83 In _0.17 N light emitting layer 104 lattice-matched thereto, and as a result, light emission excellent in monochromaticity was resulted. The full width at half maximum (so-called FWHM) at the central wavelength of light emission was 18 nm.
[0023]
Furthermore, a lamp was constructed using the blue LED 1A described in the first embodiment. FIG. 4 shows a schematic sectional view of the lamp 10.
[0024]
First, the LED 1 </ b> A was fixed to the central portion of the metallic casing 16 plated with silver (Ag) on the pedestal 15 with a conductive bonding material. From this, [1.0.0. ] Conductive {1.1.0. } The p-type back electrode 14 provided on the back surface of the Si substrate 11 was electrically connected to one terminal 17 attached to the base 15. Next, the n-type surface electrode 13 placed on the amorphous boron phosphide (BP) layer forming the upper barrier layer 12 of the LED 1A was connected to the other terminal 18 attached to the base 15. Next, the LED 1 </ b> A was surrounded by an epoxy resin 19 for sealing a semiconductor element to obtain a lamp 10.
[0025]
The lamp 10 configured using the n-side-up type LED 1A described in the first example exhibited the characteristics described in the following items (a) to (e). From this, it has {1.1.0. } It has been shown that the high-intensity lamp 10 can be constructed from the LED 1A using -Si as the substrate 11.
(A) Emission center wavelength: 450 nm
(B) Light emission half width: 18 nm
(C) Luminance: 0.7 candela (cd)
(D) Forward voltage: 3.0 volts (V) (forward current = 20 mA)
(E) Reverse voltage: 6 V (reverse current = 10 μA)
[0026]
(Second embodiment)
<0.1.0. > Schottky junction field effect transistor (MESFET) with a silicon (Si) single crystal whose surface is a (1.1.0) crystal plane inclined at an angle of 12.2 ° with respect to the crystal direction as a substrate The present invention will be described in detail by taking the case of configuring the above as an example.
[0027]
FIG. 5 shows a schematic cross-sectional view of the MESFET 2A described in the second embodiment. The laminated structure 2B for constituting the MESFET 2A is described in (1) to (4) in the next section on a silicon single crystal (silicon) substrate 101 having an undoped high resistance (1.1.0.) Plane. Functional layers were sequentially deposited and constructed. The surface of the substrate 101 is <0.1. > Since the crystal plane is inclined by 12.2 ° in the direction (1.1.0.), It intersects at the surface {1.1.1. } The distance (= d) between crystal planes (d ₀ = 3.136 Å) was 3.209 Å.
[0028]
(1) (C ₂ H ₅ ) ₃ B / PH ₃ / H ₂ system atmospheric pressure MOCVD method grown at 350 ° C., polycrystalline undoped, high resistance boron phosphide (BP ) Low temperature buffer layer 102
(2) High resistance of oxygen (O) dope grown at 850 ° C. using the (C ₂ H ₅ ) ₃ B / PH ₃ / H ₂ atmospheric pressure MOCVD means (resistivity at room temperature≈10 ⁴ A buffer layer 108 made of a BP layer (lattice constant = 4.538 cm). The oxygen doping source using triethoxy boron _{((C 2 H 5 0)} 3 B).
(3) Cubic undoped n-type Ga _0.94 In _0.06 N layer (lattice constant = 4.538Å) grown at 850 ° C. using (CH ₃ ) ₃ Ga / NH ₃ / H ₂ system atmospheric pressure MOCVD means To the main operation layer 109 (carrier concentration≈2 × 10 ¹⁷ cm ⁻³ , layer thickness≈40 nm).
(4) An undoped n-type BP layer having a forbidden band width of about 3.1 eV grown at 400 ° C. by a (C ₂ H ₅ ) ₃ B / PH ₃ / H ₂ system atmospheric pressure MOCVD means. A contact layer 110 for forming an amorphous ohmic electrode.
[0029]
The boron phosphide (BP) layer constituting the high resistance buffer layer 108 is {1.1.0. } A crystal layer composed of crystal planes was obtained. Further, the spacing of {111} lattice planes of Si on the surface is set to {1.1.0. } The distance between the crystal planes (d = 3.209 mm) was made to coincide {1.1.0. } -Si single crystal was used as the substrate 101, and therefore, the dislocation density inside the high-resistance buffer layer 108 was measured to be less than 1 × 10 ⁵ cm ^{−2 in} the observation of the crystal structure by the cross-sectional TEM technique.
[0030]
Using a known photolithography (photoetching) technique, as shown in FIG. 5, the contact layer 110 was removed only in a region where the gate electrode 111 was to be formed. Next, titanium (Ti), platinum (Pt), and gold (Au) were sequentially vacuum-deposited on the surface of the operation layer 109 exposed in the same region by a general electron beam evaporation means. Thus, a Schottky contact gate electrode 111 having a three-layer structure in which the side in contact with the operation layer 109 is titanium (Ti) and the surface layer is gold (Au) is configured. The electrode length of the gate electrode 111 was about 2.5 μm. An ohmic source electrode 112 and a drain electrode 113 were provided on the surface of the n-type BP contact layer 110 left on both sides facing each other across the gate electrode 111. Both the ohmic electrodes of the source 112 and the drain 113 were made of a multilayer structure of gold / germanium alloy (Au 95 mass% + Ge 5 mass%) and gold (Au) without contacting the operation layer 109.
[0031]
When a source / drain voltage (= V _DS ) of +20 V was applied between the source electrode 112 and the drain electrode 113, the MESFET 2A exhibited the following DC characteristics.
(A) Source-drain current (I _DS ): 2.4 mA
(B) Mutual conductance (g _m ): 20 milliSiemens (mS) / mm
(C) Pinch-off voltage: -10.5V.
In particular, [1.0.0. ] Tilted 12.2 ° to the crystal orientation {1.1.0. } The crystal plane is the surface {1.1.0. } Si single crystal is used as the substrate 101 and has excellent crystallinity and high resistance {1.1.0. } Having constituting the buffer layer 108 from -BP layer, include the effect of preventing leakage of I _DS to the internal buffer layer 108 (leak), MESFET having excellent pinch-off (pinch-off) characteristic has resulted .
[0032]
【The invention's effect】
According to the present invention, the {110} crystal plane inclined by the {110} -boron phosphide-based semiconductor layer {110} crystal plane at an interval so that the {111} crystal plane of Si intersects the surface. Since the {110} -boron phosphide-based semiconductor layer having a {110} crystal plane is formed on the Si single crystal to be used as the substrate, a boron phosphide-based semiconductor layer having excellent crystallinity can be obtained. As a result, a compound semiconductor light emitting device having excellent monochromaticity of light emission can be provided by using a boron phosphide-based semiconductor layer having excellent crystallinity.
[0033]
Further, according to the present invention, a {110} -Si single crystal in which Si {111} crystal planes intersect at the same interval as the {110} crystal plane interval of boron phosphide (BP) is used as a substrate. Since a {110} -boron phosphide-based semiconductor layer having a {110} crystal plane is formed, a field effect transistor can be formed using a boron phosphide layer having excellent crystallinity and high resistance. And a MESFET excellent in pinch-off characteristics can be provided.
[Brief description of the drawings]
FIG. 1 {1.1.0. } The crystal plane is the surface {1.1.0. } It is a cross-sectional schematic diagram of a -Si single crystal.
FIG. 2 [1.0.0. ] Tilted in the crystal direction at an angle of θ degrees {1.1.0. } The crystal plane is the surface {1.1.0. } It is a cross-sectional schematic diagram of a -Si single crystal.
FIG. 3 is a schematic cross-sectional view of an LED described in the first embodiment.
FIG. 4 is a schematic sectional view of a lamp described in the first embodiment.
FIG. 5 is a schematic cross-sectional view of a MESFET described in a second embodiment.
[Explanation of symbols]
1A LED
2A MESFET
1B, 2B Laminated structure 1 {110} -Si single crystal 2 Surface 3a {110} -Si crystal surface 3b {111} -Si crystal surface 10 Lamp 11 Substrate 12 Upper barrier layer 13 Surface electrode 14 Back electrode 15 Base 16 碗Body 17, 18 Terminal 19 Sealing resin 101 Single crystal substrate 102 Low temperature buffer layer 103 Lower barrier layer 104 Light emitting layer 105 Upper barrier layer 106 Front electrode 107 Back electrode 108 Buffer layer 109 Operation layer 110 Contact layer 111 Gate electrode 112 Source electrode 113 Drain electrode

Claims (9)

A compound semiconductor comprising a boron phosphide (BP) -based semiconductor layer containing boron (B) and phosphorus (P) as constituent elements provided on the surface of a substrate made of silicon (Si) single crystal (silicon) [1.0.0. ] Tilted at an angle of 9 degrees (°) or more and 15 degrees (°) or less in the crystal orientation {1.1.0. } A compound semiconductor device characterized in that a silicon single crystal having a crystal plane as a surface is used as a substrate. [1.0.0. ] Tilted at an angle of 11 degrees (°) or more and 13 degrees (°) or less in the crystal orientation {1.1.0. The compound semiconductor element according to claim 1, wherein a silicon single crystal having a crystal plane as a surface is used as a substrate. [1.0.0. ] Tilted in the crystal orientation in the range of 12.2 ± 0.5 degrees (°) {1.1.0. The compound semiconductor element according to claim 1, wherein a silicon single crystal having a crystal plane as a surface is used as a substrate. [1.0.0. ] Tilted at an angle of 9 degrees (°) or more and 15 degrees (°) or less in the crystal orientation {1.1.0. } A silicon single crystal having a crystal plane as a surface is used as a substrate, and a boron phosphide (BP) based semiconductor layer containing boron (B) and phosphorus (P) as constituent elements is provided on the surface of the substrate. A method for producing a compound semiconductor device. [1.0.0. ] Tilted at an angle of 11 degrees (°) or more and 13 degrees (°) or less in the crystal orientation {1.1.0. The method for producing a compound semiconductor device according to claim 4, wherein the substrate is a silicon single crystal having a crystal plane as a surface. [1.0.0. ] Tilted to a crystal orientation in an angle range of 12.2 ± 0.5 degrees (°) {1.1.0. The method for producing a compound semiconductor device according to claim 4, wherein the substrate is a silicon single crystal having a crystal plane as a surface. The light emitting element which consists of a compound semiconductor element of any one of Claims 1 thru | or 3. A lamp using the light emitting device according to claim 7. A transistor comprising the compound semiconductor device according to claim 1.

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