JP3844197B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention can be interrupted by an NMI (Non-Maskable Interrupt) signal that is an unmaskable interrupt signal and an SMI signal (System Management Interrupt) that is an unmaskable interrupt signal having a higher interrupt priority than the NMI signal. The present invention relates to an information processing apparatus including a CPU (Central Processing Unit) that executes various arithmetic processes and programs.
[0002]
[Prior art]
At present, Microsoft's Windows series (hereinafter referred to as Windows-based OS) is widely used in various fields as an OS (Operating System) which is basic software for performing file management, memory management, and the like. This Windows OS is an information processing apparatus equipped with a CPU for executing various arithmetic processes, programs, etc., for example, a personal computer or a POS (Point of Sales) which is a merchandise sales data processing apparatus for executing merchandise sales processing. : Point-of-sale management) It is also used in terminals. As a CPU mounted on such an information processing apparatus, an Intel X86 CPU is widely used.
[0003]
This X86 CPU (hereinafter referred to as CPU) is configured to be interruptible by an NMI signal, an SMI signal, or the like, which is an interrupt signal that cannot be masked. The NMI signal is input to the CPU when a system error, which is a fatal problem that must be dealt with immediately, occurs. The SMI signal has a higher interrupt priority than the NMI signal, and is input to the CPU when the temperature of the heat generating part such as the CPU is abnormal or when the cover that protects each of the built-in parts from the outside is opened. This SMI signal is also used as a signal for instructing a shift to a system management mode for cutting off the power of peripheral devices.
[0004]
Here, such a CPU will be described with reference to FIG. 9, taking a conventional POS terminal as an example. FIG. 9 is a block diagram showing the electrical connection of each unit provided in the conventional POS terminal 100.
[0005]
As shown in FIG. 9, a CPU / memory control unit 103 that controls the CPU and memory is connected to the CPU 101 via a bus line 102. The CPU / memory control unit 103 includes a peripheral bus control unit 104 that controls bus connection with peripheral devices via a bus line 102, and a RAM (Random Access Memory) that stores programs to be processed, various data, and the like. The main memory 105 is connected to a nonvolatile memory 106 that stores a basic I / O system (BIOS) that is a program for performing initialization and various settings of the peripheral device and controlling the peripheral device. The nonvolatile memory 106 is configured by a flash memory that is a rewritable ROM that does not require a backup power source.
[0006]
The peripheral bus control unit 104 is formed with a keyboard 107 as an input device, a display 108 as a display device, a receipt printer 109 for printing a receipt, a drawer 110 for storing money, and a magnetic layer on the surface via a bus line 102. A hard disk drive (hereinafter referred to as HDD) 111 that reads / writes data magnetically from / to the read disk is connected as a peripheral device. The HDD 111 is recorded with a Windows OS, a program for executing sales processing of products, and the like.
[0007]
The CPU 101 receives an NMI signal and an SMI signal from the peripheral bus control unit 104 as interrupt signals. Further, the CPU 101 receives a reset signal / RESET signal (the symbol / attached to the front of the signal name indicates that it is a low active signal, the same shall apply hereinafter) to be restarted from the initial state. Input from the memory control unit 103.
[0008]
Here, when a temperature abnormality occurs in a heat generation part such as a CPU during the sales process of the product by the POS terminal, that is, during the startup of the Windows OS, an SMI signal is input from the peripheral bus control unit 104 to the CPU 101. The CPU 101 interrupts the processing of the CPU 101. At this time, the system control right is transferred from the Windows OS to the BIOS, and the CPU 101 performs predetermined error processing based on the BIOS.
[0009]
If a system error occurs while the Windows OS is running, an NMI signal is input from the peripheral bus control unit 104 to the CPU 101 to interrupt the processing of the CPU 101. At this time, the system control right remains the Windows OS, and the CPU 101 performs predetermined error processing based on the Windows OS.
[0010]
[Problems to be solved by the invention]
As described above, when a system error occurs, predetermined error processing is performed based on the Windows OS, but before the Windows OS spreads, it is based on an OS developed by each company, such as TPOS, FlexOS, etc. Each company had its own error handling. Further, by improving the error processing unique to each company and performing pre-prevention and subsequent measures against failure of the information processing apparatus, the reliability of the information processing apparatus is improved, and added value is pursued.
[0011]
However, in an information processing apparatus that uses a Windows OS, the error processing when a system error occurs is determined by the Windows OS, so that each company's own error processing that has been performed based on the OS developed in-house is executed. Can not do it. Therefore, it is almost impossible to improve the reliability of the information processing apparatus and to pursue added value.
[0012]
Therefore, in order to make this possible, when a system error occurs, it is necessary to transfer the system control right from the Windows OS to a program that executes error processing unique to each company. A BIOS that can be developed in-house is suitable as this program. That is, when a system error occurs, the reliability of the information processing apparatus can be improved and the added value can be pursued by transferring the system control right from the Windows OS to the BIOS.
[0013]
An object of the present invention is to make it possible to execute error processing unique to each company in an information processing apparatus employing a Windows OS, thereby improving the reliability of the information processing apparatus and pursuing added value.
[0014]
[Means for Solving the Problems]
The invention of the information processing device according to claim 1 can be interrupted by an NMI signal that is an unmaskable interrupt signal or an SMI signal that is an unmaskable interrupt signal having a higher interrupt priority than the NMI signal. A CPU that executes arithmetic processing and programs, a memory that stores various programs and data, a CPU / memory control unit that controls the CPU and the memory, a peripheral bus control unit that controls bus connections of peripheral devices, and a system error And a switching circuit that switches an NMI signal input to the CPU to an SMI signal when it occurs.
[0015]
Therefore, by switching the signal that is input to the CPU from the NMI signal to the SMI signal when a system error occurs, the system control right at the time of the system error can be transferred from the Windows OS to the BIOS. By developing this BIOS, even in an information processing apparatus adopting a Windows OS, it becomes possible to perform error prevention unique to each company and perform pre-prevention and subsequent countermeasures against apparatus failure.
[0016]
According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, the peripheral bus control unit outputs the NMI signal, the first SIOGP signal, the second SIOGP signal, and the third SIOGP signal to the switching circuit, and the SMI signal / EXTTSMI signal to output the SMI signal to the peripheral bus control unit based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs. Is generated as an input signal of the peripheral bus control unit, and the CPUNMI signal is generated as an interrupt signal to the CPU based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit.
[0017]
Therefore, when a system error occurs, the switch circuit generates an / EXTSMI signal based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit, and the peripheral bus control unit generates the / EXTSMI signal based on the / EXTSMI signal. By inputting the SMI signal to the CPU, it becomes possible to transfer the system control right when the system error occurs from the Windows OS to the BIOS, and to transfer the system control right from the BIOS without releasing the system error. When the system OS is returned to the system OS, a CPU NMI signal generated by the switching circuit based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit is input to the CPU, thereby causing a system error in the Windows OS. It becomes possible to notify the occurrence of .
[0018]
According to a third aspect of the present invention, in the information processing device according to the first aspect, the peripheral bus control unit outputs the NMI signal, the SMI signal, the first SIOGP signal, the second SIOGP signal, and the third SIOGP signal to the switching circuit. The switching circuit generates a CPU SMI signal as an interrupt signal to the CPU based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs, and the peripheral bus control unit The CPUNMI signal is generated as an interrupt signal to the CPU based on the second SIOGP signal and the third SIOGP signal input from.
[0019]
Therefore, when a system error occurs, a CPU SMI signal is generated by the switching circuit based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit, and this CPU SMI signal is input from the switching circuit to the CPU. When the system error occurs, the system control right can be transferred from the Windows OS to the BIOS or returned to the BIOS, and when the system control right is returned from the BIOS to the Windows OS without being able to cancel the system error, By inputting the CPUNMI signal generated by the switching circuit based on the second SIOGP signal and the third SIOGP signal input from the bus control unit to the CPU, it becomes possible to notify the Windows OS of the occurrence of the system error. .
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The information processing apparatus according to the first embodiment of the present invention will be described. As an example of the information processing apparatus of the present embodiment, a POS terminal that is a merchandise sales data processing apparatus that executes merchandise sales processing will be described with reference to FIGS.
[0021]
FIG. 1 is an external perspective view schematically showing a POS terminal 1 according to the present embodiment. As shown in FIG. 1, the POS terminal 1 is placed on a drawer 2 and controls the opening and closing of the drawer 3 of the drawer 2. The casing 4 of the POS terminal 1 is provided with a keyboard 5 in which various keys are gathered, a mode key 6 for switching a business mode with a key (not shown), and a receipt issuing port 7 for issuing a printed receipt. Further, a display 8a that functions as a display means on the operator side is arranged on the upper right side of the POS terminal 1, and a customer that functions as an auxiliary display means that displays, for example, only the selling price or total amount of goods, for example, is provided in the vicinity of the display 8a. A side display 8b is erected.
[0022]
FIG. 2 is a block diagram showing an electrical connection of each unit provided in the POS terminal 1 of the present embodiment. As shown in FIG. 2, a CPU / memory control unit 11 that controls the CPU and memory is connected to the CPU 9 via a bus line 10. The CPU / memory control unit 11 includes a peripheral bus control unit 12 that controls bus connection with peripheral devices via the bus line 10, and a main memory 13 that is a RAM that stores programs to be processed, various data, and the like. A non-volatile memory 14 is connected to store a BIOS or the like, which is a program for performing initialization and various settings of the peripheral device and controlling the peripheral device.
[0023]
The nonvolatile memory 14 is constituted by a flash memory that is a rewritable ROM that does not require a backup power source. As a result, the BIOS can be rewritten. The BIOS incorporates a program for investigating / recording system errors as SMI module software.
[0024]
The peripheral bus control unit 12 is connected to a switching circuit 15 that switches an NMI signal input to the CPU 9 to an SMI signal when a system error occurs, and further, via the bus line 10, a keyboard 5 that is an input device, A peripheral device is connected to the display 8, which is a display device, a receipt printer 16 that prints on receipts, a drawer 2 that stores money, an HDD 17 that magnetically reads and writes data on a disk having a magnetic layer formed on the surface, and the like. The hard disk stores a merchandise sales processing program for causing the Windows OS and the POS terminal 1 to execute merchandise sales processing and various applications.
[0025]
A reset signal / RESETD signal to be restarted from the initial state is input to the switching circuit 15 from the CPU / memory control unit 11, and further, an NMI signal and a first SIOGP (Super I / O IC's General Pins) signal. The SIOGP10 signal, the SIOGP11 signal that is the second SIOGP signal, and the SIOGP12 signal that is the third SIOGP signal are input from the peripheral bus control unit 12.
[0026]
The peripheral bus control unit 12 receives an / EXTSMI signal (EXTernal System Management Interrupt) from the switching circuit 15 based on the NMI signal and the SIOGP10 signal.
[0027]
The CPU 9 receives the SMI signal as an interrupt signal from the peripheral bus control unit 12 based on the / EXTSMI signal. The CPU 9 receives a CPU NMI (Central Processing Unit Non-Maskable Interrupt) signal from the switching circuit 15 based on the SIOGP11 signal and the SIOGP12 signal. Here, the CPUNMI signal is an interrupt signal that cannot be masked, like the NMI signal. Further, a reset signal / RESET signal is input to the CPU 9 from the CPU / memory control unit 11.
[0028]
FIG. 3 is a schematic circuit diagram showing the switching circuit 15 built in the POS terminal 1 of the present embodiment. As shown in FIG. 3, the switching circuit 15 includes two flip-flops 18 (18a, 18b), three AND gates 19 (19a, 19b, 19c), and three tristate buffers 20 (20a, 20b, 20c) It is composed of two buffers 21 (21a, 12b).
[0029]
First, a circuit that generates the / EXTSMI signal based on the NMI signal and the SIOGP10 signal will be described.
[0030]
In the flip-flop 18a, the voltage V is applied to the PR terminal and the D terminal. _CC (3.3V) is input, the PR terminal and the D terminal are fixed to a high level (hereinafter referred to as H level), the NMI signal is input to the CK terminal, and the output signal from the AND gate 19a is input to the CLR terminal. Entered. Based on these signals, an output signal is output from the / Q terminal of the flip-flop 18a through the buffer 21a as the / EXTSMI signal.
[0031]
The AND gate 19a receives the SIOGP10 signal and the output signal from the AND gate 19b. In the AND gate 19b, the voltage V is applied to one input terminal. _CC Is fixed at the H level, and the / RESETD signal is input to the other input terminal.
[0032]
Here, the NMI signal is input to the tri-state buffer 20a, and the output signal from the AND gate 19b to which the / RESETD signal is input is input as a state selection signal. That is, the tri-state buffer 20a changes to a disconnected state or a conductive state based on the state of the H level and the Low level (hereinafter referred to as L level) in the output signal from the AND gate 19b.
[0033]
As a result, when the / RESETD signal is at the H level, the output signal from the AND gate 19b becomes the H level, the tri-state buffer 20a is disconnected, and the CPU NMI even when the NMI signal becomes the H level. The signal is configured not to become H level. When the / RESETD signal is at L level, that is, during the initial setting operation of the CPU 9, the output signal from the AND gate 19b is at L level, and the tri-state buffer 20a becomes conductive. Thus, when the NMI signal becomes H level, the CPU NMI signal becomes H level, so that the operation check at the initial setting is executed without any problem.
[0034]
Next, a circuit that generates a CPUNMI signal based on the SIOGP12 signal and the SIOGP13 signal will be described.
[0035]
In the flip-flop 18b, the voltage V is applied to the CK terminal and the D terminal. _CC , The CK terminal and the D terminal are fixed to the H level, the SIOGP11 signal is input to the PR terminal, and the output signal from the AND gate 19c is input to the CLR terminal. Based on these signals, signals are output from the Q terminal of the flip-flop 18b.
[0036]
An output signal from the AND gate 19b to which the / RESETD signal is input and the SIOGP12 signal are input to the AND gate 19c.
[0037]
Here, the output signal from the Q terminal of the flip-flop 18b is input to the tristate buffer 20b, and the output signal from the tristate buffer 20c is input as a state selection signal. The tristate buffer 20c has a voltage V _CC Is input (fixed to the H level), and the / RESETD signal is input as the state selection signal.
[0038]
The tri-state buffer 20c changes to a disconnected state or a conductive state based on the state of the H level and the L level in the / RESETD signal. Similarly, the tri-state buffer 20b changes to a disconnected state or a conductive state based on the H level and L level states in the output signal from the tri-state buffer 20c.
[0039]
When the / RESETD signal becomes H level, the tri-state buffer 20c is disconnected, and the output signal of the tri-state buffer 20c becomes L level. As a result, the tri-state buffer 20b becomes conductive, and an output signal from the Q terminal of the flip-flop 18b is output as a CPUNMI signal via the buffer 21b.
[0040]
Conversely, when the / RESETD signal becomes L level, the tristate buffer 20c becomes conductive, and the output signal of the tristate buffer 20c becomes H level. As a result, the tri-state buffer 20b is disconnected, and the output signal from the Q terminal of the flip-flop 18b is cut off.
[0041]
In such a configuration, when the power of the POS terminal 1 is turned on and the power supply voltage reaches a predetermined voltage, the CPU 9 becomes operable by the / RESET signal input from the CPU / memory control unit 11. Initial setting operation is started. First, the CPU 9 reads the BIOS recorded in the ROM 14 and executes initialization and various settings of the peripheral device. The CPU 9 reads the Windows OS recorded on the hard disk, writes it in the main memory 13 and executes it. Thereafter, the merchandise sales processing program recorded in the HDD 17 is read, and the POS terminal 1 becomes ready to execute merchandise sales processing.
[0042]
FIG. 4 is a time chart of various signals. In the normal state in which the POS terminal 1 can execute the sales process of the product, the / RESET signal, the / RESETD signal, the SIOGP10 signal, the SIOGP11 signal, and the SIOGP12 signal are held at the H level as shown in FIG. . In addition, the / EXTSMI signal also holds the H level.
[0043]
Here, in the switching circuit 15, since the / RESETD signal is at the H level, the output signal of the AND gate 19b is at the H level, and since the SIOGP10 signal is at the H level, the output signal of the AND gate 19a is at the H level. As a result, the CLR terminal of the flip-flop 18a is kept at the H level.
[0044]
Since the SIOGP11 signal is at the H level, the PR terminal of the flip-flop 18b is also at the H level. Since the SIOGP12 signal and the output signal of the AND gate 19b are at the H level, the output signal of the AND gate 19c is at the H level. As a result, the CLR terminal of the flip-flop 18b is kept at the H level.
[0045]
A case where a memory error occurs as a system error in the circuit state during the sales process of the product by the POS terminal 1, that is, during the startup of the Windows OS will be described.
[0046]
Here, the memory error means that the data read from the main memory 13 is in a different state compared to the time of writing. This memory error is detected using ECC (Error-Correcting Code) which is a code added separately from the original data.
[0047]
When a memory error occurs as a system error, the CPU / memory control unit 11 notifies the peripheral bus control unit 12 of the occurrence of the memory error. Due to the occurrence of this memory error, the NMI signal becomes H level.
[0048]
In the switching circuit 15, since the NMI signal becomes H level, the CK terminal of the flip-flop 18a becomes H level. As a result, the / EXTSMI signal, which is an output signal from the / Q terminal of the flip-flop 18a, becomes L level.
[0049]
When the / EXTSMI signal becomes L level, the SMI signal is input from the peripheral bus control unit 12 to the CPU 9. With this SMI signal input, the system control right of the CPU 9 is transferred from the Windows OS to the BIOS. As a result, the SMI module software incorporated in the BIOS is activated without depending on the application or OS being executed.
[0050]
FIG. 5 is a flowchart showing the flow of processing by the SMI module software. As shown in FIG. 5, the SMI module software confirms the related register status of the CPU 9, investigates / records the cause of the system error (memory error), and further performs processing for the cause (step S1).
[0051]
If the memory error is a 1-bit error, the 1-bit error is repaired by ECC. However, when the memory error is an error of 2 bits or more, the memory error cannot be repaired by the ECC, and the memory error is not repaired.
[0052]
After the error processing is completed, when the SIOGP10 signal input to the switching circuit 15 from the peripheral bus control unit 12 is set to the L level, the output signal of the AND gate 19a is set to the L level in the switching circuit 15, so that the flip-flop 18a The CLR terminal becomes L level. As a result, the output signal from the / Q terminal of the flip-flop 18a becomes H level.
[0053]
Therefore, since the / EXTSMI signal is held at the H level again, the SMI signal is not input from the peripheral bus control unit 12 to the CPU 9, and the system control right is returned from the BIOS to the Windows OS (S2).
[0054]
Then, it is determined whether or not it is necessary to input the CPUNMI signal to the CPU 9 (S3). At this time, if the memory error is a 1-bit error, it is not necessary to input the CPUNMI signal to the CPU 9 because the memory error has been repaired (N in S3), and the program ends. Then, the Windows OS causes the CPU 9 to execute various processes as if nothing happened.
[0055]
Here, when the memory error is an error of 2 bits or more, since the memory error is not repaired by the ECC, it is necessary to input the CPUNMI signal to the CPU 9 in order to initialize and restart the system (S3). Y).
[0056]
For this purpose, the CPU 9 keeps the SIOGP11 signal input from the peripheral bus control unit 12 to the switching circuit 15 at the L level for a predetermined time based on the SMI module software. Then, in the switching circuit 15, the PR terminal of the flip-flop 18b becomes L level. In addition, since the CLR terminal of the flip-flop 18a is kept at the H level, the output signal from the Q terminal of the flip-flop 18b becomes the H level.
[0057]
Since the / RESETD signal is at the H level and the tristate buffer 20b is in the conductive state, the output signal from the Q terminal of the flip-flop 18b becomes the CPUNMI signal, and the CPUNMI signal is kept at the H level.
[0058]
Next, the SIOGP12 signal input from the peripheral bus control unit 12 to the switching circuit 15 is set to the L level. Then, in the switching circuit 15, the output signal of the AND gate 19c becomes H level. As a result, the CLR terminal of the flip-flop 18b becomes H level. In addition, since the PR terminal of the flip-flop 18a is kept at the H level, the output signal from the Q terminal of the flip-flop 18b becomes the L level.
[0059]
Since the / RESETD signal is at the H level and the tristate buffer 20b is in the conductive state, the output signal at the Q terminal of the flip-flop 18b becomes the CPUNMI signal, and the CPUNMI signal changes from the H level to the L level.
[0060]
Thus, the CPUNMI signal generated by the switching circuit 15 is input to the CPU 9 (S4), and the program ends.
[0061]
The CPU 9 knows that a system error has occurred and performs predetermined error processing by the Windows OS. Since the memory error of 2 bits or more has not been repaired, in order to initialize and restart the system, the CPU / memory control unit 11 inputs a / RESET signal to the CPU 9 to restart the CPU 9. Again, the CPU 9 performs an initial setting operation, reads and executes the Windows OS, reads the merchandise sales processing program recorded in the HDD 17, and sets the POS terminal 1 in a state in which the merchandise sales processing can be executed.
[0062]
In the POS terminal 1 of the present embodiment, when a system error occurs, the signal input to the CPU 9 is switched from the NMI signal to the SMI signal, so that the system control right when the system error occurs is changed from the Windows OS to the BIOS. Since each company can develop its own BIOS, it is possible to execute error handling that is unique to each company even in information processing devices that employ Windows-based OSs. As a result, the reliability of the information processing apparatus can be improved and the added value can be pursued.
[0063]
Further, when a system error occurs, the switching circuit 15 generates an / EXTSMI signal based on the NMI signal and the SIOGP10 signal input from the peripheral bus control unit 12, and the peripheral bus control unit 12 based on the / EXTSMI signal. By inputting the SMI signal to the CPU 9, the system control right when the system error occurs can be transferred from the Windows OS to the BIOS or returned to the BIOS, and the system control right can be transferred from the BIOS to the BIOS system without releasing the system error. When the OS is returned to the OS, the CPU NMI signal generated by the switching circuit 15 based on the SIOGP11 signal and the SIOGP12 signal input from the peripheral bus control unit 12 is input to the CPU 9, thereby causing the Windows OS to generate a system error. Inform Door can be.
[0064]
An information processing apparatus according to the second embodiment of the present invention will be described. As an example of the information processing apparatus according to the present embodiment, a POS terminal that is a merchandise sales data processing apparatus that executes merchandise sales processing will be described with reference to FIGS. In addition, the same part as the part demonstrated in 1st embodiment is shown with the same code | symbol, and description is also abbreviate | omitted. The basic configuration of this embodiment is almost the same as that of the first embodiment.
[0065]
FIG. 6 is a block diagram showing an electrical connection of each unit provided in the POS terminal 1 of the present embodiment. The difference between the present embodiment and the first embodiment is that, as shown in FIG. 6, the / EXTSMI signal is not input from the switching circuit 15 to the peripheral bus control unit 12 (see FIG. 2). An SMI signal is input from the control unit 12 to the switching circuit 15, and a CPU SMI (Central Processing Unit System Management Interrupt) signal is input from the switching circuit 15 to the CPU 9 based on the NMI signal and the SIOGP10 signal. Here, the CPUSMI signal is a non-maskable interrupt signal having a higher interrupt priority than the NMI signal and the CPUNMI signal, like the SMI signal.
[0066]
FIG. 7 is a schematic circuit diagram showing the switching circuit 15 built in the POS terminal 1 of the present embodiment. As shown in FIG. 7, the circuit configuration of the present embodiment is almost the same as that of the first embodiment. The difference from the first embodiment is that the SMI signal becomes a CPU SMI signal. The output signal from the / Q terminal of the flip-flop 18a is connected and output as the CPUSMI signal via the inverter 22. This is a circuit that generates a CPU SMI signal based on the NMI signal and the SIOGP10 signal.
[0067]
In such a configuration, the processing operation of the CPU 9 in the POS terminal 1 is almost the same as that of the first embodiment. The difference from the first embodiment is that the / EXTSMI signal is not generated and the CPUSMI is not generated. This is where the signal is generated.
[0068]
FIG. 8 is a time chart of various signals. More specifically, as shown in FIGS. 7 and 8, when a memory error occurs and the NMI signal becomes H level, in the switching circuit 15, the CK terminal of the flip-flop 18a becomes H level. As a result, the output signal from the / Q terminal of the flip-flop 18 a becomes L level and becomes H level via the inverter 22. Therefore, the CPUSMI signal becomes H level.
[0069]
When the CPUSMI signal becomes H level, the system control right of the CPU 9 is transferred from the Windows OS to the BIOS. As a result, the SMI module software incorporated in the BIOS is activated without depending on the application or OS being executed.
[0070]
The flow of processing by the SMI module software is almost the same as in the first embodiment (see FIG. 5). However, when the SIOGP10 signal input from the peripheral bus control unit 12 to the switching circuit 15 is set to L level in step S2, the output signal of the AND gate 19a is set to L level in the switching circuit 15, so that the flip-flop 18a The CLR terminal becomes L level. As a result, the output signal from the / Q terminal of the flip-flop 18 a becomes H level and becomes L level via the inverter 22. Therefore, since the CPUSMI signal is held at the L level, the system control right is returned from the BIOS to the Windows OS. The subsequent processing is exactly the same as in the first embodiment.
[0071]
In the POS terminal 1 of the present embodiment, when a system error occurs, the signal input to the CPU 9 is switched from the NMI signal to the SMI signal, so that the system control right when the system error occurs is changed from the Windows OS to the BIOS. Since each company can develop its own BIOS, it is possible to execute error handling that is unique to each company even in information processing devices that employ Windows-based OSs. As a result, the reliability of the information processing apparatus can be improved and the added value can be pursued.
[0072]
Further, when a system error occurs, a CPU SMI signal is generated by the switching circuit 15 based on the NMI signal and SIOGP10 signal input from the peripheral bus control unit 12, and this CPU SMI signal is input from the switching circuit 15 to the CPU 9. The system control right when a system error occurs can be transferred from the Windows OS to the BIOS or returned to the BIOS. When the system control right is returned from the BIOS to the Windows OS without being able to cancel the system error, the peripheral bus By inputting the SIOGP11 signal input from the control unit 12 and the CPUNMI signal generated by the switching circuit 15 based on the SIOGP12 signal to the CPU 9, it is possible to notify the Windows OS of the occurrence of a system error.
[0073]
【The invention's effect】
According to the information processing apparatus of the first aspect of the present invention, the NMI signal that is an unmaskable interrupt signal or the SMI signal that is an unmaskable interrupt signal having a higher interrupt priority than the NMI signal can be interrupted. CPU for executing various arithmetic processes and programs, memory for storing various programs and data, CPU / memory control unit for controlling CPU and memory, peripheral bus control unit for controlling bus connection of peripheral devices, and system A switching circuit that switches an NMI signal input to the CPU to an SMI signal when an error occurs, so that by switching the signal input to the CPU from an NMI signal to an SMI signal when a system error occurs, System control right when a system error occurs can be transferred from Windows OS to BIOS Therefore, by developing a BIOS unique to each company, even an information processing device adopting a Windows OS can execute error processing unique to each company. It becomes possible to improve the reliability of the processing apparatus and pursue added value.
[0074]
According to the second aspect of the present invention, in the information processing device according to the first aspect, the peripheral bus control unit outputs the NMI signal, the first SIOGP signal, the second SIOGP signal, and the third SIOGP signal to the switching circuit, The SMI signal is output to the CPU, and the switching circuit causes the peripheral bus control unit to output the SMI signal based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs / Since the EXTMI signal is generated as an input signal of the peripheral bus control unit, and the CPUNMI signal is generated as an interrupt signal to the CPU based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit. When the system error occurs, the switching circuit is based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit. The system control right when a system error occurs is transferred from the Windows OS to the BIOS or returned by inputting the SMI signal from the peripheral bus control unit to the CPU based on the / EXTSMI signal. When the system control right is returned from the BIOS to the Windows OS without being able to cancel the system error, the switching circuit based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit By inputting the generated CPUNMI signal to the CPU, it is possible to notify the Windows OS of the occurrence of a system error.
[0075]
According to a third aspect of the present invention, in the information processing apparatus according to the first aspect, the peripheral bus control unit uses the NMI signal, the SMI signal, the first SIOGP signal, the second SIOGP signal, and the third SIOGP signal as a switching circuit. The switching circuit generates a CPU SMI signal as an interrupt signal to the CPU based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs, and generates a peripheral bus Since the CPUNMI signal is generated as an interrupt signal to the CPU based on the second SIOGP signal and the third SIOGP signal input from the control unit, the NMI input from the peripheral bus control unit when a system error occurs. A CPU SMI signal is generated by the switching circuit based on the signal and the first SIOGP signal, and the CPU SMI signal is converted into the switching circuit. The system control right when a system error occurs can be transferred to the BIOS from the Windows OS to the BIOS, and the system control right can be returned from the BIOS to the Windows OS without releasing the system error. In this case, a CPU NMI signal generated by the switching circuit based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit is input to the CPU, thereby informing the Windows OS that a system error has occurred. be able to.
[Brief description of the drawings]
FIG. 1 is an external perspective view schematically showing a POS terminal according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical connection of each unit provided in the POS terminal.
FIG. 3 is a schematic circuit diagram showing a switching circuit built in the POS terminal.
FIG. 4 is a time chart of various signals.
FIG. 5 is a flowchart showing a flow of processing by SMI module software.
FIG. 6 is a block diagram showing an electrical connection of each unit provided in the POS terminal according to the second embodiment of this invention.
FIG. 7 is a schematic circuit diagram showing a switching circuit built in the POS terminal.
FIG. 8 is a time chart of various signals.
FIG. 9 is a block diagram showing electrical connection of each unit provided in a conventional POS terminal.
[Explanation of symbols]
9 CPU
13, 14 memory
11 CPU / memory control unit
12 Peripheral bus control unit
15 switching circuit

Claims (3)

It can be interrupted by an NMI (Non-Maskable Interrupt) signal that is an unmaskable interrupt signal or an SMI (System Management Interrupt) signal that is an unmaskable interrupt signal having a higher interrupt priority than the NMI signal. CPU (Central Processing Unit) that executes arithmetic processing and programs,
A memory for storing various programs and data;
A CPU / memory control unit for controlling the CPU and the memory;
A peripheral bus control unit for controlling the peripheral device bus connection;
A switching circuit that switches the NMI signal input to the CPU to the SMI signal when a system error occurs;
An information processing apparatus comprising: The peripheral bus control unit outputs the NMI signal, a first SIOGP (Super I / O IC's General Pins) signal, a second SIOGP signal, and a third SIOGP signal to the switching circuit, and outputs the SMI signal to the CPU. do it,
The switching circuit causes the peripheral bus control unit to output the SMI signal based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs / EXTSMI (EXTernal System Management Interrupt) signal is generated as an input signal of the peripheral bus control unit, and based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit, a CPU NMI (Central Processing Unit System Management) The information processing apparatus according to claim 1, wherein an interrupt signal is generated as an interrupt signal to the CPU. The peripheral bus control unit outputs the NMI signal, the SMI signal, the first SIOGP signal, the second SIOGP signal, and the third SIOGP signal to the switching circuit,
The switching circuit sends a CPU SMI (Central Processing Unit Non-Maskable Interrupt) signal to the CPU based on the NMI signal and the first SIOGP signal input from the peripheral bus control unit when a system error occurs. Generate as interrupt signal,
The CPU NMI (Central Processing Unit System Management Interrupt) signal is generated as an interrupt signal to the CPU based on the second SIOGP signal and the third SIOGP signal input from the peripheral bus control unit. Information processing device.

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