JP3844807B2 - Solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device that outputs the amount of light received by a photoelectric conversion device as digital data.
[0002]
[Prior art]
In recent years, with the spread of image processing technology, MOS type solid-state imaging devices having a photoelectric conversion function have been developed, and various solid-state imaging devices using these have been known. Along with the demand for higher resolution of images, the photodiodes constituting the pixels at the time of imaging tend to be miniaturized and a large number of photodiodes tend to be used to secure the imaging area.
[0003]
However, as the number of photodiodes increases, for high-speed processing, an analog-digital converter (hereinafter referred to as AD) that converts an analog value, which is the amount of light received by the photodiode, into a digital value that is a suitable data format for image processing calculations. Will inevitably increase).
[0004]
Therefore, proposals have been made to reduce the cost and size by integrating charge amplifiers and AD converters that amplify charges output as current signals from photodiodes into an array. Since the circuit system of the charge amplifier is almost established, the device for integration is concentrated on the circuit system of the AD converter.
[0005]
One of these proposals is "SLGarverick et al., Journal of Solid-State Circuits, Vol. 30, No. 5, May 1995, pp. 533-541" (hereinafter referred to as Conventional Example 1). . In Conventional Example 1, the charge generated in the photodiode as a result of light reception is accumulated in a feedback capacitance element using a charge amplifier, converted into a voltage signal, and this voltage value is held. Thereafter, AD conversion is performed by sequentially comparing the voltage values of voltage signals that change in a stepwise manner common to all the arrays (in a so-called dual slope AD conversion method).
[0006]
Also, Burr-Brown has announced a model name “DDC101” (hereinafter referred to as Conventional Example 2) as an AD converter dedicated to reading out a CT (Computer Tomography) photodiode. Conventional example 2 applies the principle of a Δ modulator to AD conversion, and each operation is performed in synchronization with a high-speed clock having a period of several tenths to one hundredths compared to the integration time. Is called.
[0007]
That is, every time the clock cycle of the high-speed clock signal is switched, a step voltage is generated in small increments and applied to the capacitive element. The resulting change in the accumulated charge of the capacitor is compared with the amount of charge from the photodiode, and the excess or deficiency of the charge is corrected in the next clock cycle. Then, a digital signal pulse train of “0” or “1” is generated according to the comparison result in each clock cycle. The digital signal pulse train is passed through a digital filter (such as an FIR filter) to obtain a highly accurate AD conversion result.
[0008]
Also, a technology that applies the principle of the ΣΔ modulator to AD conversion is disclosed in “RHNixon et al., Proc. SPIE, vol.1900, 1993, pp.31-39” (hereinafter referred to as Conventional Example 3). Has been. In Conventional Example 3, the charge amount generated in the photodiode corresponding to each pixel is converted into a voltage signal and then held. The hold result is subjected to first-order ΣΔ modulation by a one-stage ΣΔ modulator, and the total number of “1” pulses in the digital signal pulse train of “0” or “1” as a modulation result is counted by a counter, An AD conversion value is obtained.
[0009]
A technique of an AD converter that applies the principle of the ΣΔ modulator is disclosed in Japanese Patent Laid-Open No. 6-237175 (hereinafter referred to as Conventional Example 4). In Conventional Example 4, a voltage signal is input, second-order ΣΔ modulation is performed by a two-stage ΣΔ modulator, a modulation result “0” or “1” digital signal pulse train is output, and an AD conversion result A voltage signal corresponding to the total number of “1” pulses in the digital signal pulse train is generated by a digital-to-analog converter and added to the reference voltage of the ΣΔ modulator, thereby removing the offset of the ΣΔ modulator.
[0010]
[Problems to be solved by the invention]
Since the conventional solid-state imaging device is configured as described above, there are the following problems.
[0011]
In Conventional Example 1, when noise is superimposed on the stepped voltage signal to be compared, the influence cannot be removed, and it is difficult to stably maintain the conversion accuracy.
[0012]
Further, in the conventional example 1, in order to improve the conversion accuracy, that is, the resolution of AD conversion, it is necessary to lengthen the conversion time. However, in the case of being used as an AD converter exclusively for reading X-ray CT photodiodes, Considering the need to reduce the exposure to the subject, the conversion time cannot be lengthened. As a result, the conversion accuracy is limited.
[0013]
In the method of Conventional Example 2, the technical point is how to accurately apply the step charge amount to the capacitance to which the step voltage is applied. In Conventional Example 2, the value corresponding to the charge accumulation amount is a digital value. As a result, and a charge accumulation amount is given to the capacitor element array constituting the capacitor, the circuit size becomes large. That is, Conventional Example 2 is a technique originally proposed for the purpose of a single-element photodiode, and is not suitable for multi-element integration.
[0014]
Further, in the conventional example 2, since Δ modulation is employed, high accuracy can be realized when the change amount of the current value from the photoelectric conversion element is small, but the change amount of the current value from the photoelectric conversion element is large. In this case, the linearity of the conversion becomes worse.
[0015]
In Conventional Example 3, since the charge amount generated in the photodiode is once converted into a voltage and held, and then input to the ΣΔ modulator, oversampling is performed only on the held DC voltage. As a result, noise generated during the integration period is accumulated as it is, and it is difficult to stably maintain the conversion accuracy.
[0016]
Further, in the conventional example 3, since an offset voltage generally exists in the ΣΔ modulator, this offset potential is integrated together in integration, so that the conversion accuracy is lowered.
[0017]
Such problems relating to the offset voltage have been solved in the conventional ΣΔ modulation type AD converter, but since the DA converter is used as the solution means, the circuit scale becomes large and is not suitable for integration. .
[0018]
In the first to third conventional examples, no countermeasure is taken for dark current, which is a problem peculiar to a photodiode. As a result, when a photodiode having a relatively large light receiving area is used, the dark current increases. However, in the conventional examples 1 to 3, since there is no means for distinguishing the dark current from the signal current, the accuracy is high. An imaging result cannot be obtained.
[0019]
The present invention has been made in view of the above, and has a simple circuit configuration, reduces the influence of dark current according to the amount of light received by a photoelectric conversion element, and outputs high-precision digital data. An object is to provide an element.
[0020]
[Means for Solving the Problems]
The solid-state imaging device of the present invention adopts a method of performing ΣΔ modulation while removing dark current, and adopts a direct current input method in which the offset potential of the ΣΔ modulator does not inherently become a problem during signal input. Thus, a solid-state imaging device that outputs high-precision digital data is realized.
[0021]
That is,The present inventionIn the solid-state imaging device (a), the first terminal is set to a third reference potential between the first reference potential and the second reference potential, and a charge corresponding to the amount of received light is generated and the second is set. At least one photoelectric conversion element that discharges electric charge from the terminal, (b) a dark current removal circuit that removes the dark current of the photoelectric conversion element, and (c) the photoelectric conversion elementSecond terminalAnd a first feedback capacitive element in which the first terminal and the first terminal are directly connected, and (d) of the photoelectric conversion elementSecond terminalAnd a signal input terminal are electrically connected directly, and a first charge amplifier in which an output terminal is connected to a second terminal of the first feedback capacitive element, and (e) a first reference potential and a second A first step charge generator for generating a step charge from the reference potential and supplying the step charge to the first feedback capacitive element; and (f) a first integrated voltage signal output from the first charge amplifier. And a potential comparator that compares the potential of the first integrated voltage signal with the third reference potential and outputs a comparison result signal corresponding to the comparison result, and (g) a comparison result signal is input and compared. A binary sampling circuit for binary-sampling the result signal; (h) the first clock signal; and the first clock signal is insignificant at a significant level and is part of the insignificant level period of the first clock signal And a second clock signal that becomes significant in a period of A basic timing generation circuit that outputs the first clock signal and the second clock signal toward the step charge generator and outputs the first clock signal toward the binary sampling circuit. Features.Further, the dark current elimination circuit includes a field effect transistor (FET) such as a MOS whose source terminal is connected to the signal input terminal of the first charge amplifier and whose drain terminal is set to the third reference potential, The dark current storage capacitor element in which the gate terminal and the first terminal of the effect transistor are connected and the second terminal is set to the third reference potential; the first terminal of the dark current storage capacitor element; And a current holding switch element to which the output terminal of the first charge amplifier and the second terminal are connected.
[0023]
Also, an output signal from the binary sample circuit is input, and an output signal from the binary sample circuit and an inverted signal of the output signal from the binary sample circuit are directed to the first step charge generator as a step charge generation instruction. It is preferable to further include a first step charge generation control circuit that outputs the first step.
[0024]
The present inventionIn this solid-state imaging device, prior to light reception, the photoelectric conversion element is set to a state in which light is not received over a predetermined period, which is a dark current component detection period, and is detected as dark current over this period. While being stored in the removal circuit, the same amount of current as the stored dark current is always removed from the input current to the charge amplifier.
[0025]
For example, the current holding switch element is closed without receiving light from the photoelectric conversion element, and a voltage corresponding to the amount of dark current generated at this time is generated in the dark current storage capacitor element. Since this voltage is applied to the gate terminal of the field effect transistor, dark current flows from the source to the drain of the field effect transistor.
[0026]
Next, when the current holding switch element is opened, the voltage generated in the dark current storage capacitor element at that time is held, and thereafter, the dark current is removed from the input current to the charge amplifier. Thereafter, imaging is performed in this state.
[0027]
When the photoelectric conversion element receives light, a charge corresponding to the amount of light received is generated and output as a current signal. This current signal is input to a first integration circuit composed of a first feedback capacitance element and a first charge amplifier, and is integrated over time.
[0028]
Here, the photoelectric conversion elementSecond terminalAnd the first terminal of the first feedback capacitive element and the signal input terminal of the first charge amplifier are directly electrically connected, and the current integration itself is not essentially affected by the offset voltage. Therefore, the voltage value output as a result of the integration operation is not affected by the offset voltage at all.
[0029]
The above-mentioned “directly connected” means that there are no components (resistive element, inductor element, capacitive element, amplifier, attenuator, etc.) that change the signal mode in the signal transmission path. It means that there are no parts in the signal transmission path and that only the switch element is interposed for signal transmission.
[0030]
On the other hand, according to the first clock signal and the second clock signal supplied from the basic timing generation circuit, the first step charge generator corresponds to one of the first reference potential and the second reference potential. The charge is generated and injected into the first feedback capacitor in synchronization with the clock signal (or the charge is extracted from the first feedback capacitor). Here, regarding the generation of electric charge, the electric charge corresponding to one of the first reference potential or the second reference potential is set in accordance with the output signal of the binary sampling circuit supplied from the binary sampling circuit and its inverted signal. It is preferable to generate.
[0031]
Thus, the first integration circuit accumulates the electric charge generated by the photoelectric conversion element in the first feedback capacitance element and executes the integration operation, while performing the first feedback for each cycle of the timing generated by the basic timing generation circuit. The ΣΔ modulation is executed by further accumulating electric charge in the capacitive element or extracting the electric charge from the first feedback capacitive element. The result of the ΣΔ modulation is obtained as an output signal of the first integration circuit that is the output voltage of the first charge amplifier corresponding to the amount of charge accumulated in the first feedback capacitive element. That is, the first integration circuit and the first step charge generator constitute a current input first ΣΔ modulator that is not affected by the offset voltage.
[0032]
The first integrated voltage signal output from the first charge amplifier is input to the potential comparator. The potential comparator compares the input potential of the first integrated voltage signal with the third reference potential, and outputs a binarized comparison result signal corresponding to the comparison result. This comparison signal is input to the binary sampling circuit, sampled at the same cycle as the timing cycle generated by the basic timing generation circuit (for example, in synchronization with the first clock signal), and “0” or “ 1 "is output as a digital signal sequence. By processing this digital signal sequence (for example, counting the number of “1” s in the integration period), an AD conversion result can be obtained.
[0033]
The present inventionIn the solid-state imaging device of the first aspect, the first step charge generator includes: (i) a first switch that opens and closes according to an output signal from the binary sample circuit by inputting a first reference potential from a first terminal; An element; (ii) a second switching element that receives a second reference potential from the first terminal and opens and closes in response to an inverted signal of the output signal from the binary sampling circuit; and (iii) a third reference A third switch element that opens and closes in response to the first clock signal by inputting a potential from the first terminal; and (iv) a third reference potential that is input from the first terminal to generate a first clock signal. A fourth switch element that opens and closes in response; and (v) a first terminal connected to the second terminal of the third switch element, and a second terminal connected to the second terminal of the fourth switch element. First step charge generation capacitor element, and (vi) first step charge generation capacitor A first switch terminal connected to the first terminal; an input terminal connected to the second terminal of the first charge amplifier; and a fifth switch element that opens and closes in response to a second clock signal; , (Vii) the second terminal of the first switch element, the second terminal of the second switch element, and the first terminal are connected, and the second terminal of the first step charge generation capacitor element and the second terminal The second terminal is connected, and a sixth switch element that opens and closes in response to the second clock signal is preferably configured.
[0034]
According to the first step charge generator, when the first clock signal becomes significant, the third switch element and the fourth switch element are closed, and the first step charge generator capacitive element Since the potential becomes the third reference potential, the charge accumulated in the first step charge generation capacitive element becomes zero. The first clock signal isNonWhen the second clock signal becomes significant after the third switch element and the fourth switch element are opened, the fifth switch element and the sixth switch element are closed. As a result, a step charge corresponding to either the first reference potential or the second reference potential is generated in the first step charge generation capacitive element.
[0035]
Depending on the generation of the step charge, the first feedback capacitive element is given a charge corresponding to the step charge, or the charge is removed from the first feedback capacitive element by the step charge. As a result, the ΣΔ modulation is preferably executed in cooperation with the first integration circuit.
[0036]
The solid-state imaging device of the present invention isBetween the first charge amplifier and the potential comparator, (a) a signal sample circuit that samples the first integration signal at the instructed timing and outputs an AC component; and (b) output from the signal sample circuit. A feedback capacitance circuit having a second feedback capacitance element that inputs the received signal from the first terminal, and (c) a signal output from the signal sampling circuit is input from the input terminal, and the output terminal is the second feedback capacitance circuit. (D) a second step of generating a step charge from the first reference potential and the second reference potential and supplying the step charge to the second feedback capacitance element And a charge generator, wherein the potential comparator receives the second integration signal output from the second charge amplifier.
[0037]
Here, the output signal from the binary sampling circuit is input, and the first step charge generator is used with the output signal from the binary sampling circuit and the inverted signal of the output signal from the binary sampling circuit as a step charge generation instruction. It is preferable to further include a second step charge generation control circuit that outputs to the second step charge generator.
[0038]
Of the present inventionIn the solid-state imaging device, the second integration circuit including the feedback amplifier circuit and the second charge amplifier and the second step charge generator constitute a voltage input second ΣΔ modulator.
[0039]
The modulation result output from the first ΣΔ modulator is further ΣΔ modulated by the second ΣΔ modulator. As a result, the change in the output reference potential accompanying the current emission of the photoelectric conversion element, which normally occurs in one-stage ΣΔ modulation, is eliminated. As a result, the AD change value can be obtained with high accuracy by comparison with the third reference potential later.
[0040]
Of the present inventionIn the solid-state imaging device, the output signal from the first ΣΔ modulator is sampled in synchronization with the first clock signal and the second clock signal by the signal sampling circuit, and the electric charge generated as a sampling result is second integrated. Accumulate and integrate in the circuit.
[0041]
On the other hand, the second step charge generator has a first reference potential or a second reference potential according to the first clock signal and the second clock signal supplied from the basic timing generation circuit. The charge is generated and injected into the second feedback capacitor in synchronization with the clock signal (or the charge is extracted from the second feedback capacitor). Here, regarding the generation of electric charge, the electric charge corresponding to one of the first reference potential or the second reference potential is set in accordance with the output signal of the binary sampling circuit supplied from the binary sampling circuit and its inverted signal. It is preferable to generate.
[0042]
Thus, in the second integration circuit, the charge generated in the sample of the output of the first ΣΔ modulator is accumulated in the second feedback capacitance element and the integration operation is performed, and the timing generated by the basic timing generation circuit is determined. The ΣΔ modulation is executed by accumulating charges in the second feedback capacitive element every period or extracting charges from the second feedback capacitive element. The result of the ΣΔ modulation is obtained as an output signal of the second integration circuit that is the output voltage of the second charge amplifier according to the amount of charge accumulated in the second feedback capacitive element.
[0043]
The second integrated voltage signal output from the second charge amplifier is input to the potential comparator. The potential comparator compares the potential of the input second integrated voltage signal with the third reference potential, and outputs a binarized comparison result signal corresponding to the comparison result. This comparison signal is input to the binary sampling circuit, sampled at the same cycle as the timing cycle generated by the basic timing generation circuit (for example, in synchronization with the first clock signal), and “0” or “ 1 "is output as a digital signal sequence. By processing this digital signal sequence (for example, counting the number of “1” s in the integration period), an AD conversion result can be obtained.
[0044]
Of the present inventionIn the solid-state imaging device, the signal sample circuit includes: (i) a seventh switch element that is connected to the output terminal of the first charge amplifier and the first terminal and opens and closes in response to the first clock signal; and (ii) It is possible to include a signal transmission capacitive element in which the second terminal and the first terminal of the seventh switch element are connected, and the input terminal of the second charge amplifier and the second terminal are connected. It is.
[0045]
In this case, the second step charge generator includes (i) an eighth switch element that receives the first reference potential from the first terminal and opens and closes according to the output signal from the binary sample circuit; ii) a ninth switch element that inputs a second reference potential from the first terminal and opens / closes in response to an inverted signal of the output signal from the binary sampling circuit; and (iii) a second switch element of the eighth switch element. And the second terminal of the ninth switch element and the first terminal are connected, the first terminal and the second terminal of the signal transmission capacitive element are connected, and in response to the second clock signal. A feedback capacitance circuit comprising: (i) a second feedback capacitance element having a first terminal connected to a signal input terminal of the second charge amplifier; and (ii) a first capacitance element. The second charge amplifier is connected to the second terminal and the first terminal of the two feedback capacitance elements. An eleventh switch element connected to the output terminal and the second terminal and opened / closed in response to an inverted signal of the first clock signal, and (iii) a first terminal as a signal input terminal of the second charge amplifier Are connected, the second terminal is connected to the output terminal of the second charge amplifier, and a twelfth switch element that opens and closes in response to the first clock signal is preferably provided.
[0046]
According to the combination of the signal sampling circuit, the second step charge generator, and the feedback capacitance circuit, the output signal of the first ΣΔ modulator is sampled by the signal sampling circuit according to the first clock signal. In the meantime, the twelfth switch element is closed and the input terminal and the output terminal of the second charge amplifier are short-circuited, and an offset voltage is generated. However, since the eleventh switch element is open during this period, the charge accumulated in the second feedback capacitance element is stored as it is. In addition, since the second terminal of the signal transmission capacitive element remains connected to the input terminal of the second charge amplifier, the offset voltage remains applied. Therefore, even if the eleventh switch element is closed in response to the second clock signal after the twelfth switch element is opened and the state is changed to a state where charges are accumulated in the second feedback capacitor element, the influence of the offset voltage is exerted. Does not appear. In this way, ΣΔ modulation having no offset effect is executed.
[0047]
Also,The present inventionIn the solid-state imaging device, the signal sample circuit includes: (i) a thirteenth switch element that is connected to the output terminal of the first charge amplifier and the first terminal and opens / closes in response to the first clock signal; ) A signal transmission capacitive element in which the second terminal and the first terminal of the thirteenth switch element are connected; (iii) a second terminal and a first terminal of the signal transmission capacitive element are connected; A second terminal connected to the signal input terminal of the second charge amplifier, a fourteenth switch element that opens and closes in response to the second clock signal, and (iv) a third reference potential from the first terminal. The fifteenth switch element connected to the first terminal and the second terminal of the signal transmission capacitive element and opened and closed according to the second clock signal, and (v) a third reference potential Input from the first terminal, the second terminal and the second end of the signal transmission capacitive element Together but are connected, it can be constructed and a sixteenth switching element that opens and closes in response to the first clock signal.
[0048]
In this case, the second step charge generator includes (i) a seventeenth switch element that receives the first reference potential from the first terminal and opens and closes in response to an output signal from the binary sample circuit; ii) an 18th switch element that receives the second reference potential from the first terminal and opens / closes in response to the inverted signal of the output signal from the binary sampling circuit; and (iii) the third reference potential is the first A nineteenth switch element that is input from the first terminal and opens and closes in response to the first clock signal; and (iv) a third reference potential is input from the first terminal and opens and closes in accordance with the first clock signal. A second terminal in which a first terminal is connected to the twentieth switch element and (v) a second terminal of the nineteenth switch element, and a second terminal is connected to the second terminal of the twentieth switch element. A step charge generating capacitive element, and (vi) a second step charge generating capacitive element The first terminal and the first terminal, the input terminal of the second charge amplifier and the second terminal are connected, and a twenty-first switching element that opens and closes in response to the second clock signal; (Vii) The second terminal of the seventeenth switch element and the second terminal and the first terminal of the eighteenth switch element are connected, and the second terminal and the second terminal of the second step charge generation capacitor element And a twenty-second switching element that opens and closes in response to a second clock signal, and the feedback capacitance circuit has a first terminal connected to the signal input terminal of the second charge amplifier. It is preferable that the second feedback capacitive element having a second terminal connected to an output terminal of the second charge amplifier is provided.
[0049]
According to the combination of the signal sample circuit, the second step charge generator, and the feedback capacitor circuit, the signal sample circuit closes the thirteenth switch element and the sixteenth switch element in response to the first clock signal. Thus, when sampling the output signal of the first ΣΔ modulator, the second terminal of the signal transmission capacitive element is set to the third reference potential. In addition, after the thirteenth switch element and the sixteenth switch element are opened, the fourteenth switch element and the fifteenth switch element are closed in accordance with the second clock signal, and charge is supplied to the second feedback capacitor element. Is transferred, the first terminal of the signal transmission capacitive element is set to the third reference potential. Therefore, an offset voltage difference does not occur between sampling and charge transfer, and ΣΔ modulation that is not affected by the offset voltage is executed.
[0050]
The solid-state imaging device of the present invention isThe digital filter circuit further includes a digital filter circuit that inputs a digital data signal sequence output from the binary sample circuit and outputs a digital signal subjected to digital filtering.
[0051]
The present inventionAccording to the solid-state imaging device, since digital filtering is performed on the digital data signal sequence output from the binary sampling circuit and obtained as data, AD conversion with high accuracy can be executed.
[0052]
The solid-state imaging device of the present invention isThe capacitance value of the first feedback capacitance element and the capacitance value of the first step charge generation capacitance element are selected according to the time-varying characteristics of the output current of the photoelectric conversion element.
[0053]
The present inventionAccording to the solid-state imaging device, the capacitance value of the first feedback capacitive element and the capacitance of the first step charge generating capacitive element from the viewpoint of conversion accuracy and conversion speed according to the current range of the photoelectric conversion element to be employed. Since the capacitance value is selected, optimum conversion accuracy and conversion speed can be achieved. The first feedback capacitive element and the first step charge generating capacitive element of different types are set with a constant ratio between the capacitance value of the first feedback capacitive element and the capacitance value of the first step charge generating capacitive element. Are preferably prepared in pairs and can be selected from these pairs.
[0054]
The solid-state imaging device of the present invention isA plurality of photoelectric conversion elements are arranged in a one-dimensional or two-dimensional manner, and further include a selection circuit that selects one of the photoelectric conversion elements connected to the first terminal of the first feedback capacitance element. It is characterized by that.
[0055]
Here, the selection circuit can select (i) the photoelectric conversion elements in a predetermined order or (ii) a random order.
[0056]
The present inventionAccording to the solid-state imaging device, AD conversion related to a plurality of photoelectric conversion devices is performed by one AD converter, so that the number of AD converters to be mounted can be reduced, and integration is facilitated.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the solid-state imaging device of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.
[0058]
(First embodiment)
FIG. 1 is a circuit configuration diagram of a first embodiment of a solid-state imaging device of the present invention. In this embodiment, AD conversion is performed by performing one-stage ΣΔ modulation. As shown in FIG. 1, the solid-state imaging device of the present embodiment includes (a) a photodiode whose ground is connected to the cathode, generates a charge corresponding to the amount of received light, and flows out from the anode, and (b) a photodiode. A dark current removal circuit 700 that removes 100 dark current; (c) a current signal output from the photodiode 100; and a ΣΔ modulator 210 that integrates the inflowed charge and performs ΣΔ modulation; A comparator 300 that receives the modulation signal MS output from the ΣΔ modulator 210, compares the potential of the modulation signal MS with the ground potential, and outputs a binary comparison result signal CMP according to the comparison result; e) A comparison result signal CMP is input, sampled in synchronization with the clock CLK1, and a binary sample circuit 400 that outputs a binary digital signal D1; and (f) a signal D1 is input, and a signal D And a step charge generation control circuit 460 that outputs an inverted signal D1 * of the signal D1 to the ΣΔ modulator 210, and (g) a digital signal D1 is input and subjected to digital filtering, and an AD conversion result is obtained. A digital filter circuit 500, and (h) a clock signal CLK1 and a clock signal CLK2 that is insignificant when the clock signal CLK1 is significant and significant during a part of the insignificant level period of the clock signal CLK1. The clock signal CLK1 and the clock signal CLK2 are output to the ΣΔ modulator 210, the clock signal CLK1 is output to the binary sample circuit 400 and the digital filter circuit 500, the reset signal RST, and the current holding instruction signal And a basic timing generation circuit 610 that outputs IH.
[0059]
The dark current elimination circuit 700 includes a field effect transistor (FET) 710 such as a MOS having a source terminal connected to the signal input terminal of the charge amplifier 222 and a drain terminal grounded, and (ii) a field effect transistor. A dark current storage capacitor element 720 having a gate terminal 710 connected to the first terminal and a second terminal grounded; and (iii) a first terminal and a first terminal of the dark current storage capacitor element 720. Are connected, the output terminal of the charge amplifier 222 is connected to the second terminal, and a current holding switch element 730 that opens and closes in response to the current holding instruction signal IH.
[0060]
The ΣΔ modulator 210 generates (i) an integration circuit 220 that accumulates and integrates the charge from the photodiode 100, and (ii) the clock signal CLK1 and the clock signal CLK2 based on the reference potential + Vref and the reference potential −Vref. A step charge generator 230 that generates a step charge in synchronization and supplies the step charge to the integration circuit 220.
[0061]
The integrating circuit 220 includes (i) a feedback capacitive element 221 (capacitance value = C11) in which the current output terminal of the photodiode 100 and the first terminal are directly electrically connected, and (ii) a current output of the photodiode 100. The terminal and a negative input terminal which is a signal input terminal (hereinafter also simply referred to as an input terminal) are directly electrically connected, and the positive input terminal is grounded so as to have the same potential as the cathode of the photodiode 100, A charge amplifier 222 whose output terminal is connected to the second terminal of the feedback capacitor 221; and (iii) an input terminal and a first terminal of the charge amplifier 222 are connected, and an output terminal and a second terminal of the charge amplifier 222 are connected. And a switch element 223 that opens and closes in response to a reset signal RST.
[0062]
The step charge generator 230 has (i) a reference potential + Vref input from the first terminal, a switch element 231 that opens and closes in response to the signal D1, and (ii) a reference potential −Vref input from the first terminal. The switch element 232 that opens and closes in response to the inverted signal D1 *, (iii) the first terminal is grounded, the switch element 233 that opens and closes in response to the clock signal CLK1, and (iv) the first terminal is grounded, and the clock (V) a step in which the first terminal is connected to the second terminal of the switch element 233 and the second terminal is connected to the second terminal of the switch element 234; The charge generation capacitive element 235 (capacitance value = C12) and (vi) the first terminal and the first terminal of the step charge generation capacitive element 235 are connected, and the input terminal of the charge amplifier 222 and the second terminal A switch element 236 that opens and closes in response to the clock signal CLK2, and (vii) a second terminal of the switch element 231 and a second terminal of the switch element 232 and the first terminal are connected, A second terminal and a second terminal of the charge generation capacitive element 235 are connected to each other, and a switch element 237 that opens and closes in response to the clock signal CLK2 is provided.
[0063]
The binary sample circuit 400 inputs the comparison result signal CMP to the data input terminal, inputs the clock signal CLK1 to the trigger terminal, samples the comparison result signal CMP at the rising edge of the clock signal CLK1, and outputs it from the data output terminal In addition, a D-type flip-flop capable of resetting the data output terminal by the reset signal RST is provided.
[0064]
The step charge generation control circuit 460 includes an inverter that inputs and inverts the signal D1.
[0065]
FIG. 2 is a circuit configuration diagram of the digital filter circuit 500. As shown in FIG. 2, the digital filter circuit 500 includes: (i) a counter 510 that can be reset by a reset signal RST, which inputs a clock signal CLK1 to a trigger terminal, counts the clock signal CLK1, and outputs a count value; (Ii) The count value signal CNT output from the counter 510 is input, the data table 520 that outputs the weighting data DWT corresponding to the count value, (iii) the weighting data DWT and the signal D1 are input, and the count value A multiplier 530 that calculates the product of the value of the signal D1 and outputs the product signal D2, and (iv) data that is input from the first data input terminal and is input from the second data input terminal An adder 540 that calculates the sum with the signal D3 and outputs the sum signal DS; and (v) a holding circuit 550 that latches the sum signal DS and outputs the data signal D3. Equipped with a.
[0066]
The solid-state imaging device of the present embodiment obtains digital data corresponding to the amount of light received by the photodiode 100 as follows. FIG. 3 is a timing chart of the operation of the solid-state imaging device of the present embodiment.
[0067]
Prior to the measurement of the amount of received light, the photodiode 100 is set in a state in which it does not receive light, the reset signal RST is temporarily made significant, the current holding instruction signal IH is made significant, and the current holding switch element 730 is closed. . As a result, dark current generated in the photodiode 100 is input to the integration circuit 220. When the dark current is input, a voltage signal corresponding to the dark current amount is output from the integration circuit 210, and this voltage signal is applied to the gate terminal of the FET 710 via the switch element 730. When applied to the gate terminal of the FET 710, dark current flows from the source of the FET 710 through the drain.
[0068]
Next, when the switch element 730 is opened, the voltage generated in the capacitor element 720 at that time is held, and thereafter, the dark current is removed from the input current to the charge amplifier 220.
[0069]
Next, the basic timing generation circuit 610 makes the reset signal RST significant, closes the switch element 223, removes the accumulated charge of the feedback capacitor element 221, and sets the count value output from the counter 510 to zero.
[0070]
Further, the binary sample circuit 400 is reset. As a result, the switch element 232 is closed.
[0071]
Next, the reset signal RST is made insignificant, and the amount of light received by the subsequent photodiodes is measured in synchronization with the clock signal CLK1 and the clock signal CLK2.
[0072]
In the solid-state imaging device of the present embodiment, when the photodiode 100 receives light, an electric charge corresponding to the amount of received light is generated and output as a current signal. This current signal is input to an integration circuit 220 including a feedback capacitive element 221 and a charge amplifier 222, and is accumulated and integrated.
[0073]
Here, the signal output terminal of the photodiode 100, the first terminal of the feedback capacitive element 221, and the signal input terminal of the charge amplifier 222 are directly electrically connected, and the current integration function itself is affected by the offset voltage. Since it is not inherently affected, the voltage value output as a result of the integration operation is not affected by the offset voltage at all.
[0074]
On the other hand, when the clock signal CLK1 supplied from the basic timing generation circuit 610 becomes significant, the step charge generator 230 closes the switch element 233 and the switch element 234, and the potentials at both ends of the step charge generation capacitive element 235 are set. Since it becomes the ground potential, the charge accumulated in the step charge generation capacitor element 235 becomes zero. When the clock signal CLK1 becomes insignificant and the clock signal CLK2 becomes significant after the switch element 233 and the switch element 234 are opened, the switch element 236 and the switch element 237 are closed. As a result, a step charge Q 21 corresponding to the reference potential −Vref is generated in the step charge generation capacitor element 235 and is given to the feedback capacitor element 221. here,
Q21 = C12 · (−Vref) (1)
It becomes.
[0075]
The charge Q21 and the charge Q11 that has flowed in from the photodiode 100 until the clock signal CLK1 becomes significant for the second time are accumulated in the feedback capacitive element 221, and according to the charge Q01 that is the sum of the charge Q21 and the charge Q11. ,
V11 = Q01 / C11
Is output when the clock signal CLK1 becomes significant for the second time.
[0076]
The potential V11 is input to the comparator 300 and compared with the zero potential. If V11> 0, the comparator 300 outputs “1” as the comparison result signal CMP and inputs it to the binary sample circuit 400. On the other hand, when V11 ≦ 0, the comparator 300 outputs “0” as the comparison result signal CMP and inputs it to the binary sample circuit 400.
[0077]
The binary sample circuit 400 samples the comparison result signal CMP when the clock signal CLK1 rises, and outputs a digital signal D1.
[0078]
The signal D1 is input to the step charge generation control circuit 460. The step charge generation control circuit 460 outputs the signal D1 as it is and outputs the inverted signal D1 *. That is, a pair of signals in which either one becomes significant is output. The pair of signals instructs to close the switches 231 and 232, respectively. That is, when the comparison result signal CMP is “0”, the inverted signal D1 * becomes significant, the reference potential −Vref becomes the reference potential for generating the step charge, and when the comparison result signal CMP is “1”, the signal D1 is It becomes significant, and the reference potential + Vref becomes the reference potential for generating the step charge.
[0079]
Hereinafter, the description will be continued assuming that V11> 0 when the clock signal CLK1 becomes significant for the second time.
[0080]
The signal D1 (= “1”) is input to the digital filter circuit 500. The counter 510 counts the clock signal CLK1, and weight data DWT for the signal D1 at this time is output from the data table 520. Multiplier 530 calculates the product of weighted data DWT and 1 which is the value of signal D1, and outputs product value signal D2 of the value of weighted data DWT as the product value. The product value signal D2 is input to the adder 540, calculates the sum of the product value and the previous addition result held in the holding circuit 550, and outputs it as a sum signal DS. Then, the calculation result is held in the holding circuit 550 and output as a signal D3.
[0081]
When the clock signal CLK1 becomes significant for the second time, the switch element 233 and the switch element 234 are closed, and the potentials at both ends of the step charge generation capacitor element 235 become the ground potential, so that they are stored in the step charge generation capacitor element 235. The charge is zero. When the first clock signal becomes insignificant and the clock signal CLK2 becomes significant after the switch element 233 and the switch element 234 are opened, the switch element 236 and the switch element 237 are closed. As a result, a step charge Q22 corresponding to the reference potential + Vref is generated in the step charge generation capacitor element 235 and is given to the feedback capacitor element 221. here,
Q22 = C12 · (+ Vref) (2)
It becomes.
[0082]
In addition to the charge Q01, the charge Q22 and the charge Q12 flowing from the photodiode 100 until the clock signal CLK1 becomes significant after the second time become significant are accumulated in the feedback capacitor 221. Depending on the total charge Q02 of
V12 = Q02 / C11
Is output when the clock signal CLK1 becomes significant for the third time.
[0083]
The signal D1 is input to the step charge generation control circuit 460. The step charge generation control circuit 460 outputs the signal D1 as it is and outputs the inverted signal D1 *.
[0084]
Hereinafter, the description will be continued assuming that V11 ≦ 0 when the clock signal CLK1 becomes significant for the third time.
[0085]
The signal D1 (= “0”) is input to the digital filter circuit 500. The counter 510 counts the clock signal CLK1, and weight data DWT for the signal D1 at this time is output from the data table 520. Multiplier 530 calculates the product of weighted data DWT and 0, which is the value of signal D1, and outputs a product value signal D2 having a value of 0 as the product value. The product value signal D2 is input to the adder 540, calculates the sum of the product value and the previous addition result held in the holding circuit 550, and outputs it as a sum signal DS. Then, the calculation result is held in the holding circuit 550 and output as a signal D3.
[0086]
Similarly, the current signal input from the photodiode 100 is ΣΔ modulated by the ΣΔ modulator 210 over a period corresponding to the desired resolution of the AD conversion result, and the modulation result is binarized by the comparator 300, and then 2 The digital filter circuit 500 applies digital filtering to the serial digital signal obtained by sampling with the value sample circuit and processes it to obtain an AD conversion result. In this way, an AD conversion result without the influence of the offset voltage is obtained.
[0087]
Note that the period corresponding to the desired resolution of the AD conversion result is 2 of the cycle of the clock signal CLK1 if N-bit resolution is desired.^NDouble time.
[0088]
Further, the capacitance value C11 and the capacitance value C12 are selected from the viewpoint of conversion accuracy and conversion speed according to the current range of the photodiode 100. The ratio between the capacitance value C11 and the capacitance value C12 is constant, different types of feedback capacitance elements and step charge generation capacitance elements are prepared in pairs, and a configuration that can be selected from these pairs is used. Is preferred.
[0089]
The above is an embodiment for a single photodiode, but a plurality of photodiodes may be arranged in a one-dimensional or two-dimensional manner. In this case, a photodiode selection circuit is newly provided and the above operation may be executed after selecting the photodiodes in a predetermined order or a random order. Alternatively, a plurality of photodiodes and AD conversion units described above may be arranged in parallel as a pair.
[0090]
(Second Embodiment)
FIG. 4 is a circuit configuration diagram of the second embodiment of the solid-state imaging device of the present invention. In this embodiment, AD conversion is performed by performing two-stage ΣΔ modulation. As shown in FIG. 4, the solid-state imaging device of the present embodiment includes (a) a photodiode whose ground is connected to the ground, generates a charge corresponding to the amount of received light, and flows out of the anode, and (b) a photodiode. 100, the current signal output from 100 is input, the charge that has flowed in is integrated, and the ΣΔ modulator 210 that performs ΣΔ modulation and (c) the modulation signal MS1 output from the ΣΔ modulator 210 are input and sampled The sample circuit 240, (d) integrating the sample signal output from the signal sample circuit 240 and performing ΣΔ modulation, ΣΔ modulator 251, (e) the potential of the modulation signal MS2 output from the ΣΔ modulator 251, and the ground A comparator 300 that compares the potential and outputs a binary comparison result signal CMP according to the comparison result; and (f) a comparison result signal CMP is input, and the clock CLK (G) the signal D1 is input, and the signal D1 and the inverted signal D1 * of the signal D1 are converted into the ΣΔ modulator 210 and the binary sampling circuit 400 that samples the signal D1 in synchronization with the signal D1. A step charge generation control circuit 470 that outputs to the ΣΔ modulator 251; (f) a digital filter circuit 500 that obtains an AD conversion result after inputting the digital signal D1 and applying digital filtering; and (g) a clock signal. CLK1 and a clock signal CLK2 that is insignificant at the significant level of the clock signal CLK1 and significant during a part of the insignificant level period of the clock signal CLK1 are generated, and the ΣΔ modulator 210, the signal sample circuit 240, The clock signal CLK1 and the clock signal CLK2 are output to the ΣΔ modulator 251 and the binary sampling times are output. Outputs the clock signal CLK1 towards 400, and a basic timing generating circuit 620 for outputting a reset signal.
[0091]
The configuration of the solid-state imaging device according to the present embodiment is different from the first embodiment in that a signal sample circuit 240 and a ΣΔ modulator 251 are further provided between the ΣΔ modulator 210 and the comparator 300.
[0092]
The signal sample circuit 240 includes (i) a switch element 241 that is connected to the output terminal of the ΣΔ modulator 210 and a first terminal and opens / closes in response to the clock signal CLK1, and (ii) a second terminal of the switch element 241. A signal transmission capacitive element 242 (capacitance value = C21) connected to the first terminal and connected to the input terminal of the ΣΔ modulator 251 and the second terminal is provided.
[0093]
The ΣΔ modulator 251 is synchronized with the clock signal CLK2 based on (i) an integration circuit 260 that accumulates and integrates the charge from the signal sampling circuit 240, and (ii) a reference potential + Vref and a reference potential −Vref. And a step charge generator 270 that generates step charges and supplies them to the integration circuit 260.
[0094]
The integration circuit 260 includes (i) a feedback capacitance circuit 261 to which the signal output terminal of the signal sampling circuit 240 and the first terminal are connected, and (ii) a negative input that is a signal output terminal and a signal input terminal of the signal sampling circuit 240. And a charge amplifier 262 having a positive input terminal connected to ground and a second terminal of the feedback capacitance circuit 261 connected to the output terminal.
[0095]
The feedback capacitance circuit 261 includes (i) a feedback capacitance element 263 (capacitance value = C22) in which the first terminal is connected to the signal input terminal of the charge amplifier 262, and (ii) a second terminal of the feedback capacitance element 263. A switch element 264 connected to the first terminal, the output terminal of the charge amplifier 262 connected to the second terminal, and opened and closed in response to the inverted signal CLK1 * of the clock signal CLK1 or the reset signal RST; and (iii) A first terminal is connected to the signal input terminal of the charge amplifier 262, a second terminal is connected to the output terminal of the charge amplifier 262, and a switch element 265 that opens and closes in response to the clock signal CLK1 or the reset signal is provided. .
[0096]
The step charge generator 270 includes (i) a switch element 271 that receives a reference potential + Vref from a first terminal and opens / closes in response to an output signal D1 from the binary sample circuit 400, and (ii) a reference potential −Vref. A switch element 272 that is input from the first terminal and opens and closes in response to an inverted signal D1 * of the output signal from the binary sampling circuit 400; and (iii) a second terminal of the switch element 271 and a second of the switch element 272 And the first terminal, the first terminal and the second terminal of the signal transmission capacitive element 242 are connected, and a switch element 273 that opens and closes in response to the clock signal CLK2 is provided.
[0097]
The solid-state imaging device of the present embodiment obtains digital data corresponding to the amount of light received by the photodiode 100 as follows. FIG. 5 is a timing chart of the operation of the solid-state imaging device of the present embodiment.
[0098]
Prior to the measurement of the amount of received light, in the same manner as in the first embodiment, after setting the dark current elimination circuit 700, the basic timing generation circuit 620 determines that the reset signal RST is significant, and the switch element 223, the switch element 264, and the switch element 265 is closed to remove the accumulated charges of the feedback capacitive element 221 and the feedback capacitive element 263, and the count value output from the counter 510 is set to zero.
[0099]
Further, the binary sample circuit 400 is reset. As a result, the switch element 232 is closed.
[0100]
Next, the reset signal RST is made insignificant, and the amount of light received by the subsequent photodiodes is measured in synchronization with the clock signal CLK1 and the clock signal CLK2.
[0101]
In the solid-state imaging device of the present embodiment, when the photodiode 100 receives light, an electric charge corresponding to the amount of received light is generated and output as a current signal. Then, as described in the first embodiment, this current signal is ΣΔ modulated by the ΣΔ modulator 210, and a modulated signal MS1 is output.
[0102]
Normally, in the one-stage ΣΔ modulation, a change in the output reference potential occurs due to current discharge of the photoelectric conversion element.
[0103]
The modulation signal MS1 is input to the signal sample circuit 240. The switch element 241 of the signal sample circuit 240 is closed when the clock signal CLK1 becomes significant, and charges Q31 corresponding to the potential value of the modulation signal MS1 are accumulated in the signal transmission capacitive element 242. While the clock signal CLK1 is significant, the switch element 265 is closed, and the input terminal and the output terminal of the charge amplifier 262 are short-circuited, but the switch element 264 is open, so that it is accumulated in the feedback capacitor element 263. The charge is stored as it is.
[0104]
When the clock signal CLK1 becomes insignificant, the inverted signal CLK1 * becomes significant, the switch element 241 and the switch element 265 are opened, and the switch element 264 is closed.
[0105]
Thereafter, when the clock signal CLK2 becomes significant, the switch element 273 is closed and a step charge Q32 is generated. When the signal D1 is “0”, the step charge Q32 is because the switch element 272 is closed and −Vref is selected.
Q32 = C21 · (−Vref) (3)
When the signal D1 is “1”, the switch element 271 is closed and + Vref is selected.
Q32 = C21 · (+ Vref) (4)
It is.
[0106]
In this way, the sum charge Q03 of the charge Q31 and the step charge Q32 is supplied to the feedback capacitor 263. In accordance with the charge Q04 that is the sum of the charge Q03 and the charge accumulated in the feedback capacitor 263 until then,
V21 = Q04 / C22
Is output as a modulation signal MS2.
[0107]
By the way, during the period when the modulation signal MS1 is sampled by the signal sampling circuit 240, that is, during the period when the clock signal CLK1 is significant, the switch element 265 is closed, and the input terminal and the output terminal of the charge amplifier 262 are short-circuited. An offset voltage is generated. However, since the switch element 264 is open during this period, the charge accumulated in the feedback capacitance element 263 is stored as it is. In addition, since the second terminal of the signal transmission capacitive element 242 remains connected to the input terminal of the charge amplifier 262, the offset voltage remains applied. Therefore, even if the switch element 265 is opened and then the switch element 264 is closed in response to the inverted signal CLK1 * and the state is changed to a state where charges are accumulated in the feedback capacitance element 263, the influence of the offset voltage does not appear. In this way, ΣΔ modulation having no offset effect is executed.
[0108]
The modulation signal MS2 output from the ΣΔ modulator 251 is input to the comparator 300, and thereafter, an AD conversion result is obtained without being affected by the offset voltage, as in the first embodiment.
[0109]
As in the first embodiment, the capacitance value C11 and the capacitance value C12 are selected from the viewpoint of conversion accuracy and conversion speed according to the current range of the photodiode 100. The ratio between the capacitance value C11 and the capacitance value C12 is constant, different types of feedback capacitance elements and step charge generation capacitance elements are prepared in pairs, and a configuration that can be selected from these pairs is used. Is preferred.
[0110]
The above is an embodiment in the case where there is one photodiode, but as in the first embodiment, a plurality of photodiodes may be arranged in a one-dimensional or two-dimensional manner. In this case, a photodiode selection circuit is newly provided and the above operation may be executed after selecting the photodiodes in a predetermined order or a random order. Alternatively, a plurality of photodiodes and AD conversion units described above may be arranged in parallel as a pair.
[0111]
In addition, when a plurality of solid-state imaging devices according to the present embodiment are arrayed into one chip, an output selection circuit is newly provided, and the output of each digital filter circuit is sequentially selected and read out. Moreover, it is suitable from the viewpoint of the circuit scale of the latter stage.
[0112]
(Third embodiment)
FIG. 6 is a circuit configuration diagram of a third embodiment of the solid-state imaging device of the present invention. In the present embodiment, as in the second embodiment, AD conversion is performed by performing two-stage ΣΔ modulation. As shown in FIG. 6, the solid-state imaging device of the present embodiment is different from the second embodiment in that a signal sample circuit 244 and a ΣΔ modulator 252 are used.
[0113]
The signal sample circuit 244 includes (i) a switch element 245 that is connected to the output terminal of the ΣΔ modulator 210 and a first terminal and opens / closes in response to the clock signal CLK1, and (ii) a second terminal of the switch element 245. (Iii) the second terminal of the signal transmission capacitive element 246 and the first terminal are connected, and the signal input terminal of the ΣΔ modulator 252 is connected to the second signal input terminal. And (iv) the first terminal is grounded, and the first terminal and the second terminal of the signal transmission capacitive element 246 are connected to each other. And (v) the first terminal is grounded, the second terminal and the second terminal of the signal transmission capacitive element 246 are connected, and the switch element 248 that opens and closes in response to the clock signal CLK2. The Tsu and a switch element 249 to be opened or closed in response to click signal CLK1.
[0114]
The ΣΔ modulator 252 includes (i) an integration circuit 280 that accumulates and integrates charges from the signal sample circuit 244, and (ii) a clock signal CLK1 and a clock signal CLK2 based on the reference potential + Vref and the reference potential −Vref. A step charge generator 290 that generates a step charge in synchronization with and supplies the step charge to the integration circuit 280.
[0115]
The integrating circuit 280 includes (i) a feedback capacitive element 281 (capacitance value = C23) to which the output terminal and the first terminal of the signal sampling circuit 244 are connected, and (ii) an output terminal and a signal input of the signal sampling circuit 244. A charge amplifier 282 having a negative input terminal as a terminal connected thereto, a positive input terminal grounded, and an output terminal connected to the second terminal of the feedback capacitive element 281, and (iii) an input terminal of the charge amplifier 282 And a first terminal, an output terminal of the charge amplifier 282 and a second terminal are connected, and a switching element 283 that opens and closes in response to a reset signal RST is provided.
[0116]
The step charge generator 290 has (i) a reference potential + Vref input from the first terminal, a switch element 291 that opens and closes in response to the signal D1, and (ii) a reference potential −Vref input from the first terminal. A switch element 292 that opens and closes in response to the inverted signal D1 *, (iii) a first terminal that is grounded, a switch element 293 that opens and closes in response to the clock signal CLK1, and (iv) a first terminal that is grounded. (V) a step in which the first terminal is connected to the second terminal of the switch element 293, and the second terminal is connected to the second terminal of the switch element 294; The charge generation capacitive element 295 (capacitance value = C24) and (vi) the first terminal and the first terminal of the step charge generation capacitive element 295 are connected, and the input terminal of the charge amplifier 282 and the second terminal And a switch element 296 that opens and closes in response to the clock signal CLK2, (vii) a second terminal of the switch element 291, and a second terminal of the switch element 292 and the first terminal are connected, A second terminal and a second terminal of the charge generation capacitive element 295 are connected, and a switch element 297 that opens and closes in response to the clock signal CLK2 is provided.
[0117]
That is, the ΣΔ modulator 210 and the ΣΔ modulator 252 are ΣΔ modulators having a similar circuit configuration, and are connected in series via the signal sample circuit 244 to perform second-order ΣΔ modulation.
[0118]
The solid-state imaging device of the present embodiment obtains digital data corresponding to the amount of light received by the photodiode 100 as follows. FIG. 7 is a timing chart of the operation of the solid-state imaging device of the present embodiment.
[0119]
Prior to the measurement of the amount of received light, after setting the dark current removal circuit 700, the basic timing generation circuit 610 makes the reset signal RST significant and closes the switch element 223 and the switch element 283, as in the first embodiment. The accumulated charge in the feedback capacitive element 221 and the feedback capacitive element 281 is removed, and the count value output from the counter 510 is set to zero.
[0120]
Further, the binary sample circuit 400 is reset. As a result, the switch element 232 is closed.
[0121]
Next, the reset signal RST is made insignificant, and the amount of light received by the subsequent photodiodes is measured in synchronization with the clock signal CLK1 and the clock signal CLK2.
[0122]
In the solid-state imaging device of the present embodiment, when the photodiode 100 receives light, an electric charge corresponding to the amount of received light is generated and output as a current signal. Then, as described in the first embodiment, this current signal is ΣΔ modulated by the ΣΔ modulator 210, and a modulated signal MS1 is output.
[0123]
The modulation signal MS1 is input to the signal sample circuit 244. The switch element 245 and the switch element 249 of the signal sample circuit 244 are closed when the clock signal CLK1 becomes significant, and charges Q41 corresponding to the potential value of the modulation signal MS1 are accumulated in the signal transmission capacitive element 246.
[0124]
When the clock signal CLK1 becomes significant, the switch element 293 and the switch element 294 are closed, and the charge of the step charge generation capacitor element 295 becomes zero.
[0125]
When the clock signal CLK1 becomes significant after the clock signal CLK1 becomes insignificant and the switch element 245 and the switch element 249 are opened, the switch element 247 and the switch element 248 are closed, and the charge Q41 is transmitted to the feedback capacitor element 281. Further, when the clock signal CLK1 becomes significant after the clock signal CLK1 becomes insignificant and the switch element 293 and the switch element 294 are opened, the switch element 296 and the switch element 297 are closed, and the step charge generation capacitor element 295 is supplied with the step charge. Q42 is generated. When the signal D1 is “0”, the step charge Q42 is because the switch element 292 is closed and −Vref is selected.
Q42 = C24 · (−Vref) (5)
When the signal D1 is “1”, the switch element 291 is closed and + Vref is selected.
Q42 = C24 · (+ Vref) (6)
It is.
[0126]
In this way, the sum charge Q05 of the charge Q41 and the step charge Q42 is supplied to the feedback capacitive element 281. According to the charge Q06 which is the sum of the charge Q05 and the charge accumulated in the feedback capacitor 281 until then,
V31 = Q06 / C23
Is output as a modulation signal MS2.
[0127]
By the way, during the period when the modulation signal MS1 is sampled by the signal sample circuit 244, that is, during the period when the clock signal CLK1 is significant, the signal sample circuit 244 closes the switch element 245 and the switch element 249 according to the clock signal CLK1. When the output signal MS1 of the ΣΔ modulator 210 is sampled, the second terminal of the signal transmission capacitive element 246 is grounded. In addition, after the switch element 245 and the switch element 249 are opened, the switch element 247 and the switch element 248 are closed according to the clock signal CLK2, and the charge transfer capacitance is transferred to the feedback capacitor element 281. The first terminal of the element 246 is grounded. Therefore, an offset voltage difference does not occur between sampling and charge transfer, and ΣΔ modulation that is not affected by the offset voltage is executed.
[0128]
The modulation signal MS2 output from the ΣΔ modulator 252 is input to the comparator 300, and thereafter, an AD conversion result is obtained without being affected by the offset voltage, as in the first embodiment.
[0129]
As in the first embodiment, the capacitance value C11 and the capacitance value C12 are selected from the viewpoint of conversion accuracy and conversion speed according to the current range of the photodiode 100. The ratio between the capacitance value C11 and the capacitance value C12 is constant, different types of feedback capacitance elements and step charge generation capacitance elements are prepared in pairs, and a configuration that can be selected from these pairs is used. Is preferred.
[0130]
The above is an embodiment in the case where there is one photodiode, but as in the first embodiment, a plurality of photodiodes may be arranged in a one-dimensional or two-dimensional manner. In this case, a photodiode selection circuit is newly provided and the above operation may be executed after selecting the photodiodes in a predetermined order or a random order. Alternatively, a plurality of photodiodes and AD conversion units described above may be arranged in parallel as a pair.
[0131]
When a plurality of solid-state imaging devices according to the present embodiment are arrayed into one chip, an output selection circuit is newly provided to sequentially select and read out the output of each digital filter circuit. This is preferable from the viewpoint of the number of pins and the circuit scale of the subsequent stage.
[0132]
In the above embodiment, the photodiode, the positive input terminal of the comparator, the positive input terminal of the charge amplifier, and the first terminals of the switch elements 233 and 234 are grounded, but the reference potential + Vref and the reference potential −Vref Any potential may be used.
[0133]
【The invention's effect】
As explained in detail above,The present inventionAccording to the solid-state imaging device, while the dark current of the photoelectric conversion element is removed, the current is input to the ΣΔ modulator, and the current signal from the photoelectric conversion element such as a photodiode is directly input as it is. Therefore, high-precision digital data can be obtained according to the amount of light received by the photoelectric conversion element with a simple circuit configuration suitable for integration without the influence of the offset voltage in the ΣΔ modulator. Can do.
[0134]
Also,The present inventionAccording to the solid-state imaging device, since the ΣΔ modulator is arranged in two stages in series and the second-order ΣΔ modulation is performed, the performance of the first-stage ΣΔ modulator cannot be removed. It is possible to eliminate the cause of the accuracy reduction derived from the characteristics of the conversion element, and high-accuracy digital data can be obtained according to the amount of light received by the photoelectric conversion element.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a solid-state imaging element according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a digital filter circuit.
FIG. 3 is a timing chart of the operation of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 4 is a configuration diagram of a solid-state imaging device according to a second embodiment of the present invention.
FIG. 5 is a timing chart of the operation of the solid-state imaging device according to the second embodiment of the present invention.
FIG. 6 is a configuration diagram of a solid-state imaging element according to a third embodiment of the present invention.
FIG. 7 is a timing chart of the operation of the solid-state imaging device according to the third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Photodiode, 210, 251, 252 ... Sigma-delta modulator, 220, 260, 280 ... Integration circuit, 221, 263, 281 ... Feedback capacitance element, 222, 262, 282 ... Charge amplifier, 223, 264, 265, 283 ... Switch element, 261 ... Feedback capacitance circuit, 230,270,290 ... Step charge generator, 231,232,233,234,236,237,271,272,273,291,292,293,294,296,297 ... switch elements, 235, 295 ... capacitance elements for generating step charges, 240,244 ... signal sampling circuits, 241,245,247,248,249 ... switch elements, 242,246 ... capacitance elements for signal transmission, 300 ... comparators , 400 ... Binary sampling circuit, 460, 470 ... Step charge generation control circuit, 500 ... Digital filter circuit, 510 ... Counter, 520 ... Data table, 530 ... Multiplier, 540 ... Adder, 550 ... Holding circuit, 610,620 ... Basic timing generation circuit, 700 ... Dark current elimination circuit.

Claims (13)

The first terminal is set at a third reference potential between the first reference potential and the second reference potential, generates charges according to the amount of received light, and flows out charges from the second terminal, at least One photoelectric conversion element;
A dark current removing circuit for removing dark current of the photoelectric conversion element;
A first feedback capacitive element in which a second terminal and a first terminal of the photoelectric conversion element are directly electrically connected;
A first charge amplifier in which a second terminal and an input terminal of the photoelectric conversion element are directly electrically connected and an output terminal is connected to a second terminal of the first feedback capacitance element;
A first step charge generator that generates a step charge from the first reference potential and the second reference potential and supplies the step charge to the first feedback capacitor;
The first integrated voltage signal output from the first charge amplifier is input, the potential of the first integrated voltage signal is compared with the third reference potential, and a comparison result signal corresponding to the comparison result is obtained. An output potential comparator;
A binary sample circuit that inputs the comparison result signal and binary samples the comparison result signal;
Generating a first clock signal and a second clock signal that is insignificant when the first clock signal is insignificant and becomes significant during part of the insignificant level period of the first clock signal And outputting the first clock signal and the second clock signal to the first step charge generator, and outputting the first clock signal to the binary sample circuit. A timing generation circuit,
The dark current elimination circuit is
A field effect transistor having a source terminal connected to the signal input terminal of the first charge amplifier and a drain terminal set to the third reference potential; and a gate terminal and a first terminal of the field effect transistor A dark current storage capacitor element having a second terminal set to the third reference potential, and a first terminal and a first terminal of the dark current storage capacitor element connected to each other; A solid-state imaging device comprising: a current holding switch element connected to the output terminal of the charge amplifier and the second terminal . The output signal from the binary sampling circuit is input, and the output signal from the binary sampling circuit and the inverted signal of the output signal from the binary sampling circuit are used as the step charge generation instruction to generate the first step charge generator. The solid-state imaging device according to claim 1, further comprising a first step charge generation control circuit that outputs the output toward The first step charge generator is
A first switch element that receives the first reference potential from a first terminal and opens and closes in response to an output signal from the binary sampling circuit;
A second switch element that receives the second reference potential from a first terminal and opens and closes in response to an inverted signal of an output signal from the binary sampling circuit;
A third switch element that receives the third reference potential from a first terminal and opens and closes in response to the first clock signal;
A fourth switch element that receives the third reference potential from a first terminal and opens and closes in response to the first clock signal;
A first step charge generation capacitive element having a first terminal connected to the second terminal of the third switch element and a second terminal connected to the second terminal of the fourth switch element; ,
A first terminal and a first terminal of the first step charge generation capacitive element are connected, an input terminal and a second terminal of the first charge amplifier are connected, and the second clock signal A fifth switch element that opens and closes in response to
The second terminal of the first switch element, the second terminal of the second switch element, and the first terminal are connected, and the second terminal of the first step charge generation capacitor element and the second terminal And a sixth switch element that opens and closes in response to the second clock signal;
The solid-state imaging device according to claim 2, further comprising: Between the first charge amplifier and the potential comparator,
A signal sampling circuit that samples the first integration signal at an instructed timing and outputs an AC component;
A feedback capacitance circuit having a second feedback capacitance element that inputs a signal output from the signal sample circuit from a first terminal;
A second charge amplifier in which a signal output from the signal sampling circuit is input from an input terminal, and an output terminal is connected to the feedback capacitance circuit;
The potential comparator further includes a second step charge generator that generates a step charge from the first reference potential and the second reference potential and supplies the step charge to the second feedback capacitance element. The solid-state imaging device according to claim 1, wherein the second integration signal output from the second charge amplifier is input. An output signal from the binary sample circuit is input, and the first step charge generation is performed using the output signal from the binary sample circuit and an inverted signal of the output signal from the binary sample circuit as a step charge generation instruction. The solid-state imaging device according to claim 4 , further comprising a second step charge generation control circuit that outputs to a second step charge generator. The signal sample circuit includes:
A seventh switch element connected between the output terminal of the first charge amplifier and the first terminal, and opened and closed according to the first clock signal;
A signal transmission capacitive element in which a second terminal and a first terminal of the seventh switch element are connected, and an input terminal and a second terminal of the second charge amplifier are connected;
The solid-state imaging device according to claim 5, further comprising: The second step charge generator is
An eighth switch element that inputs the first reference potential from a first terminal and opens and closes in response to an output signal from the binary sample circuit;
A ninth switch element that inputs the second reference potential from a first terminal and opens and closes in response to an inverted signal of an output signal from the binary sampling circuit;
The second terminal of the eighth switch element and the second terminal of the ninth switch element are connected to the first terminal, and the first terminal and the second terminal of the signal transmission capacitive element are connected to each other. A tenth switching element that opens and closes in response to the second clock signal;
With
The feedback capacitance circuit is
The second feedback capacitive element having a first terminal connected to a signal input terminal of the second charge amplifier;
A second terminal and a first terminal of the second feedback capacitive element are connected, an output terminal and a second terminal of the second charge amplifier are connected, and an inverted signal of the first clock signal An eleventh switch element that opens and closes in response to
The first terminal is connected to the signal input terminal of the second charge amplifier, the second terminal is connected to the output terminal of the second charge amplifier, and opens and closes according to the first clock signal. A twelfth switch element;
The solid-state imaging device according to claim 6, further comprising: The signal sample circuit includes:
A thirteenth switch element connected between the output terminal of the first charge amplifier and the first terminal, and opened and closed according to the first clock signal;
A capacitive element for signal transmission in which the second terminal and the first terminal of the thirteenth switch element are connected;
A second terminal and a first terminal of the signal transmission capacitive element are connected, a second terminal is connected to a signal input terminal of the second charge amplifier, and according to the second clock signal A fourteenth switch element that opens and closes;
The third reference potential is inputted from the first terminal, and the first terminal and the second terminal of the signal transmission capacitive element are connected, and the fifteenth is opened and closed according to the second clock signal. Switch elements of
The third reference potential is inputted from the first terminal, and the second terminal and the second terminal of the signal transmission capacitive element are connected, and the sixteenth is opened and closed according to the first clock signal. Switch elements of
The solid-state imaging device according to claim 5, further comprising: The second step charge generator is
A seventeenth switching element that inputs the first reference potential from a first terminal and opens and closes in response to an output signal from the binary sampling circuit;
An eighteenth switching element that inputs the second reference potential from a first terminal and opens and closes in response to an inverted signal of the output signal from the binary sampling circuit;
A nineteenth switch element that inputs the third reference potential from a first terminal and opens and closes in response to the first clock signal;
A twentieth switch element that receives the third reference potential from a first terminal and opens and closes in response to the first clock signal;
A second step charge generation capacitive element having a first terminal connected to a second terminal of the nineteenth switch element and a second terminal connected to a second terminal of the twentieth switch element; ,
A first terminal and a first terminal of the second step charge generation capacitive element are connected, an input terminal and a second terminal of the second charge amplifier are connected, and the second clock signal A twenty-first switching element that opens and closes in response to
The second terminal of the seventeenth switch element, the second terminal of the eighteenth switch element and the first terminal are connected, and the second terminal of the second step charge generation capacitor element and the second terminal And a 22nd switch element that opens and closes in response to the second clock signal,
With
The feedback capacitance circuit includes a second feedback capacitance element in which a first terminal is connected to a signal input terminal of the second charge amplifier, and a second terminal is connected to an output terminal of the second charge amplifier. The solid-state imaging device according to claim 8, comprising: 2. The solid-state imaging device according to claim 1, further comprising a digital filter circuit that inputs a digital data signal sequence output from the binary sampling circuit and outputs a digital signal subjected to digital filtering. . The capacitance value of the first feedback capacitance element and the capacitance value of the first step charge generation capacitance element are selected according to a time change characteristic of an output current of the photoelectric conversion element. The solid-state imaging device according to claim 1. A plurality of photoelectric conversion elements arranged in a one-dimensional or two-dimensional manner, and a selection circuit for selecting one photoelectric conversion element connected to the first terminal of the first feedback capacitance element; The solid-state imaging device according to claim 1, further comprising: The solid-state imaging device according to claim 12 , wherein the selection circuit selects the photoelectric conversion elements in one of a predetermined order and a random order.

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