JP3846345B2 - High frequency semiconductor integrated circuit module - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-layered semiconductor integrated circuit chip for high frequency / high power application formed on a compound semiconductor substrate such as GaAs or InP and a module structure including the mounting substrate.
[0002]
[Prior art]
FIG. 4 is a diagram showing the structure of a conventional multilayer wiring semiconductor integrated circuit module 1. In the multilayer wiring semiconductor integrated circuit chip 2, functional elements such as transistors, resistors, capacitors, etc. (not shown) are formed on a semiconductor substrate 3 such as GaAs or InP, and a protective film is formed on the electrode portion of each functional element. An opening is formed. Further, the multilayer wiring semiconductor integrated circuit chip 2 connects the electrode opening 12 of the transistor, the electrode opening 13 of the resistor, the electrode opening 14 of the capacitor, etc. with the wiring 15 and the contact hole 16 using the interlayer insulating film 4 having a low dielectric constant. A multi-layered wiring structure is provided, and power is supplied and signals are input / output by terminal electrodes 7 provided in the peripheral portion of the uppermost layer. Further, a ground plate 8 is provided at the center of the uppermost layer in order to eliminate radio noise from the outside, suppress generation of radio noise from the inside, and stabilize the frequency characteristics with respect to the operation of the multilayer wiring semiconductor integrated circuit chip 2. Is provided. The multilayer wiring semiconductor integrated circuit chip 2 formed in this way is flip-chip connected to the mounting substrate 5 with gold pillars (or bumps or the like) 9, and in order to improve impact resistance, an adhesive resin 6 is placed in the gap. To be fixed.
[0003]
FIG. 5 is a plan view of the multilayer wiring semiconductor integrated circuit chip 2 constituting the multilayer wiring semiconductor integrated circuit module 1 shown in FIG. 4 as viewed from the uppermost layer side of the interlayer insulating film 4. A cross section along line AA 'is shown in FIG. An inner region surrounded by a dotted line is an active region 17 in which functional elements such as transistors, resistors, and capacitors are formed on the semiconductor substrate 3.
[0004]
[Problems to be solved by the invention]
In the multilayer wiring semiconductor integrated circuit module 1 having the conventional structure, the heat generated in the multilayer wiring semiconductor circuit chip 2 can be released only through the gold pillars 9, so that it cannot be applied to a high output semiconductor integrated circuit that generates a large amount of heat. . Therefore, improvement of heat dissipation of the multilayer wiring semiconductor integrated circuit module is a first problem.
[0005]
Further, the resin 6 and the interlayer insulating film 4 are water permeable or water absorbing, and when the humidity in the surrounding environment of the semiconductor integrated circuit module 1 is high, moisture reaches the active region 17 shown in FIG. It becomes. Therefore, improvement of moisture resistance for the resin 6 and the interlayer insulating film 4 is a second problem.
[0006]
[Means for Solving the Problems]
FIG. 1 shows a multilayer wiring semiconductor integrated circuit module 1 according to the present invention, and shows a cross-sectional structure taken along line AA ′ of the surface pattern of the multilayer wiring semiconductor integrated circuit chip 2 of FIG. The names and numbers of the respective parts are the same as those in FIG. 4 showing the cross section of the conventional multilayer wiring semiconductor integrated circuit module 1 and FIG. 5 showing the surface pattern of the multilayer wiring semiconductor integrated circuit chip 2. In the figure, 11 is a shield plate provided on the mounting substrate 5, and has the same pattern as the ground plate 8. Reference numeral 18 denotes a metal region formed in each layer of an interlayer insulating film having a pattern surrounding the outer periphery of the ground plate 8 and the terminal electrode 7.
[0007]
In order to improve heat dissipation, which is the first problem, it is necessary to shorten the heat path and increase the heat dissipation area. Therefore, in addition to dissipating heat by heat conduction by the metal of the wiring 15, the ground plate 8 is taken as large as possible and directly connected to the mounting substrate 5 by thermocompression bonding or soldering without using pillars or bumps. Also do heat dissipation. At this time, with respect to impact resistance when the module is dropped, the space between the multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5 is filled with an adhesive resin 6, and the side surface of the multilayer wiring semiconductor integrated circuit chip is covered with the resin 6. The method realized by covering with and fixing them together is used.
[0008]
In order to improve the moisture resistance, which is the second problem, the resin 6 and the interlayer insulating film 4 have water permeability or water absorption, and therefore, it is necessary to reduce the cross-sectional area of the path through which moisture enters. As shown in FIG. 4, there are two paths through which moisture around the multilayer wiring semiconductor integrated circuit chip 2 reaches the active region 17 of the multilayer wiring semiconductor integrated circuit chip 2. The first moisture intrusion path a vertically cuts the interlayer insulating film 4 through an adhesive resin layer provided in the gap between the multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5. The second moisture intrusion path b enters from the resin around the multilayer wiring semiconductor integrated circuit chip 2 and crosses the interlayer insulating film 4. In order to directly connect the terminal electrode 7 of the multilayer wiring semiconductor integrated circuit chip 2 and the wiring 10 of the mounting substrate to the first moisture intrusion path a, there is no pillar 9 shown in the conventional structure. By narrowing the vertical direction and by narrowing the horizontal direction because it is limited by the distance between the terminal electrode 7 and the ground plate 8 as compared to the pillar interval of the conventional structure, the first moisture intrusion path is greatly interrupted. The area becomes smaller. Further, the path of the small cross-sectional area becomes longer due to the terminal electrode 7 having a depth with respect to the direction of the path.
[0009]
For the second moisture intrusion path b, the metal region 18 formed in a pattern surrounding the outer periphery of the ground plate 8 and the terminal electrode 7 is arranged for each layer of the multilayer film, so that the path cross section in the lateral direction can be obtained. It can be limited to approximately 1 / (number of layers).
[0010]
DETAILED DESCRIPTION OF THE INVENTION
(First Example) The first embodiment of the present invention will be described below in detail with reference to the drawings.
FIG. 3 is a diagram showing a manufacturing process for one layer of multilayer wiring. The numbers in the figure are the same as those shown in FIGS. 1 and 2, and 20 is a resist layer and 21 is a plating seed metal layer. In this process, transistors, resistors, capacitors (not shown) are formed on a semiconductor substrate 3 such as GaAs or InP, and a passivation film such as a nitride film (not shown) is further formed. In order to function as, it is necessary to connect the functional elements. For this purpose, the multilayer wiring process is started from a state in which contact connection openings such as the transistor terminal 12, the resistance terminal 13, and the capacitor terminal 14 are formed.
[0011]
(1) 2 μm of polyimide is applied by spin coating, and cured at 350 ° C. for 40 minutes.
(2) A resist is applied to form a wiring 15 pattern and a metal region 18 pattern.
(3) Dry etching is performed using oxygen as an etching gas to form a contact hole 16 pattern and a metal region 18 contact hole pattern in polyimide.
[0012]
(4) Deposit 0.2 μm of TiW / Au by sputtering to form a plating seed metal layer 21.
(5) A resist is applied again, and a pattern of the wiring 15 and a pattern of the metal region 18 are formed.
(6) 1 μm of gold is deposited on the plating seed metal layer 21 in the resist opening of the pattern by gold plating.
[0013]
(7) The resist and the unnecessary plating seed metal layer 21 are removed by a milling method.
The above steps (1) to (7) are repeated to form a multilayer of about 4 to 5 layers. Finally,
(8) As the uppermost layer of the multilayer wiring, the gold-plated terminal electrode 7 and the ground plate 8 are formed by the steps (1) to (7). The thickness of the gold plating is 2 μm thicker than the other layers to facilitate thermocompression bonding. Here, in order to avoid a short circuit with the wiring of the mounting board, the metal region 18 is not provided in this layer.
[0014]
As shown in FIG. 3, since the pattern of the contact hole 16 and the pattern of the contact hole of the metal region 18 are formed at the same time, providing the metal region 18 does not increase the amount of work.
The multilayer wiring semiconductor integrated circuit chip 2 manufactured as described above is connected to the mounting substrate 5 patterned by gold plating by thermocompression bonding. Thereafter, the gap between the multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5 and the side surface of the multilayer wiring semiconductor integrated circuit chip 2 are filled with the resin using, for example, an epoxy adhesive resin 6.
(Second Embodiment) In addition to joining the multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5 by thermocompression bonding, both may be joined by solder joining.
[0015]
In that case, after forming the uppermost layer of the multilayer wiring semiconductor integrated circuit chip 2, Ni is used as a barrier metal, and a solder layer is deposited and patterned by 1 μm. Provide.
The multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5 are aligned and solder-connected in an inert gas atmosphere (for example, nitrogen gas) while maintaining the solder melting temperature or higher (for example, 200 ° C.). Thereafter, the gap between the multilayer wiring semiconductor integrated circuit chip 2 and the mounting substrate 5 and the side surface of the multilayer wiring semiconductor integrated circuit chip 2 are filled with the resin using, for example, an epoxy adhesive resin.
[0016]
In the first embodiment, polyimide is used as the interlayer insulating film. However, for example, BCB (benzocyclobutene) may be used which is easy to obtain flatness on the uneven surface.
[0017]
【The invention's effect】
According to the present invention, compared to the conventional structure, the electrodes are connected to each other without using a pillar to shorten the heat path, and the interlayer insulating film and the mounting substrate are directly connected to improve heat dissipation, so that the moisture content is reduced. By reducing the path through the resin layer, the moisture resistance is improved, and the chip and the mounting substrate are fixed with an adhesive resin to realize a shock-resistant multilayer wiring semiconductor integrated circuit module.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross section of a multilayer wiring semiconductor integrated circuit module according to the present invention. FIG. 2 is a diagram illustrating a surface pattern of a multilayer wiring semiconductor integrated circuit chip according to the present invention. 4 is a diagram showing a cross section of a conventional multilayer wiring semiconductor integrated circuit module. FIG. 5 is a diagram showing a surface pattern of a conventional multilayer wiring semiconductor integrated circuit chip.
DESCRIPTION OF SYMBOLS 1 Multilayer wiring semiconductor integrated circuit module 2 Multilayer wiring semiconductor integrated circuit chip 3 Semiconductor substrate 4 Interlayer insulation film 5 Mounting substrate 6 Resin 7 Terminal electrode 8 Ground plate 9 Pillar 10 Substrate wiring 11 Shield plate 12 Substrate terminal 13 Resistance terminal 14 Capacitor Terminal 15 Wiring 16 Contact hole 17 Active region 18 Metal region 20 Resist layer 21 Plating seed metal layer a First moisture intrusion path b Second moisture intrusion path

Claims (1)

At least, has a multi-layer wiring semiconductor integrated circuit chip which is wire connected to the multilayer between formed on the semiconductor substrate element through the layer insulating film, and a mounting board,
The multilayer wiring semiconductor integrated circuit chip chip electrodes formed on the uppermost layer of said at chip electrodes formed on the surface layer of the mounting board in a position opposite the mounting substrate electrode, directly without using a connection projection To, thermocompression bonding or solder connection,
Wherein the multilayer wiring semiconductor integrated circuit chip at least a portion of the top layer is covered with the ground plate of metal, metal walls forming a pattern so as to surround the outer periphery of the tip electrode and said ground plate region, except for the top layer Are formed upright from the wiring layer in the interlayer insulating film,
A shield plate having substantially the same pattern as the ground plate is provided on the surface layer of the mounting substrate.
An adhesive resin is filled between the multilayer wiring semiconductor integrated circuit chip and the mounting substrate,
And the side surface of the said multilayer wiring semiconductor integrated circuit chip is coat | covered with the said adhesive resin. The high frequency semiconductor integrated circuit module characterized by the above-mentioned.

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