JP3846651B2 - Ceramic circuit board - Google Patents

Description

【００２３】
この表１においてガラス粉末の各成分（ＣａＯ，Ａｌ₂ Ｏ₃ ，ＳｉＯ₂ ，Ｂ₂ Ｏ₃ ）の重量比は、低温焼成セラミックに対する重量比で表されている。
組成Ａは、ＣａＯ−Ａｌ₂ Ｏ₃ −ＳｉＯ₂ −Ｂ₂ Ｏ₃ 系ガラス粉末６０重量％とＡｌ₂ Ｏ₃ 粉末４０重量％との混合物であり、熱膨張係数は５．５×１０^-6／ｄｅｇである。
【００２４】
組成Ｂは、ＣａＯ−Ａｌ₂ Ｏ₃ −ＳｉＯ₂ −Ｂ₂ Ｏ₃ 系ガラス粉末５５重量％とＡｌ₂ Ｏ₃ 粉末４５重量％との混合物であり、熱膨張係数は５．７×１０^-6／ｄｅｇである。
【００２５】
組成Ｃは、ＣａＯ−Ａｌ₂ Ｏ₃ −ＳｉＯ₂ −Ｂ₂ Ｏ₃ 系ガラス粉末６５重量％とＡｌ₂ Ｏ₃ 粉末３５重量％との混合物であり、熱膨張係数は５．２×１０^-6／ｄｅｇである。
これらの組成Ａ，Ｂ，Ｃの低温焼成セラミックの熱膨張係数は、アルミナ基板の熱膨張係数（７．０×１０^-6／ｄｅｇ）と比較すれば、いずれも小さい。
【００２６】
更に、本発明者は、セラミック層１６を形成する低温焼成セラミック材料の組成と熱膨張係数との関係を評価する試験を行ったので、その試験結果を次の表２に示す。
【００２７】
【表２】

【００２８】
この表２は、前記表１の各組成Ａ，Ｂ，Ｃの低温焼成セラミックにＢｉ₂ Ｏ₃ を添加した場合、Ｂｉ₂ Ｏ₃ の添加量によって熱膨張係数がどの程度変化するかを測定したものである。この測定結果から、Ｂｉ₂ Ｏ₃ の添加量が外掛けで０．５〜１５重量％であれば、いずれの組成でも、熱膨張係数が５．０×１０^-6／ｄｅｇ以下となり、Ｂｉ₂ Ｏ₃ を含まない低温焼成セラミックよりも熱膨張係数が小さくなる。
【００２９】
本発明者は、低温焼成セラミック基板１１のセラミック層１６に実装する半導体チップ１５の接合信頼性を評価するために、前記組成Ａの低温焼成セラミックにＢｉ₂ Ｏ₃ を添加して作ったペーストで低温焼成セラミック基板１１の表層にセラミック層１６を印刷し、これを焼成した後、このセラミック層１６上に半導体チップ１５をＡｇエポキシ１９で実装して、温度サイクル試験（−５５℃３０分／＋１５０℃３０分：１００サイクル）を行い、チップ接合部の故障率を測定したので、その測定結果を次の表３に示す。
【００３０】
【表３】

【００３１】
この表３の試験結果から明らかなように、Ｂｉ₂ Ｏ₃ の添加量が０重量％（セラミック層１６が無い場合と実質的に同じ）の場合には、故障率が０．５％であるが、Ｂｉ₂ Ｏ₃ の添加量が外掛けで０．５〜１５重量％であれば、熱膨張係数が４．９×１０^-6／ｄｅｇ以下となり、半導体チップ１５（Ｓｉ）の熱膨張係数（３．５×１０^-6／ｄｅｇ）に近くなるため、故障率が０％であり、極めて高い接合信頼性が得られる。Ｂｉ₂ Ｏ₃ の添加量が外掛けで２０重量％以上になるとＳｉとの熱膨張係数の差が大きくなるため、故障率が０．２％以上となり、接合信頼性が低下する。従って、十分な接合信頼性を確保するには、Ｂｉ₂ Ｏ₃ の添加量を外掛けで０．５〜１５重量％の範囲内に設定することが好ましい。この場合、セラミック層１６とＳｉとの熱膨張係数の差が１．２〜１．４×１０^-6／ｄｅｇであるが、この程度の差であれば、チップ接合部（Ａｇエポキシ１９）の弾性によって残留応力や熱応力を十分に緩和でき、故障率を０％に維持できる。
【００３２】
ところで、低温焼成セラミック基板１１とセラミック層１６との熱膨張係数の差が大きいと、焼成時の応力によって低温焼成セラミック基板１１が反ったり、セラミック層１６が剥がれてしまうおそれがある。
【００３３】
上述したように、Ｂｉ₂ Ｏ₃ の添加量を外掛けで０．５〜１５重量％の範囲内に設定すると、セラミック層１６の熱膨張係数が４．６〜５．０×１０^-6／ｄｅｇ（表２参照）となり、セラミック層１６と低温焼成セラミック基板１１との熱膨張係数の差が０．９×１０^-6／ｄｅｇ以下となる。この程度の熱膨張係数の差であれば、焼成時のＢｉ₂ Ｏ₃ の拡散によってセラミック層１６の周辺に中間的な熱膨張係数のセラミックを形成することで、焼成時の応力を十分に緩和でき、低温焼成セラミック基板１１の反りやセラミック層１６の剥がれを十分に抑えることができる。一般には、セラミック層１６と低温焼成セラミック基板１１との熱膨張係数の差が１．５×１０^-6／ｄｅｇ以下であれば、低温焼成セラミック基板１１の反りやセラミック層１６の剥がれを十分に抑えることができる。
【００３４】
次に、表層抵抗体１８の信頼性について考察する。一般に、焼成後の表層抵抗体１８は、抵抗値がばらついているので、焼成後に表層抵抗体１８をレーザトリミング法等でトリミングして抵抗値を調整するようにしているが、トリミング時の熱歪により表層抵抗体１８にマイクロクラックが入ることがあり、このマイクロクラックが実使用環境下で徐々に進行して抵抗値が経時変化し、回路の信頼性を低下させるおそれがある。このマイクロクラックの進行は、表層抵抗体１８に引張応力が作用している状態で発生しやすい。従って、マイクロクラックの進行を防ぐには、表層抵抗体１８に圧縮力が加わるように、低温焼成セラミック基板１１の熱膨張係数＞表層抵抗体１８の熱膨張係数の関係に設定することが望ましい。
【００３５】
一般に、表層抵抗体１８を形成するＲｕＯ₂ 系抵抗体ペーストは、ＲｕＯ₂ 粉末（熱膨張係数：６．０×１０^-6／ｄｅｇ）とガラス粉末との混合物であるため、熱膨張係数の小さいガラス粉末を使用しても、表層抵抗体１８の熱膨張係数を５．０×１０^-6／ｄｅｇより小さくするのは困難である。従って、表層抵抗体１８を形成する部分のセラミックは、５．０×１０^-6／ｄｅｇ以上の熱膨張係数が望ましい。この観点から、上記実施形態では、低温焼成セラミック基板１１の表面に表層抵抗体１８を形成している。
【００３６】
尚、Ｂｉ₂ Ｏ₃ を含むセラミック層１６の熱膨張係数の影響を受けないように、表層抵抗体１８はセラミック層１６より０．５ｍｍ以上（好ましくは１ｍｍ以上）の距離をおくのが良い。
【００３７】
本発明者は、この表層抵抗体１８の信頼性を評価するために、次のような試験を行った。図２に示すように、低温焼成セラミック基板２１（熱膨張係数：５．５×１０^-6／ｄｅｇ）の表面に、抵抗体電極用のＡｇ導体２２を２ｍｍ間隔で印刷・焼成し、更に、その上から、熱膨張係数が５．３×１０^-6／ｄｅｇの表層抵抗体２３（幅１ｍｍ）を印刷・焼成した。この後、表層抵抗体２３をレーザトリミングして、その抵抗値を初期値の２倍の値に調整した後、温度サイクル試験（−５５℃３０分／＋１５０℃３０分：１００サイクル）を行い、表層抵抗体２３の抵抗値の変化率を測定した。この測定をサンプル数１００個について行ったところ、次の表４の結果が得られた。
【００３８】
【表４】

【００３９】
この試験で測定された表層抵抗体２３の抵抗値の変化率は、最大値でも０．２３％と小さく、要求値（１％以内）を十分に満たす。従って、低温焼成セラミック基板２１の表面に部分的に異なる熱膨張係数のセラミック層が存在していても、表層抵抗体２３の信頼性に全く影響を及ぼさない。
【００４０】
尚、本実施形態（図１）では、低温焼成セラミック基板１１の表面にセラミック層１６を印刷したが、セラミック層１６と同じ組成の材料で形成したグリーンシートを積層しても良い。
【００４１】
［第２の実施形態］
上記第１の実施形態では、低温焼成セラミック基板１１の表面にセラミック層１６を印刷したが、図３に示す第２の実施形態では、表層のグリーンシート１２のうちの半導体チップ１５を搭載する部位に開口部２５を形成し、この開口部２５に、低温焼成セラミック基板１１と半導体チップ１５との中間的な熱膨張係数のセラミック層２６を充填して焼成し、このセラミック層２６上に半導体チップ１５を実装する。セラミック層２６は、前記第１の実施形態と同じ組成であり、そのペーストを印刷して形成しても良いし、後述する第３の実施形態で用いるグリーンシートを所定寸法に切断して開口部２５に嵌め込んでも良い。これ以外の構成は、前述した第１の実施形態と同じであるので、同一符号を付して説明を省略する。
【００４２】
尚、上記第１及び第２の実施形態では、表層抵抗体１８を形成しているが、これを省いた構成としても良いことは言うまでもない。また、１枚の低温焼成セラミック基板１１について複数箇所にセラミック層１６，２６を形成しても良く、また、１箇所のセラミック層１６，２６に複数個のフリップチップを実装するようにしても良い。
【００４３】
［第３の実施形態］
上記第１及び第２の実施形態では、低温焼成セラミック基板１１の表面の一部のみにセラミック層１６，２６を形成したが、図４に示す第３の実施形態では、低温焼成セラミック基板１１の最上層（表層）に、低温焼成セラミック基板１１と半導体チップ１５との中間的な熱膨張係数のグリーンシート２７を“セラミック層”として積層することで、低温焼成セラミック基板１１の表面全面に熱膨張係数の異なるセラミック層２７を形成している。このセラミック層２７の組成は前記第１の実施形態と同じである。セラミック層２７を形成するグリーンシートは、Ｂｉ₂ Ｏ₃ を外掛けで０．５〜１５重量％含む低温焼成セラミック材料に、バインダー樹脂、溶剤及び可塑剤を加えて作製したスラリーをテープ成形したものであり、バインダー樹脂としては、アクリル樹脂又はポリビニルブチラールを用いれば良い。
【００４４】
この第３の実施形態では、熱膨張係数の異なる２種類のグリーンシート１２，２７を積層して焼成するため、通常の焼成方法では、低温焼成セラミック基板１１が反ったり、セラミック層２７が剥がれてしまうおそれがある。この対策として、グリーンシート１２，２７の積層体を加圧しながら焼成すれば良い。この加圧焼成により、低温焼成セラミック基板１１の反りやセラミック層２７の剥がれを防止できる。
【００４５】
尚、この第３の実施形態は、基板表面に表層抵抗体を設けない回路基板に適用することが好ましい。表層抵抗体を設けると、基板表面の熱膨張係数＜表層抵抗体の熱膨張係数の関係となり、表層抵抗体に引張応力が作用して表層抵抗体にマイクロクラックが発生しやすくなり、表層抵抗体の抵抗値の変化率が大きくなるためである。
【００４７】
また、本発明のセラミック回路基板は、低温焼成セラミック回路基板に限定されず、アルミナ回路基板等、他のセラミックで形成された回路基板にも適用可能である。
【００４８】
【発明の効果】
以上の説明から明らかなように、本発明の請求項１の構成によれば、セラミック基板の実装面に、該セラミック基板と異なる熱膨張係数のセラミック層が形成されたセラミック回路基板において、前記セラミック基板が、ＣａＯ−Ａｌ _２ Ｏ _３ −ＳｉＯ _２ −Ｂ _２ Ｏ _３ 系ガラス粉末とアルミナ粉末との混合物よりなる低温焼成セラミック材料により形成され、前記セラミック層が、前記低温焼成セラミック材料に対してＢｉ _２ Ｏ _３ を外掛けで０．５〜１５重量％配合した低温焼成セラミック材料により形成されているので、セラミック層の熱膨張係数はセラミック基板の熱膨張係数とフリップチップ等の回路要素（Ｓｉ）の熱膨張係数との中間となり、回路要素の接合部に生じる残留応力や熱応力を効果的に緩和することができる。すなわち、前記セラミック層は、低温焼成セラミック材料の有する低熱膨張性が更に向上することとなり、セラミック基板とセラミック層との焼結性を良好に保ちながら、フリップチップ実装の信頼性向上を図ることができる。
【００４９】
更に、請求項２では、前記セラミック層を、セラミック基板の実装面に部分的に形成したので、熱膨張係数が異なる複数種の回路要素を１つのセラミック基板に配置する場合でも、各々の回路要素とその接合面との熱膨張係数の差を少なくするように配置することができ、良好な接合性を得ることができる。
【００５０】
また、請求項３では、前記セラミック層の熱膨張係数を、前記セラミック基板の熱膨張係数よりも小さく且つ半導体チップの熱膨張係数よりも大きく設定したので、該セラミック層を介して信頼性の高いフリップチップ実装を行うことができる。
【００５１】
さらに、請求項４では、セラミック基板とセラミック層との熱膨張係数の差を１．５×１０^-6／ｄｅｇ以下に設定したので、加圧焼成しなくても、焼成時のセラミック基板の反りやセラミック層の剥がれを抑えることができ、セラミック回路基板の品質を向上できる。
【００５２】
また、請求項５では、セラミック基板とセラミック層とを同時焼成するようにしたので、焼成工程数が増えずに済み、品質の良いセラミック回路基板を能率良く製造できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態におけるセラミック回路基板の構造を模式的に示す拡大縦断面図
【図２】表層抵抗体の信頼性評価試験に用いた表層抵抗体と導体のパターンを示す拡大平面図
【図３】本発明の第２の実施形態におけるセラミック回路基板の構造を模式的に示す拡大縦断面図
【図４】本発明の第３の実施形態におけるセラミック回路基板の構造を模式的に示す拡大縦断面図
【符号の説明】
１１…低温焼成セラミック基板、１２…グリーンシート、１３…内層導体パターン、１４…表層導体パターン、１５…半導体チップ、１６…セラミック層、１７…パッド、１８…表層抵抗体、１９…Ａｇエポキシ、２１…低温焼成セラミック基板、２２…Ａｇ導体、２３…表層抵抗体、２６…セラミック層、２７…グリーンシート（セラミック層）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ceramic circuit board capable of relieving thermal stress generated at a joint portion of circuit elements such as a semiconductor chip, a surface layer resistor, and a surface layer conductor that are bonded to a mounting surface of the ceramic substrate.
[0002]
[Prior art]
Generally, ceramic substrates are widely used as substrates for semiconductor packages and hybrid ICs because they have advantages such as excellent heat resistance compared to plastic substrates, low thermal expansion coefficient, and easy fine patterning. Yes. With recent increases in density and miniaturization, there is an increasing tendency for flip chip mounting in which a semiconductor bare chip is directly mounted on a ceramic substrate. In this flip-chip mounting, if the difference in thermal expansion coefficient between the chip (Si) and the ceramic substrate is large, residual stress due to the thermal expansion difference at the time of mounting occurs at the chip joint, or heat generation during normal use causes relatively A large thermal stress is generated, and the chip joint portion is likely to be subject to thermal fatigue failure due to the repetition thereof, and the bonding reliability is lowered.
[0003]
Among the current ceramic substrates, the most commonly used alumina substrate has a coefficient of thermal expansion of 7.0 × 10 ⁻⁶ / deg, which is considerably smaller than that of a plastic substrate. The thermal expansion coefficient of the alumina substrate is considerably larger than the thermal expansion coefficient of Si (3.5 × 10 ⁻⁶ / deg), and the difference between the thermal expansion coefficients of both is 3.5 × 10 ⁻⁶ / deg. turn into. For this reason, with an alumina substrate, the reliability of flip chip mounting is lowered.
[0004]
[Problems to be solved by the invention]
Therefore, in recent years, as disclosed in Japanese Patent Publication No. 3-53269, a low-temperature fired ceramic substrate that has a smaller thermal expansion coefficient than an alumina substrate and can be fired at 1000 ° C. or less has been developed. This low-temperature fired ceramic substrate has a thermal expansion coefficient of about 5.5 × 10 ⁻⁶ / deg, and the difference in thermal expansion coefficient from Si is smaller than that of an alumina substrate. The difference in coefficients is still about 2.0 × 10 ⁻⁶ / deg, and a large flip chip cannot sufficiently relax the residual stress and thermal stress at the chip joint. Therefore, along with the recent trend toward larger flip-chips, further improvement in the reliability of flip-chip mounting is desired even for low-temperature fired ceramic substrates.
[0005]
For the surface layer thick film pattern parts such as surface layer resistors and surface layer conductors that are printed and fired with a thick film paste on the mounting surface of the ceramic substrate, it is possible to reduce the difference in thermal expansion coefficient with the ceramic substrate. This leads to improved reliability of the film pattern part. Generally, the thermal expansion coefficient of the surface layer resistor formed of the RuO ₂ resistor paste is 5.5 to 7.5 × 10 ⁻⁶ / deg, and low conductive loss such as Ag, Cu, Au, Ag / Pd, etc. Generally, the thermal expansion coefficient of the surface layer conductor formed of the conductive paste is 14 to 20 × 10 ⁻⁶ / deg, which is greatly different from the thermal expansion coefficient of the semiconductor chip.
[0006]
The present invention has been made in view of such circumstances, and the object thereof is to improve the reliability of circuit elements bonded to the mounting surface of a ceramic substrate, such as a flip chip and a surface thick film pattern portion. It is an object of the present invention to provide a ceramic circuit board that can be used.
[0007]
[Means for Solving the Problems]
To achieve the above object, a ceramic circuit board according to claim 1 of the present invention is a ceramic circuit board in which a ceramic layer having a thermal expansion coefficient different from that of the ceramic board is formed on a mounting surface of the ceramic board. Is formed of a low-temperature fired ceramic material made of a mixture of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ -based glass powder and alumina powder, and the ceramic layer is Bi _{2 with} respect to the low-temperature fired ceramic material. It is characterized by being formed of a low-temperature fired ceramic material containing 0.5 to 15% by weight of O ₃ as an outer shell.
In this configuration, even if there is a large difference between the thermal expansion coefficient of the circuit element (flip chip or the like) joined to the mounting surface of the ceramic substrate and the thermal expansion coefficient of the ceramic substrate, the intermediate thermal expansion coefficient is By interposing the ceramic layer, the residual stress and thermal stress generated in the joint portion of the circuit element can be relaxed by the ceramic layer. That is, as shown in Tables 1 and 2 described later, Bi ₂ O ₃ The coefficient of thermal expansion of the low-temperature fired ceramic that does not contain is 5.2 to 5.7 × 10 ⁻⁶ / deg, whereas Bi ₂ O ₃ The thermal expansion coefficient of the low-temperature fired ceramic containing 0.5 to 15% by weight as an outer coating is 4.6 to 5.0 × 10 ⁻⁶ / deg, and the thermal expansion coefficient of Si (circuit element) (3. The difference with 5 × 10 ⁻⁶ / deg) can be reduced.
Thus, by controlling the amount of Bi ₂ O ₃ added to the low-temperature fired ceramic material , the thermal expansion coefficient can be lowered. Therefore, even if the difference in thermal expansion coefficient between the ceramic substrate and Si (circuit element) is large, the residual stress generated at the junction of the circuit element can be reduced by interposing a ceramic layer having an intermediate thermal expansion coefficient between them. Thermal stress can be effectively relieved. As a result, the reliability of flip chip mounting can be improved while maintaining good sinterability between the ceramic substrate and the ceramic layer.
[0008]
In this case, as in claim 2, the ceramic layer is partially formed on the mounting surface of the ceramic substrate, and a plurality of types of circuit elements having different thermal expansion coefficients are mounted on the ceramic layer and other ceramic substrates. Of the surfaces, it is preferable to arrange the surfaces closer to each other. In this way, even when a plurality of types of circuit elements having different thermal expansion coefficients are arranged on one ceramic substrate, they are arranged so as to reduce the difference in thermal expansion coefficient between each circuit element and its joint surface. And good bondability can be obtained. Moreover, since the ceramic layer is only partially provided on the ceramic substrate, the stress generated between the ceramic layer and the ceramic substrate during firing can be reduced as compared with the case where the ceramic layer is provided on the entire surface of the ceramic substrate (this stress). If it is large, the ceramic substrate warps.)
[0009]
Further, it is preferable that the thermal expansion coefficient of the ceramic layer is set smaller than the thermal expansion coefficient of the ceramic substrate and larger than the thermal expansion coefficient of the semiconductor chip mounted on the ceramic layer. In this way, even if the difference in thermal expansion coefficient between the ceramic substrate and the semiconductor chip is large, the flip of mounting a semiconductor bare chip directly by interposing a ceramic layer having an intermediate thermal expansion coefficient between them. Chip mounting is possible.
[0010]
By the way, if the difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer is large, the ceramic substrate may be warped or peeled off due to stress during firing.
[0011]
As a countermeasure against this, it is preferable to set the difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer to 1.5 × 10 ⁻⁶ / deg or less as in the fourth aspect. If it does in this way, the curvature of the ceramic substrate at the time of baking and peeling of a ceramic layer can be suppressed.
[0012]
Further, the ceramic layer may be fired on the ceramic substrate after firing, or the ceramic substrate and the ceramic layer may be fired simultaneously as in claim 5. In this way, the number of firing steps is not increased and productivity is not lowered.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
First, a configuration example of a low-temperature fired ceramic circuit board according to the first embodiment of the present invention will be described with reference to FIG. The low-temperature fired ceramic substrate 11 is obtained by laminating and thermocompressing a plurality of low-temperature fired ceramic green sheets 12 and firing them at 800 to 1000 ° C.
[0015]
The low-temperature fired ceramic green sheet 12 is manufactured by the following procedure. First, CaO: 10 to 55 wt%, SiO _2: 45 to 70 wt%, Al ₂ O _3: 0 to 30 wt%, impurities: 0 to 10% by weight and in outer percentage B ₂ O _3: 5 to 20 weight After the mixture containing 1% is melted at 1450 ° C. and vitrified, it is rapidly cooled in water and pulverized to prepare a CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ glass powder. A low-temperature fired ceramic obtained by mixing 50 to 65% by weight (preferably 60% by weight) of this glass powder and 50 to 35% by weight (preferably 40% by weight) of Al ₂ O ₃ powder containing 0 to 10% by weight of impurities. A powder is prepared, and a solvent (for example, toluene, xylene), a binder resin (for example, an acrylic resin) and a plasticizer are added to the low-temperature fired ceramic powder, and the mixture is sufficiently kneaded to prepare a slurry. Using a normal doctor blade method Make a green sheet.
[0016]
This green sheet is cut into predetermined dimensions, and via holes (not shown) are punched out at predetermined positions to form green sheets 12 for each layer. Then, Ag-based conductor pastes such as Ag, Ag / Pd, and Ag / Pt are filled in the via holes of the green sheets 12 of each layer, and the inner-layer conductors are formed on the inner-layer green sheets 12 by using an Ag-based conductor paste having the same composition. The pattern 13 is screen-printed, and the surface conductor pattern 14 is screen-printed on the uppermost (surface) green sheet 12. At this time, as a conductive paste to be used, other low melting point metals such as Cu and Au may be used instead of the Ag-based conductive paste.
[0017]
Further, a ceramic layer 16 having a thermal expansion coefficient intermediate between the thermal expansion coefficient of the low-temperature fired ceramic and the thermal expansion coefficient of the semiconductor chip 15 is screen-printed on the uppermost green sheet 12 where the semiconductor chip 15 is mounted. Form. The composition of the ceramic layer 16 is such that 0.5 to 15% by weight of Bi ₂ O ₃ is blended with the low-temperature fired ceramic material having the same composition as the green sheet 12 described above. A binder resin (ethyl cellulose or polyvinyl butyral) and a solvent are added to the paste, and a paste of a low-temperature fired ceramic material prepared by sufficiently kneading is partially screen printed at a predetermined position on the uppermost green sheet 12 to form a ceramic layer 16. Form. On the surface of the ceramic layer 16, a pad 17 for connecting the semiconductor chip 15 (flip chip) is screen-printed with an Ag-based conductive paste. Note that a via conductor (not shown) for connecting each pad 17 to the conductor patterns 13 and 14 is screen-printed in advance with an Ag-based conductor paste on the ceramic layer 16.
[0018]
After completion of the printing process as described above, the green sheets 12 of the respective layers are laminated and integrated by thermocompression bonding under conditions of, for example, 80 to 150 ° C. (preferably 110 ° C.) and 50 to 250 kg / cm ² . And this laminated body is baked at 800-1000 degreeC (preferably 900 degreeC) which is a board | substrate baking temperature on the hold | maintenance conditions for 20 minutes, and the low-temperature baking ceramic substrate 11 and the ceramic layer 16 are baked simultaneously. In this firing process, part of Bi ₂ O ₃ contained in the ceramic layer 16 diffuses into the surface green sheet 12, and an intermediate thermal expansion coefficient ceramic is formed around the ceramic layer 16. Thereby, the thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the ceramic layer 16 is continuously changed, and the stress at the time of firing is relaxed to prevent the low-temperature fired ceramic substrate 11 from warping.
[0019]
Thereafter, a surface layer resistor 18 is screen-printed on the upper surface of the low-temperature fired ceramic substrate 11 using a RuO ₂ resistor paste, and an overcoat (not shown) is formed on the surface layer resistor 18 using an overcoat paste. ) Is screen printed. Thereafter, the low-temperature fired ceramic substrate 11 is fired at a temperature slightly lower than the substrate firing temperature (for example, 890 ° C.) under the condition of holding for 10 minutes under the condition of holding for 10 minutes. This completes the manufacture of the low-temperature fired ceramic substrate 11.
[0020]
Thereafter, when the semiconductor chip 15 is flip-chip mounted on the low-temperature fired ceramic substrate 11, the electrode on the lower surface of the semiconductor chip 15 is attached to the Ag epoxy 19 or the solder bump on the pad 17 of the ceramic layer 16 of the low-temperature fired ceramic substrate 11. Connect by.
[0021]
The inventor measured the thermal expansion coefficients of the low-temperature fired ceramics having three types of compositions A, B, and C shown in Table 1 below.
[0022]
[Table 1]

[0023]
In Table 1, the weight ratio of each component (CaO, Al ₂ O ₃ , SiO ₂ , B ₂ O ₃ ) of the glass powder is represented by the weight ratio to the low-temperature fired ceramic.
Composition A is a mixture of 60% by weight of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ glass powder and 40% by weight of Al ₂ O ₃ powder, and has a thermal expansion coefficient of 5.5 × 10 ^−6. / Deg.
[0024]
Composition B is a mixture of 55% by weight of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ glass powder and 45% by weight of Al ₂ O ₃ powder, and has a thermal expansion coefficient of 5.7 × 10 ^−6. / Deg.
[0025]
Composition C is a mixture of 65% by weight of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ glass powder and 35% by weight of Al ₂ O ₃ powder, and has a thermal expansion coefficient of 5.2 × 10 ^−6. / Deg.
The thermal expansion coefficients of the low-temperature fired ceramics of these compositions A, B, and C are all small compared to the thermal expansion coefficient (7.0 × 10 ⁻⁶ / deg) of the alumina substrate.
[0026]
Furthermore, since this inventor performed the test which evaluates the relationship between the composition of the low-temperature baking ceramic material which forms the ceramic layer 16, and a thermal expansion coefficient, the test result is shown in following Table 2.
[0027]
[Table 2]

[0028]
Table 2 shows how much the coefficient of thermal expansion changes depending on the amount of Bi ₂ O ₃ when Bi ₂ O ₃ is added to the low-temperature fired ceramics having the compositions A, B, and C shown in Table 1. Is. From this measurement result, if the amount of Bi ₂ O ₃ added is 0.5 to 15% by weight, the thermal expansion coefficient is 5.0 × 10 ⁻⁶ / deg or less in any composition, and Bi ₂ The thermal expansion coefficient is smaller than that of a low-temperature fired ceramic containing no O ₃ .
[0029]
In order to evaluate the bonding reliability of the semiconductor chip 15 mounted on the ceramic layer 16 of the low-temperature fired ceramic substrate 11, the present inventor is a paste made by adding Bi ₂ O ₃ to the low-temperature fired ceramic of the composition A. After the ceramic layer 16 is printed on the surface layer of the low-temperature fired ceramic substrate 11 and fired, the semiconductor chip 15 is mounted on the ceramic layer 16 with Ag epoxy 19, and a temperature cycle test (−55 ° C. 30 minutes / + 150 30 ° C .: 100 cycles), and the failure rate of the chip joint was measured. The measurement results are shown in Table 3 below.
[0030]
[Table 3]

[0031]
As apparent from the test results of Table 3, when the amount of Bi ₂ O ₃ added is 0% by weight (substantially the same as when no ceramic layer 16 is present), the failure rate is 0.5%. However, if the added amount of Bi ₂ O ₃ is 0.5 to 15% by weight, the thermal expansion coefficient is 4.9 × 10 ⁻⁶ / deg or less, and the thermal expansion coefficient of the semiconductor chip 15 (Si) Since it is close to (3.5 × 10 ⁻⁶ / deg), the failure rate is 0%, and extremely high bonding reliability is obtained. When the amount of Bi ₂ O ₃ added is 20% by weight or more, the difference in thermal expansion coefficient from Si increases, so the failure rate becomes 0.2% or more and the joint reliability decreases. Therefore, in order to ensure sufficient bonding reliability, it is preferable to set the addition amount of Bi ₂ O ₃ within the range of 0.5 to 15% by weight. In this case, the difference in thermal expansion coefficient between the ceramic layer 16 and Si is 1.2 to 1.4 × 10 ⁻⁶ / deg. If this difference is such a degree, the chip joint (Ag epoxy 19) Residual stress and thermal stress can be sufficiently relaxed by elasticity, and the failure rate can be maintained at 0%.
[0032]
By the way, if the difference in thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the ceramic layer 16 is large, the low-temperature fired ceramic substrate 11 may be warped or the ceramic layer 16 may be peeled off due to stress during firing.
[0033]
As described above, when the addition amount of Bi ₂ O ₃ is set within the range of 0.5 to 15% by weight, the thermal expansion coefficient of the ceramic layer 16 is 4.6 to 5.0 × 10 ⁻⁶ / deg (see Table 2), and the difference in thermal expansion coefficient between the ceramic layer 16 and the low-temperature fired ceramic substrate 11 is 0.9 × 10 ⁻⁶ / deg or less. If the difference in thermal expansion coefficient is about this level, a ceramic having an intermediate thermal expansion coefficient is formed around the ceramic layer 16 by diffusion of Bi ₂ O ₃ during firing, thereby sufficiently relaxing the stress during firing. In addition, warping of the low-temperature fired ceramic substrate 11 and peeling of the ceramic layer 16 can be sufficiently suppressed. In general, if the difference in coefficient of thermal expansion between the ceramic layer 16 and the low-temperature fired ceramic substrate 11 is 1.5 × 10 ⁻⁶ / deg or less, the warp of the low-temperature fired ceramic substrate 11 and the peeling of the ceramic layer 16 are sufficient. Can be suppressed.
[0034]
Next, the reliability of the surface layer resistor 18 will be considered. Generally, since the resistance value of the surface layer resistor 18 after baking varies, the resistance value is adjusted by trimming the surface layer resistor 18 by a laser trimming method or the like after baking. As a result, micro-cracks may enter the surface layer resistor 18, and the micro-cracks gradually progress in the actual use environment, and the resistance value may change with time, which may reduce circuit reliability. The progress of the microcrack is likely to occur when a tensile stress is applied to the surface layer resistor 18. Therefore, in order to prevent the progress of microcracks, it is desirable to set the relationship of the thermal expansion coefficient of the low-temperature fired ceramic substrate 11> the thermal expansion coefficient of the surface layer resistor 18 so that a compressive force is applied to the surface layer resistor 18.
[0035]
In general, the RuO ₂ resistor paste forming the surface layer resistor 18 is a mixture of RuO ₂ powder (thermal expansion coefficient: 6.0 × 10 ⁻⁶ / deg) and glass powder, and therefore has a small thermal expansion coefficient. Even if glass powder is used, it is difficult to make the thermal expansion coefficient of the surface layer resistor 18 smaller than 5.0 × 10 ⁻⁶ / deg. Therefore, the ceramic of the portion forming the surface layer resistor 18 desirably has a thermal expansion coefficient of 5.0 × 10 ⁻⁶ / deg or more. From this point of view, in the above embodiment, the surface layer resistor 18 is formed on the surface of the low-temperature fired ceramic substrate 11.
[0036]
In order to avoid the influence of the thermal expansion coefficient of the ceramic layer 16 containing Bi ₂ O ₃ , it is preferable that the surface layer resistor 18 has a distance of 0.5 mm or more (preferably 1 mm or more) from the ceramic layer 16.
[0037]
The present inventor conducted the following test in order to evaluate the reliability of the surface layer resistor 18. As shown in FIG. 2, on the surface of the low-temperature fired ceramic substrate 21 (coefficient of thermal expansion: 5.5 × 10 ⁻⁶ / deg), Ag conductors 22 for resistor electrodes are printed and fired at intervals of 2 mm. Then, a surface layer resistor 23 (width 1 mm) having a thermal expansion coefficient of 5.3 × 10 ⁻⁶ / deg was printed and fired. Thereafter, the surface resistor 23 is laser-trimmed, and the resistance value is adjusted to twice the initial value, and then a temperature cycle test (-55 ° C. 30 minutes / + 150 ° C. 30 minutes: 100 cycles) is performed. The change rate of the resistance value of the surface layer resistor 23 was measured. When this measurement was performed for 100 samples, the results shown in Table 4 below were obtained.
[0038]
[Table 4]

[0039]
The change rate of the resistance value of the surface layer resistor 23 measured in this test is as small as 0.23% even at the maximum value, and sufficiently satisfies the required value (within 1%). Therefore, even if a ceramic layer having a partially different thermal expansion coefficient exists on the surface of the low-temperature fired ceramic substrate 21, the reliability of the surface layer resistor 23 is not affected at all.
[0040]
In this embodiment (FIG. 1), the ceramic layer 16 is printed on the surface of the low-temperature fired ceramic substrate 11, but a green sheet formed of the same composition as the ceramic layer 16 may be laminated.
[0041]
[Second Embodiment]
In the first embodiment, the ceramic layer 16 is printed on the surface of the low-temperature fired ceramic substrate 11, but in the second embodiment shown in FIG. 3, the portion of the surface green sheet 12 where the semiconductor chip 15 is mounted. An opening 25 is formed in the opening 25, and the opening 25 is filled with a ceramic layer 26 having an intermediate thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the semiconductor chip 15 and fired. 15 is implemented. The ceramic layer 26 has the same composition as that of the first embodiment, and may be formed by printing a paste thereof, or a green sheet used in a third embodiment to be described later is cut to a predetermined size to form an opening. 25 may be fitted. Since the other configuration is the same as that of the first embodiment described above, the same reference numerals are given and the description thereof is omitted.
[0042]
In the first and second embodiments, the surface layer resistor 18 is formed, but it goes without saying that the structure may be omitted. In addition, the ceramic layers 16 and 26 may be formed at a plurality of locations on one low-temperature fired ceramic substrate 11, and a plurality of flip chips may be mounted on the ceramic layers 16 and 26 at one location. .
[0043]
[Third Embodiment]
In the first and second embodiments, the ceramic layers 16 and 26 are formed on only a part of the surface of the low-temperature fired ceramic substrate 11, but in the third embodiment shown in FIG. A green sheet 27 having an intermediate thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the semiconductor chip 15 is laminated on the uppermost layer (surface layer) as a “ceramic layer”, thereby thermally expanding the entire surface of the low-temperature fired ceramic substrate 11. Ceramic layers 27 having different coefficients are formed. The composition of the ceramic layer 27 is the same as that in the first embodiment. The green sheet forming the ceramic layer 27 is obtained by tape-forming a slurry prepared by adding a binder resin, a solvent and a plasticizer to a low-temperature fired ceramic material containing 0.5 to 15% by weight of Bi ₂ O ₃ as an outer shell. As the binder resin, an acrylic resin or polyvinyl butyral may be used.
[0044]
In this third embodiment, since two types of green sheets 12 and 27 having different thermal expansion coefficients are laminated and fired, the low-temperature fired ceramic substrate 11 is warped or the ceramic layer 27 is peeled off by a normal firing method. There is a risk that. As a countermeasure against this, the laminate of the green sheets 12 and 27 may be fired while being pressed. By this pressure firing, warping of the low-temperature fired ceramic substrate 11 and peeling of the ceramic layer 27 can be prevented.
[0045]
The third embodiment is preferably applied to a circuit board in which no surface layer resistor is provided on the substrate surface. When a surface layer resistor is provided, the relationship between the thermal expansion coefficient of the substrate surface <the thermal expansion coefficient of the surface layer resistor is established, and tensile stress acts on the surface layer resistor, and microcracks are likely to occur in the surface layer resistor. This is because the rate of change of the resistance value increases.
[0047]
The ceramic circuit board of the present invention is not limited to a low-temperature fired ceramic circuit board, and can be applied to a circuit board formed of other ceramics such as an alumina circuit board.
[0048]
【The invention's effect】
As is apparent from the above description, according to the configuration of claim 1 of the present invention, in the ceramic circuit board in which the ceramic layer having a thermal expansion coefficient different from that of the ceramic board is formed on the mounting surface of the ceramic board, the ceramic The substrate is formed of a low-temperature fired ceramic material made of a mixture of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ -based glass powder and alumina powder, and the ceramic layer is Bi to the low-temperature fired ceramic material. Since it is made of a low-temperature fired ceramic material containing 0.5 to 15% by weight of ₂ O ₃ as an outer coating, the thermal expansion coefficient of the ceramic layer is equal to the thermal expansion coefficient of the ceramic substrate and circuit elements (Si) such as flip chips. It is possible to effectively relieve residual stress and thermal stress generated at the joint portion of the circuit element. That is, the ceramic layer further improves the low thermal expansion property of the low-temperature fired ceramic material, and can improve the reliability of flip chip mounting while maintaining good sinterability between the ceramic substrate and the ceramic layer. it can.
[0049]
Further, in claim 2, since the ceramic layer is partially formed on the mounting surface of the ceramic substrate, each circuit element is provided even when a plurality of types of circuit elements having different thermal expansion coefficients are arranged on one ceramic substrate. Can be arranged so as to reduce the difference in coefficient of thermal expansion between the contact surface and the bonding surface, and good bondability can be obtained.
[0050]
According to the third aspect of the present invention, since the thermal expansion coefficient of the ceramic layer is set smaller than the thermal expansion coefficient of the ceramic substrate and larger than the thermal expansion coefficient of the semiconductor chip, the ceramic layer has high reliability through the ceramic layer. Flip chip mounting can be performed.
[0051]
Further, in claim 4, since the difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer is set to 1.5 × 10 ⁻⁶ / deg or less, the warpage of the ceramic substrate during firing can be performed without firing by pressure. And the peeling of the ceramic layer can be suppressed, and the quality of the ceramic circuit board can be improved.
[0052]
According to the fifth aspect of the present invention, since the ceramic substrate and the ceramic layer are fired simultaneously, the number of firing steps is not increased, and a high-quality ceramic circuit substrate can be efficiently manufactured.
[Brief description of the drawings]
FIG. 1 is an enlarged longitudinal sectional view schematically showing a structure of a ceramic circuit board in a first embodiment of the present invention. FIG. 2 shows a pattern of a surface layer resistor and a conductor used in a reliability evaluation test of a surface layer resistor. Fig. 3 is an enlarged plan view schematically showing the structure of a ceramic circuit board according to a second embodiment of the present invention. Fig. 4 is a diagram showing the structure of a ceramic circuit board according to a third embodiment of the present invention. Schematic enlarged vertical sectional view [Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Low temperature firing ceramic substrate, 12 ... Green sheet, 13 ... Inner layer conductor pattern, 14 ... Surface layer conductor pattern, 15 ... Semiconductor chip, 16 ... Ceramic layer, 17 ... Pad, 18 ... Surface layer resistor, 19 ... Ag epoxy, 21 ... low temperature fired ceramic substrate, 22 ... Ag conductor, 23 ... surface layer resistor, 26 ... ceramic layer, 27 ... green sheet (ceramic layer).

Claims (5)

In a ceramic circuit board in which a ceramic layer having a thermal expansion coefficient different from that of the ceramic substrate is formed on the mounting surface of the ceramic substrate ,
The ceramic substrate is formed of a low-temperature fired ceramic material made of a mixture of CaO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃ glass powder and alumina powder,
The ceramic circuit board , wherein the ceramic layer is formed of a low-temperature fired ceramic material in which 0.5 to 15% by weight of Bi ₂ O ₃ is externally blended with the low-temperature fired ceramic material . The ceramic layer is partially formed on the mounting surface of the ceramic substrate, and a plurality of types of circuit elements having different thermal expansion coefficients are similar in thermal expansion coefficient among the mounting surfaces of the ceramic layer and other ceramic substrates. ceramic circuit board according to claim 1 Symbol mounting wherein it is arranged towards. Thermal expansion coefficient of the ceramic layer, No It mounting according to claim 1 or claim 2 Symbol for being greater than the thermal expansion coefficient of the semiconductor chip to be mounted on small and the ceramic layer than the thermal expansion coefficient of said ceramic substrate Ceramic circuit board. Difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer, the ceramic circuit board according to any one of claims 1 to 3, characterized in that it is 1.5 × 10 ^-6 / deg or less. The ceramic circuit board according to any one of claims 1 to 4, wherein the ceramic substrate and the ceramic layer are simultaneously fired.

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