JP3849035B2 - Input / output control device for pachinko machines - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device in a pachinko machine and relates to an input / output interface.
[0002]
[Prior art]
In a pachinko machine, a central processing unit (hereinafter referred to as a CPU) that drives and controls each driving element and each detecting means arranged in the pachinko machine, a ROM that stores a control program related to a pachinko game, and various data necessary for each control process A control device having a RAM for performing reading and writing is provided. A programmable input / output interface (hereinafter referred to as PPI) is connected to the CPU so that the CPU can smoothly and synchronously output drive signals to the drive elements and input detection signals from the detection means. Inputs a detection signal from each detection means via an input / output interface, and outputs a drive signal to each drive element.
[0003]
FIG. 3 is a plan view showing the appearance of a conventional PPI 1a. The PPI 1a is provided with a total of 40 pins. D0 to D7 are connected to the data bus. A reset signal is input to RESET. CS is a chip select terminal. RD is a read signal input terminal. WR is a write signal input terminal. A0 and A1 are input terminals for port selection. The operating voltage 5V of PPI 1a is applied to the Vcc terminal, and the GND terminal is the ground of 0V. PA0 to PA7 are first ports, PB0 to PB7 are second ports, and PC0 to PC7 are third ports.
[0004]
FIG. 4 is a principal block diagram of the PPI 1a. D7 to D0 are bidirectional buses connected to the data bus of the CPU, and are connected to the 8-bit internal data bus of the PPI 1a through the data bus buffer 2. D7 to D0 are used for writing control data at the time of initialization, and for transferring data between the input / output port and the CPU data bus.
[0005]
The control logic 3 is a part for transferring data and control words (data for initialization), and includes the CPU address bus output (A0, A1, CS), control bus output (RD, WR), and reset (RESET). Each signal is received and two control groups inside the PPI 1a are commanded.
[0006]
CS is a chip select terminal, and PPI 1a is selected when the input is at a low level, and exchange with the CPU is possible. When the input is at a high level, the data bus is in a high impedance state and is disconnected from the CPU. It becomes a state. At this time, the previously output data is held in the output port. When a plurality of I / O ports are used, a selection signal is given to the CS terminal from the address decoder.
[0007]
The RD is a read signal input terminal, and transfers data input to the port of the PPI 1a to the CPU when the input is at a low level. When controlled by the RD signal of the CPU and connected to the CPU, a signal generated in combination with an IORQ (I / O request) signal output when the CPU executes the IN and OUT instructions is given.
[0008]
WR is a write signal input terminal, and when the input is at a low level, data or a control word is written from the CPU to the PPI 1a. When connecting to the CPU in the same manner as the RD input, a signal made in combination with an IORQ (I / O request) signal is given.
[0009]
A0 and A1 are terminals for port selection input, and are used to select the first port, the second port, the third port and the command register, and are normally connected to the lower 2 bits of the CPU address bus. . Together with the CS input, each PPI port and command register address are determined. This relationship is shown in Table 1.
[0010]
[Table 1]
The RESET terminal is an input terminal for resetting the PPI 1a, and performs a power-on reset when the power is turned on.
[0011]
The group A control 4 and the group B control 5 receive the control word of the internal data bus in response to a command from the control logic, and issue a command to each port. Actually, the function of each port is determined by writing a control word in the command register 6. Note that the command register 6 is only writable and reading is prohibited.
[0012]
The eight data bits of the first ports PA7 to PA0 operate as latches at output, latches and buffers at input, or bidirectional buses, respectively. The eight data bits of the second ports PB7 to PB0 operate as a latch at the time of output, a latch at the time of input, and a buffer, respectively, as in the first port, but do not perform a bidirectional operation.
[0013]
The third ports PC7 to PC0 operate as an output latch and an input buffer. The third ports PC7 to PC0 have functions different from those of the first ports PA7 to PA0 and the second ports PB7 to PB0. In mode 0, the third ports PC7 to PC0 operate as a latch at the time of output and operate as a buffer at the time of input. PC4 and lower 4 bits PC3 to PC0 can be divided and designated as input or output ports. Further, it is also used as a control signal for the first port and the second port.
[0014]
When the third ports PC7 to PC0 are designated as output ports, any one of the 8 bits can be set (high level) or reset (low level) by a control word from the CPU. The execution method of this bit set and bit reset is the same as that in the case of mode set (initialization), but the control word is different. This function is also used for setting and resetting INTE (interrupt enable flag) in mode 1 and mode 2.
[0015]
There are three modes of operation of the PPI 1a: mode 0, mode 1 and mode 2. In mode 0, each port (first port, second port, upper 4 bits of the third port and lower 4 bits of the third port) of the PPI 1a is simply used as an input port or an output port. Mode 1 is a mode for inputting and outputting data while knowing and checking the state of the external device. The first port and the second port are used for data input / output, and the third port is used for each control signal. Mode 2 can only be used for the first port and operates as an 8-bit bidirectional bus port.
[0016]
As shown in Table 1, the mode setting of PP I 1a is performed by writing data with both the A1 terminal and the A0 terminal set to “1”. Since the A1 terminal and the A0 terminal are normally connected to the lower two bits of the address bus of the CPU, they are executed by a write command for a specific address in terms of software.
[0017]
When mode setting is performed, the value of bit 7 of the control word to be written is set to 1, and data for actual mode setting is performed by seven bits of bit 6 to bit 0 (see FIG. 5). In writing with bit 7 of the control word set to 0, when the third ports PC7 to PC0 become control signals in mode 1 or mode 2, these signals are set / reset (see FIG. 6).
[0018]
Further, as shown in Table 1, data reading / writing with respect to the port is performed in the same manner as the control data by combining the A1 terminal and the A0 terminal of the PPI 1a.
[0019]
In the PPI 1a configured as described above, the frequency of use in mode 0 is the highest in pachinko machines, and the control word to be written to the command register on the PPI 1a side is switched by the CPU side input / output port switching setting program. ing. Table 2 shows control words for setting mode 0. In Table 2, the output indicates an output port, and the input indicates an input port.
[0020]
[Table 2]
On the CPU side, the input / output port switching setting program is executed every time a reset signal is input to the CPU. In the processing of the input / output port switching setting program, all ports are first input. The port is set again, and then the output port is set sequentially. For this reason, every time a reset signal is input to the CPU, the input / output ports are periodically set to the PPI 1a. However, the PPI 1a has a very low electrostatic noise withstand voltage, and the control word is static. The problem of rewriting due to noise sometimes occurred.
[0021]
[Problems to be solved by the invention]
An object of the present invention is not to write a control word to the command register of the PPI by the CPU, but instead to set input / output of each port group by giving a setting signal to each port group in hardware. It is to provide an input / output control device for a pachinko machine capable of performing the above.
[0022]
[Means for Solving the Problems]
An input / output control device for a pachinko machine according to the present invention is an input / output control device including a plurality of port groups that can be set to either an input port or an output port in order to solve the above problem.
The input / output control device is provided with an input / output setting terminal for inputting a setting signal for setting each of the plurality of port groups to either an input port or an output port,
Separately for the input and output setting pin, provided with an external decoder for setting the setting signal is either pulled-up high-level signal or pulldown processed low-level signal, the entering-output controller ,
The operation of the input / output control device is fixedly determined by the setting signal given in hardware, instead of using a control word by a program for input / output port switching setting.
[0023]
The decoder individually gives a setting signal to an input / output setting terminal that sets each of a plurality of port groups provided in the input / output control device of the pachinko machine as either an input port or an output port. The setting signal is either a pulled up high level signal or a pulled down low level signal, and is always input to the input / output setting terminals of each of the plurality of port groups. The control word periodically output from the CPU by the processing of the CPU is not written to the command register of the PPI, but a setting signal is always given in hardware from the decoder for each port group. Since the input / output setting is performed, the phenomenon that the control word is rewritten due to electrostatic noise can be avoided, and the malfunction of the pachinko machine due to the incorrect input / output setting of the port group can be effectively prevented.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing an external appearance of an input / output device of a pachinko machine according to an embodiment of the present invention. The input / output device (hereinafter referred to as PPI) 1 has terminals of the conventional input / output device 1a shown in FIG. 3, that is, RD, CS, GND, A0, A1, Vcc, WR, RESET, D7˜ In addition to the four port groups PA7 to PA0, PB7 to PB0, PC7 to PC4, and PC3 to PC0 that can be set to D0 and any of the input and output ports, four port groups PA7 to PA0, PB7 to Input / output setting terminals CD1 to CD4 for setting each port group as either an input port or an output port are attached to each of PB0, PC7 to PC4, and PC3 to PC0.
[0025]
CD1 is an input / output setting terminal for the first ports PA7 to PA0, CD2 is an input / output setting terminal for the second ports PB7 to PB0, and CD3 is a higher rank of the third ports PC7 to PC0. An input / output setting terminal for PC7 to PC4 composed of 4 bits, and CD4 is an input / output setting terminal for PC3 to PC0 composed of lower 4 bits of the third ports PC7 to PC0.
[0026]
As in the conventional input / output device 1a shown in FIG. 3, the RD terminal is a read signal input terminal, and when the input is at a low level, the data input to the port of the PPI 1 is omitted from the CPU (not shown). ). When controlled by the RD signal of the CPU and connected to the CPU, a signal generated in combination with an IORQ (I / O request) signal output when the CPU executes the IN and OUT instructions is given.
[0027]
The WR terminal is a write signal input terminal, and when the input is at a low level, data or a control word is written from the CPU to PPI1. When connecting to the CPU in the same manner as the RD input, a signal made in combination with an IORQ (I / O request) signal is given.
[0028]
The CS terminal is a chip select terminal, and when the input is at a low level, PPI1 is selected and can communicate with the CPU. When the input is at a high level, the data bus is in a high impedance state and is disconnected from the CPU. It becomes a state. At this time, the previously output data is held in the output port. When a plurality of I / O ports are used, a selection signal is given to the CS terminal from the address decoder.
[0029]
The operating voltage 5V of PPI1 is applied to the Vcc terminal, and the GND terminal is the ground of 0V.
[0030]
The D7 to D0 terminals are bidirectional buses connected to the data bus, and are connected to the 8-bit internal data bus of PPI1 through the data bus buffer 2. D7 to D0 are used for writing control data at the time of initialization, and for transferring data between the input / output port and the CPU data bus. RESET is an input terminal for resetting PPI1, and performs a power-on reset when the power is turned on.
[0031]
The A0 terminal and the A1 terminal are input terminals for port selection, and the first port PA7 to PA0, the second port PB7 to PB0, the upper PC7 to PC4 of the third port, and the lower PC3 to PC0 of the third port are selected. Normally, it is connected to the lower 2 bits of the address bus of the CPU. The address of each port of PPI1 is determined together with the CS input. This relationship is shown in Table 3.
[0032]
[Table 3]
Further, as shown in Table 3, data reading / writing with respect to the port is performed in the same manner as the control data by combining the A1 terminal and the A0 terminal of PPI1.
[0033]
FIG. 2 is a principal block diagram of the PPI 1 in the embodiment. For each of the four port groups shown in FIG. 1, ie, the first port PA7 to PA0, the second port PB7 to PB0, the upper PC7 to PC4 of the third port, and the lower PC3 to PC0 of the third port, A port setting decoder 7 is provided to individually provide port setting signals for the input port and the output port for each of the input / output setting terminals CD1 to CD4 for setting the port group to either the input port or the output port. It is provided as a supplement.
[0034]
The operation of the PPI 1 is fixedly determined by the port setting signals A to D of the input port and the output port output from the port setting decoder 7, and each port of the PPI 1 (first port PA7 to PA0, second port PB7 to PB0, the upper 4 bits PC7 to PC4 of the third port, and the lower 4 bits PC3 to PC0 of the third port) are simply used as input ports or output ports.
[0035]
The port setting signals A to D are either a pulled up high level signal or a pulled down low level signal, and are always input to the input / output setting terminals CD1 to CD4 of each of the four port groups. When the port setting signal is at a high level, the port is set to input, and when the port setting signal is at a low level, the port is set to output.
[0036]
For example, the first ports PA7 to PA0 are input ports, the second ports PB7 to PB0 are output ports, the upper 4 bits PC7 to PC4 of the third port are output ports, and the lower 4 bits PC3 to PC0 of the third port are input ports. When used, the port setting signal of the port setting decoder 7 is obtained by setting the port setting signal A to the high level, the port setting signal B to the low level, the port setting signal C to the low level, and the port setting signal D to the high level. Realized.
[0037]
Thus, the four port groups of PPI1, that is, each of the first port PA7 to PA0, the second port PB7 to PB0, the upper 4 bits PC7 to PC4 of the third port, and the lower 4 bits PC3 to PC0 of the third port The setting of either the input port or the output port is not performed by periodically writing the control word data output from the CPU by the CPU to the command register of the PPI, but from the port setting decoder 7 for each port group. By constantly providing port setting signals A to D in hardware, the input / output setting of each port group is performed, so that the phenomenon that the control word is rewritten due to electrostatic noise can be avoided. It is possible to effectively prevent the malfunction of the pachinko machine due to the incorrect setting.
[0038]
Further, there is an effect that handshake mutual communication does not have to be recognized between the CPU and the PPI 1.
[0039]
【The invention's effect】
The input / output control device for a pachinko machine according to the present invention is provided with input / output setting terminals for setting each port group as either an input port or an output port for each of a plurality of port groups. By providing an external decoder for individually providing input port and output port setting signals to the output setting terminals, any of the input ports and output ports for each of the plurality of port groups can be set by the CPU. The control word output from the CPU periodically is not written to the command register of the PPI, and the port setting signal is always provided from the decoder for each port group in a hardware manner, so that the input / output of each port group is performed. Because of this setting, the phenomenon that the control word is rewritten due to electrostatic noise can be avoided. Malfunction of pachinko machines due to erroneous setting can be effectively prevented.
[0040]
In addition, there is an effect that the handshake mutual communication does not have to be recognized between the CPU and the PPI.
[Brief description of the drawings]
FIG. 1 is a plan view showing an external appearance of an input / output control device for a pachinko machine according to an embodiment of the present invention. FIG. 2 is a block diagram of a main part of the input / output control device according to the embodiment. FIG. 4 is a block diagram of the main part of the conventional input / output control device. FIG. 5 is a diagram showing the configuration of control data for mode setting for the conventional input / output control device. 6 is a diagram showing the configuration of bit set / reset control data for a conventional input / output control device.
DESCRIPTION OF SYMBOLS 1 Input / output controller 2 Data bus buffer 3 Control logic 4 Group A control 5 Group B control 6 Command register 7 Port setting decoder PA7-PA0 1st port PB7-PB0 2nd port PC7-PC0 3rd port

Claims (1)

In the input / output control device having a plurality of port groups that can be set to either the input port or the output port,
The input / output control device is provided with an input / output setting terminal for inputting a setting signal for setting each of the plurality of port groups to either an input port or an output port,
A decoder for setting the setting signal, which is either a pulled-up high level signal or a pulled-down low level signal, is provided externally to the input / output control device for the input / output setting terminal. ,
The operation of the input / output control device is fixedly determined by the setting signal given in hardware, instead of using a control word by a program for switching an input / output port.
Input / output control device for pachinko machines.

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