JP3849562B2 - Current output transmitter - Google Patents

Description

になる。この式に前記（６）式およびＲ１＝１００Ω、Ｒ２＝Ｒ３＝１００ＫΩを代入すると、
Io＝(Vref／100)×(D1＋D2／128)
になる。
【００４５】
すなわち、上位８ビットを粗調設定値Ｄ１に設定し、下位７ビットを微調設定値Ｄ２にセットすればよいことがわかる。このようにすると、時間のかかる剰余算を行わなくてもよいので、応答性を高めることができる。
【００４６】
図３に本発明の他の実施例を示す。この実施例はデジタルアナログ変換部を３つ用いたものである。図３において、４３は信号処理回路中のマイクロプロセッサであり、センサ（図示せず）の出力Ｓを（ｎ１＋ｎ２＋ｎ３）ビットの値に変換する。
【００４７】
要素１〜要素３は図１のＰＷＭ回路５２あるいはデジタルアナログ変換部１であり、マイクロプロセッサ４３が変換した値が入力される。すなわち、要素１には下位ｎ３ビットが、要素２には中位ｎ２が、要素３には上位ｎ１ビットがそれぞれ設定値として入力される。要素１〜要素３はこの入力された設定値をアナログ信号に変換して出力する。
【００４８】
２１は減衰部であり、要素１の出力を１／２^{ｎ２＋ｎ３}に減衰する。２２は減衰部であり、要素２の出力を１／２^ｎ２に減衰する。３は加算部であり、減衰部２１，２２および要素３の出力を加算し、また必要であれば電流信号に変換して出力する。
【００４９】
なお、これらの実施例ではデジタルアナログ変換部を２つあるいは３つ使用したが、４つ以上使用するようにしてもよい。また、図１実施例では２線式伝送器の例で説明したが、３線式あるいは４線式の伝送器に用いることもできる。
【００５０】
【発明の効果】
以上説明したことから明らかなように、本発明によれば、次の効果が期待できる。
本発明の実施例は、異なる最小出力値を有する複数のデジタルアナログ変換部１，５２を有し、この複数のデジタルアナログ変換部１，５２にアナログ値に変換すべきデジタル値に関連する値を入力し、複数のデジタルアナログ変換部１，５２のアナログ出力を加算して出力する構成のデジタルアナログ変換器であって、デジタルアナログ変換部の少なくとも１つをパルス幅変調方式のデジタルアナログ変換器５２で構成し、他のデジタルアナログ変換部を変換速度が速いデジタルアナログ変換器１１で構成するようにした。
【００５１】
デジタルアナログ変換部を２個以上用いて変換するようにしたので、パルス変調方式のデジタルアナログ変換器の出力パルスの周期を短くすることができるので、応答速度を早くすることができるという効果がある。また、構成が簡単なパルス変調方式のデジタルアナログ変換器も併用するようにしたので、構成が複雑にならないという効果もある。
【００５２】
また、本発明の実施例は、前記変換速度が早いデジタルアナログ変換器は重み抵抗型またはラダー抵抗型または重み定電流型または抵抗回路網型のデジタルアナログ変換器であることを特徴とした。構成が比較的簡単でかつ変換速度が速いデジタルアナログ変換器を用いることができるという効果がある。
【００５３】
さらに、本発明の実施例は、複数のデジタルアナログ変換部１，５２のうち最小出力値が最大のデジタルアナログ変換部を除いたデジタルアナログ変換部１は、デジタル値をアナログ信号に変換するＤ／Ａ変換回路１１と、このＤ／Ａ変換回路１１の出力を減衰させる減衰部１２とから構成されることを特徴とした。
【００５４】
減衰部で減衰させるために高抵抗を用いる必要がないので、漏れ電流による精度低下がなく、かつ信頼性が低下しないという効果がある。
【００５５】
また、本発明の実施例は、最小出力値が最大のデジタルアナログ変換部５２およびＤ／Ａ変換回路１１はほぼ同じ最小出力値を持つようにし、減衰部１２の減衰率を調整することにより、デジタルアナログ変換部１、５２の最小出力値を異ならせるようにした。
【００５６】
デジタルアナログ変換部に同じ基準電圧を用いることができるなど、構成が簡単になるという効果がある。また、簡単に任意の減衰率を得ることができるという効果がある。
【００５７】
さらに、本発明の実施例は、複数のデジタルアナログ変換部５２、１のうち、最小出力値が最大のデジタルアナログ変換部５２をパルス幅変調方式のデジタルアナログ変換器とし、他のデジタルアナログ変換部１を変換速度が速いデジタルアナログ変換器とした。
【００５８】
下位側に変換速度の速いデジタルアナログ変換器を用いるようにしたので、細かい変動を高速で捕らえることができるという効果がある。
【００５９】
また、本発明の実施例は、複数のデジタルアナログ変換部５２，１の最小出力値の比率を２の乗数倍に設定した。データのビットを分割して各デジタルアナログ変換部に分配するだけでよく、設定値算出の剰余算が不要になるので、高速応答が可能になるという効果がある。
【００６０】
さらに、本発明の実施例は、異なる最小出力値を有する複数のデジタルアナログ変換部１，５２を有し、この複数のデジタルアナログ変換部１，５２に物理量を変換したデジタル値に関連する値を入力し、この複数のデジタルアナログ変換部１，５２のアナログ出力を加算して電流信号に変換して出力する電流出力伝送器であって、デジタルアナログ変換部１，５２の少なくとも１つをパルス幅変調方式のデジタルアナログ変換器５２で構成し、他のデジタルアナログ変換部１を変換速度が速いデジタルアナログ変換器で構成するようにした。
【００６１】
デジタルアナログ変換部を２個以上用いて変換するようにしたので、パルス変調方式のデジタルアナログ変換器の出力パルスの周期を短くすることができるので、応答速度を早くすることができるという効果がある。また、構成が簡単なパルス変調方式のデジタルアナログ変換器を併用するようにしたので、構成が複雑にならないという効果もある。
【００６２】
また、本発明の実施例は、変換速度が早いデジタルアナログ変換器１は、重み抵抗型またはラダー抵抗型または重み定電流型または抵抗回路網型のデジタルアナログ変換器であることを特徴とした。構成が比較的簡単でかつ変換速度が速いデジタルアナログ変換器を用いることができるという効果がある。
【００６３】
さらに、本発明の実施例は、変換速度が速いデジタルアナログ変換器１１は、マイクロプロセッサに内蔵されたデジタルアナログ変換器であることを特徴とした。個別のデジタルアナログ変換器が不要なため、構成が簡単になるという効果がある。
【００６４】
また、本発明の実施例は、複数のデジタルアナログ変換部１，５２のうち最小出力値が最大のデジタルアナログ変換部５２を除いたデジタルアナログ変換部は、デジタル値をアナログ信号に変換するＤ／Ａ変換回路１１と、このＤ／Ａ変換回路１１の出力を減衰させる減衰部１２とから構成されることを特徴とした。
【００６５】
減衰部で減衰させるために高抵抗を用いる必要がないので、漏れ電流による精度低下がなく、かつ信頼性が低下しないという効果がある。
【００６６】
さらに、本発明の実施例は、最小出力値が最大のデジタルアナログ変換部５２およびＤ／Ａ変換回路１１はほぼ同じ最小出力値を持つようにし、減衰部１２の減衰率を調整することにより、デジタルアナログ変換部１の最小出力値を異ならせるようにした。
【００６７】
デジタルアナログ変換部に同じ基準電圧を用いることができるなど、構成が簡単になるという効果がある。また、簡単に任意の減衰率を得ることができるという効果がある。
【００６８】
また、本発明の実施例は、複数のデジタルアナログ変換部１、５２のうち、最小出力値が最大のデジタルアナログ変換部５２をパルス幅変調方式のデジタルアナログ変換器とし、他のデジタルアナログ変換部１を変換速度が速いデジタルアナログ変換器とした。
【００６９】
下位側に変換速度の速いデジタルアナログ変換器を用いるようにしたので、細かい変動を高速で捕らえることができるという効果がある。
【００７０】
さらに、本発明の実施例は、複数のデジタルアナログ変換部１，５２の最小出力値の比率を２の乗数倍に設定した。データのビットを分割して各デジタルアナログ変換部に分配するだけ出よく、設定値算出の剰余算が不要になるので、高速応答が可能になるという効果がある。
【図面の簡単な説明】
【図１】本発明の一実施例を示す構成図である。
【図２】各デジタルアナログ変換部の設定の一例を示す表である。
【図３】本発明の他の実施例を示す構成図である。
【図４】従来の２線式伝送器の構成図である。
【図５】従来の２線式伝送器の構成図である。
【符号の説明】
１ デジタルアナログ変換部
１１ Ｄ／Ａ変換回路
１２、２１、２２ 減衰部
３ 加算部
４２、４３ マイクロプロセッサ
５２ ＰＷＭ回路
７２ ローパスフィルタ
８２ ２線式電圧電流変換器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital-to-analog converter that is simple in structure and capable of high-speed response, and more particularly, a digital-to-analog converter suitable for use in a current output transmitter with limited power consumption and two-wire transmission using the same. It is about a vessel.
[0002]
[Prior art]
FIG. 4 shows a configuration of a two-wire transmitter that receives a signal from a sensor (not shown) that converts a physical quantity into an electrical signal such as frequency and voltage, converts the signal into a current signal of 4 to 20 mA, and outputs the current signal. In FIG. 4, the signal S from the sensor is input to the microprocessor 41. The microprocessor 41 converts this signal S into a set value D (0 ≦ D ≦ 1) and outputs it to a PWM circuit (pulse width modulation type digital onalograph converter) 51.
[0003]
The PWM circuit 51 outputs a pulse signal having a duty ratio corresponding to the input set value D to the buffer 61. The buffer 61 converts this pulse signal into a pulse wave having the amplitude of the reference voltage Vref and outputs it to the low-pass filter 71. The low-pass filter 71 smoothes the pulse wave, converts it into a DC signal, and outputs it to the two-wire voltage-current converter 81.
[0004]
The two-wire voltage / current converter 81 outputs a current Io proportional to the input, that is, the output of the low-pass filter 71. When the resistance values of the resistors R1 to R3 are the same R1 to R3 and the voltage value of the reference voltage Vref is the same Vref, the output current Io is
Io = D × Vref × R2 / (R1 × R3)
become. In this way, the physical quantity is converted into a current signal and output.
[0005]
FIG. 5 shows another example of a two-wire transmitter. An electrical signal S from a sensor (not shown) is input to the microprocessor 42. The microprocessor 42 outputs the coarse adjustment set value D1 (0 ≦ D1 ≦ 1) to the PWM circuit A52 and the fine adjustment set value D2 (0 ≦ D2 ≦ 1) to the PWM circuit B53 according to the value of the electric signal S.
[0006]
The PWM circuit A52 and the PWM circuit B53 output a pulse wave having a duty ratio corresponding to the input set value to the buffers 62 and 63 as in the embodiment of FIG. 4, and the buffers 62 and 63 shape the amplitude to the reference voltage Vref. And output to the low-pass filters 72 and 73. Outputs of the low-pass filters 72 and 73 are added by a two-wire voltage-current converter 82, converted into a current value, and output.
[0007]
When the output current value corresponding to the coarse adjustment setting value D1 is Io1 and the output current value corresponding to the fine adjustment setting value D2 is Io2, the output current value Io is
Io ＝ Io1 ＋ Io2
It is represented by Also,
Io1 ＝ D1 × R2 × Vref / (R1 × R3)
Io2 = D2 × R2 × Vref / (R1 × R4)
It is represented by R1 to R4 are resistance values of the resistors R1 to R4, and Vref is a voltage value of the reference voltage Vref.
[0008]
The ratio of the coarse adjustment component Io1 and the fine adjustment component Io2 of the output current is
Io1 / Io2 = R4 / R3
become. That is, the ratio of the coarse adjustment component and the fine adjustment is determined by the ratio of R4 and R3. For example, when the coarse adjustment component setting value D1 is assigned 8 bits and the fine adjustment setting value D2 is assigned 8 bits, and R4 / R3 = 256, a resolution of 16 bits can be obtained.
[0009]
Since this two-wire transmitter uses two PWM circuits, the period of the output pulse wave can be shortened. Therefore, since the time constants of the low-pass filters 72 and 73 can be reduced, there is a feature that the response can be made faster than the two-wire transmitter of FIG.
[0010]
[Problems to be solved by the invention]
However, such a two-wire transmitter has the following problems.
[0011]
In the transmitter of FIG. 4, the time constant of the low-pass filter 71 has to be set to a value considerably larger than the period of the output pulse wave of the PWM circuit 51, so that there is a problem that the responsiveness is deteriorated.
[0012]
If the period of the pulse wave is shortened, the time constant of the low-pass filter 71 can be reduced, but the clock frequency of the PWM circuit 51 must be increased. However, increasing the clock frequency increases power consumption. For this reason, there is a problem that it is difficult to realize with a two-wire transmitter in which power consumption must be reduced.
[0013]
The two-wire transmitter of FIG. 5 can improve the responsiveness compared to the two-wire transmitter of FIG. 4, but the ratio of the resistors R3 and R4 must be increased in order to increase the resolution. . Therefore, the resistance value of the resistor R4 is increased, the resistance of the resistor is lowered, and there is a problem that the accuracy is deteriorated due to the influence of the leakage current when mounted on the printed board.
[0014]
Therefore, the problem to be solved by the present invention is to provide a digital-to-analog converter that can improve the responsiveness and has no deterioration in accuracy, and a current output transmitter using the same.
[0015]
[Means for Solving the Problems]
The present invention for solving such problems is as follows.
(1) A microprocessor that outputs a setting value for coarse adjustment and a setting value for fine adjustment corresponding to an electrical signal input from a sensor, and a pulse wave having a duty ratio corresponding to one input setting value At least one PWM circuit, a low-pass filter that smoothes and converts each pulse wave into a DC voltage, and at least one D / A converter that outputs an analog voltage corresponding to the other input set value, A two-wire voltage current that attenuates the output of the D / A converter, adds the output of the low-pass filter and the output of the attenuation unit, and outputs a current value corresponding to the added voltage and a converter, wherein the damping unit comprises: a voltage divider comprising the output of the D / a converter from the dividing resistor, composed of the output to the OP amplifier based on the divided voltage buffer Wherein the PWM circuit receives a set value for the coarse adjustment, the D / A converter, the current output transmitter, characterized in that inputting the set value for the fine adjustment.
(2) The current output transmitter according to (1 ), wherein the D / A converter is a weight resistance type, ladder resistance type, weight constant current type, or resistance network type digital-analog converter.
(3) The current output transmitter according to (1 ), wherein the D / A converter is a digital / analog converter built in the microprocessor.
(4) The current output transmitter according to (2) , wherein the resistance connected in series to the output of the low-pass filter and the resistance connected in series to the output of the attenuation unit have the same resistance value.
(5) The current output transmitter according to (1) , wherein the ratio between the output of the low-pass filter and the output of the attenuator is a multiplier of 2.
In addition, the embodiment of the present invention includes a plurality of digital / analog conversion units 1 and 52 having different minimum output values, and the plurality of digital / analog conversion units 1 and 52 relate to digital values to be converted into analog values. A digital-to-analog converter configured to input a value and add and output the analog outputs of a plurality of digital-to-analog converters 1 and 52, and at least one of the digital-to-analog converters is converted to a pulse width modulation type digital-to-analog converter And the other digital-to-analog converter is constituted by the digital-to-analog converter 11 having a high conversion speed. The response speed can be increased.
[0016]
Furthermore, an embodiment of the present invention is characterized in that the digital-analog converter having a high conversion speed is a weight resistance type, ladder resistance type, weight constant current type, or resistance network type digital analog converter. is there.
[0017]
In the embodiment of the present invention, the digital / analog conversion unit 1 except for the digital / analog conversion unit having the maximum minimum output value among the plurality of digital / analog conversion units 1 and 52 is a D / D converter that converts a digital value into an analog signal. It is characterized by comprising an A conversion circuit 11 and an attenuating section 12 for attenuating the output of the D / A conversion circuit 11. Loss of accuracy is eliminated.
[0018]
Further, in the embodiment of the present invention, the digital / analog conversion unit 52 and the D / A conversion circuit 11 having the largest minimum output value have substantially the same minimum output value, and the attenuation rate of the attenuation unit 12 is adjusted. The minimum output values of the digital-analog converters 1 and 52 are made different. Configuration is simplified.
[0019]
In the embodiment of the present invention, among the plurality of digital-analog conversion units 52, 1, the digital-analog conversion unit 52 having the maximum minimum output value is used as a pulse-width modulation type digital-analog converter, and the other digital-analog conversion units 1 is a digital-analog converter having a high conversion speed. Responsiveness can be improved.
[0020]
Furthermore, in the embodiment of the present invention, the ratio of the minimum output values of the plurality of digital-analog converters 52, 1 is set to a multiple of 2. The remainder calculation for setting value calculation is unnecessary.
[0021]
In addition, the embodiment of the present invention includes a plurality of digital / analog conversion units 1 and 52 having different minimum output values, and values related to digital values obtained by converting physical quantities into the plurality of digital / analog conversion units 1 and 52 are set. A current output transmitter for inputting and converting the analog outputs of the plurality of digital / analog conversion units 1 and 52 to convert them into a current signal, and outputting at least one of the digital / analog conversion units 1 and 52 with a pulse width The digital-analog converter 52 of the modulation system is used, and the other digital-analog converter 1 is formed of a digital-analog converter having a high conversion speed. Responsiveness becomes faster.
[0022]
Further, the embodiment of the present invention is characterized in that the digital-analog converter 1 having a high conversion speed is a weight resistance type, ladder resistance type, weight constant current type, or resistance network type digital analog converter. It is.
[0023]
Further, the embodiment of the present invention is characterized in that the digital-analog converter 11 having a high conversion speed is a digital-analog converter incorporated in a microprocessor. Configuration is simplified.
[0024]
Further, according to the embodiment of the present invention, the digital / analog conversion unit excluding the digital / analog conversion unit 52 having the maximum minimum output value among the plurality of digital / analog conversion units 1 and 52 converts the digital value into an analog signal. It is characterized by comprising an A conversion circuit 11 and an attenuating section 12 for attenuating the output of the D / A conversion circuit 11. The response speed can be increased.
[0025]
In the embodiment of the present invention, the digital / analog conversion unit 52 and the D / A conversion circuit 11 having the maximum minimum output value have substantially the same minimum output value, and the attenuation rate of the attenuation unit 12 is adjusted. The minimum output value of the digital-analog converter 1 is made different. Loss of accuracy is eliminated.
[0026]
Furthermore, in the embodiment of the present invention, among the plurality of digital / analog converters 1 and 52, the digital / analog converter 52 having the maximum minimum output value is a digital analog converter of a pulse width modulation type, and the other digital / analog converters are used. 1 is a digital-analog converter having a high conversion speed.
[0027]
In the embodiment of the present invention, the ratio of the minimum output values of the plurality of digital-analog converters 1 and 52 is set to a multiple of 2. The remainder calculation for obtaining the set value becomes unnecessary.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a two-wire transmitter according to the present invention. The same elements as those in FIG. 5 are denoted by the same reference numerals and description thereof is omitted. In FIG. 1, a microprocessor 42 outputs a coarse adjustment setting value D1 and a fine adjustment setting value D2 corresponding to an electric signal S input from a sensor (not shown).
[0029]
The PWM circuit 52 outputs a pulse wave having a duty ratio corresponding to the input coarse adjustment setting value D1. The amplitude of this pulse wave is shaped by the buffer 62 to the magnitude of the reference voltage Vref. The shaped pulse wave is smoothed by the low-pass filter 72 and converted into a DC voltage.
[0030]
Reference numeral 11 denotes a D / A converter which receives a fine adjustment set value D2 and outputs an analog voltage corresponding to the set value. The D / A converter 11 is a digital / analog converter having a relatively high conversion speed, such as a resistance network type, a weight resistance type, a ladder resistance type, or a weight constant current type. Alternatively, a digital / analog converter incorporated in the microprocessor 42 may be used.
[0031]
An attenuation unit 12 attenuates the output of the D / A converter 11. That is, the output of the D / A converter is divided by a voltage divider composed of resistors R5 and R6, and the divided voltage is output through a buffer constituted by an OP amplifier Amp. The D / A converter 11 and the attenuator 12 constitute the digital / analog converter 1. The outputs of the digital-analog converter 1 are added by a two-wire voltage-current converter 82, and a current value Io corresponding to the added voltage is output.
[0032]
Next, the operation of this embodiment will be described. When the output current value of the two-wire voltage-current converter 82 is Io, the output current value corresponding to the coarse adjustment setting value D1 is Io1, and the output current value corresponding to the fine adjustment setting value D2 is Io2,
Io = Io1 + Io2 (1)
become.
[0033]
Io1 and Io2 are expressed by the following equations (2) and (3).
Io1 = D1 x (R2 / R1) x Vref / R3 (2)
Io2 = D2 x (R2 / R1) x Vref x Dec / R4 (3)
However, Dec is the attenuation factor of the attenuator 12.
Dec = R6 / (R5 + R6) (4)
It is represented by Therefore, the ratio of the coarse adjustment component Io1 to the fine adjustment component Io2 in the output current Io is given by the following equation (5).
Io2 / Io1 = (R3 / R4) × R6 / (R5 + R6) (5)
[0034]
From this equation (3), the ratio of the fine adjustment component to the coarse adjustment component can be arbitrarily set by changing the voltage dividing ratio of the resistors R5 and R6. In this case, the resistors R3 and R4 can use the same resistance value. In addition, since the resistance values of the resistors R5 and R6 are not affected by other factors, it is not necessary to use such a large resistance value even if the attenuation factor is increased.
[0035]
FIG. 2 shows a specific setting example. In this example, Vref = 2.5 V, R1 = 100Ω, R2 = R3 = R6 = 100 KΩ, and R4 = R5 = 1 MΩ. The set values of D1 and D2 are both 0-255.
[0036]
The maximum output of the coarse adjustment setting value D1 by the PWM circuit 52 is calculated by substituting the respective values into the equation (1).
Maximum output = 2.5V × (100KΩ / 100Ω) × (1 / 100KΩ) = 25mA
become. The minimum output, that is, the resolution is minimum output = maximum output / 255 = 98.04 μA.
become.
[0037]
Similarly, the maximum output of the fine adjustment setting value D2 by the D / A converter 11 is the maximum output = 2.5V × (100KΩ / 100Ω) × (100KΩ / (1MΩ + 100KΩ)) ×
(1 / 1MΩ) = 227.27μA
become. The minimum output, that is, the resolution is minimum output = 227.27 μA / 255 = 0.8878 μA
It is.
[0038]
If the fine adjustment set value D2 is 110, the corresponding output current Io2 is 97.66 μA. Since this value is close to the resolution value of the coarse adjustment setting value D1, if the fine adjustment setting value is changed from 0 to 110, a relationship is obtained in which the coarse adjustment setting value increases by 1 when the fine adjustment setting value becomes full scale. .
[0039]
In order to set the coarse adjustment setting value D1 and the fine adjustment setting value D2, the following procedure is performed.
(1) Divide the current value to be output by the minimum output value of the PWM circuit of FIG.
(2) The remainder of (1) is divided by the minimum output value of the D / A converter of FIG.
(3) The quotient of (1) is set in the PWM circuit 52 as D1.
(4) The quotient of (2) is set in the D / A converter 11 as D2.
[0040]
That is, the remainder calculation must be performed twice. Since a two-wire transmitter requires low power consumption, it is difficult to increase the CPU clock frequency. For this reason, it takes time to calculate the two remainders, and there is a disadvantage that the response time is delayed.
[0041]
Therefore, the ratio of the output current of the coarse adjustment component and the output current of the fine adjustment component is adjusted to be 2 to the nth power (n is an integer). For example, a 16-bit integer (15 bits excluding the sign component) is made to correspond to the full scale of the output current, the physical quantity detected by the sensor is converted to a value of 0 to 7FFFH, and the fine adjustment setting value D2 is 7 bits. 8 bits are assigned to the coarse adjustment setting value D1. In this case, it is only necessary to obtain a relationship in which the coarse adjustment set value increases by 1 when the fine adjustment set value becomes full scale (= 128).
[0042]
Since the ratio of the output current Io1 of the coarse adjustment component and the output current Io2 of the fine adjustment component is given by the above equation (5),
Io2 / Io1 = (R3 / R4) x R6 / (R5 + R6) = 1/128 (6)
What is necessary is just to determine the value of resistance R3-R6 so that it may become.
[0043]
As in the embodiment of FIG. 1, assuming that R1 = 100Ω and R2 = R3 = 100KΩ, the above equation can be satisfied if R4 = 330KΩ + 470KΩ, R5 = 150KΩ, and R6 = 10KΩ. Since these resistance values are included in the general-purpose E24 series, they can be easily obtained.
[0044]
By arranging the equations (1) to (4), the output current Io is

become. Substituting the above equation (6) and R1 = 100Ω and R2 = R3 = 100KΩ into this equation,
Io = (Vref / 100) × (D1 + D2 / 128)
become.
[0045]
That is, it is understood that the upper 8 bits should be set to the coarse adjustment setting value D1 and the lower 7 bits should be set to the fine adjustment setting value D2. In this way, since it is not necessary to perform time-consuming remainder calculation, the responsiveness can be improved.
[0046]
FIG. 3 shows another embodiment of the present invention. This embodiment uses three digital-analog converters. In FIG. 3, reference numeral 43 denotes a microprocessor in the signal processing circuit, which converts an output S of a sensor (not shown) into a value of (n1 + n2 + n3) bits.
[0047]
Elements 1 to 3 are the PWM circuit 52 or the digital / analog conversion unit 1 in FIG. 1, and the values converted by the microprocessor 43 are input. That is, lower n3 bits are input to element 1, middle n2 is input to element 2, and upper n1 bits are input to element 3 as setting values. Element 1 to element 3 convert the input set value into an analog signal and output it.
[0048]
^{Reference numeral} 21 denotes an attenuation unit that attenuates the output of the element 1 to 1/2 ^{n2 + n3} . An attenuation unit 22 attenuates the output of the element 2 to 1/2 ⁿ² . Reference numeral 3 denotes an adder which adds the outputs of the attenuators 21 and 22 and the element 3 and converts it to a current signal and outputs it if necessary.
[0049]
In these embodiments, two or three digital / analog converters are used. However, four or more digital / analog converters may be used. In the embodiment of FIG. 1, the example of the two-wire transmitter has been described, but it can also be used for a three-wire or four-wire transmitter.
[0050]
【The invention's effect】
As is clear from the above description, the following effects can be expected according to the present invention.
The embodiment of the present invention includes a plurality of digital / analog conversion units 1 and 52 having different minimum output values, and the plurality of digital / analog conversion units 1 and 52 are provided with values related to digital values to be converted into analog values. A digital-to-analog converter configured to input and add and output the analog outputs of the plurality of digital-to-analog conversion units 1 and 52, and at least one of the digital-to-analog conversion units is a pulse-width modulation type digital-to-analog converter 52. The other digital-analog converter is configured by the digital-analog converter 11 having a high conversion speed.
[0051]
Since conversion is performed by using two or more digital / analog converters, the period of the output pulse of the pulse-modulation type digital / analog converter can be shortened, so that the response speed can be increased. . Further, since the pulse modulation type digital-analog converter having a simple configuration is also used, there is an effect that the configuration is not complicated.
[0052]
In an embodiment of the present invention, the digital-to-analog converter having a high conversion speed is a weight resistor type, ladder resistor type, weighted constant current type or resistor network type digital-to-analog converter. There is an effect that a digital-analog converter having a relatively simple configuration and a high conversion speed can be used.
[0053]
Further, according to the embodiment of the present invention, the digital / analog conversion unit 1 except for the digital / analog conversion unit having the maximum minimum output value among the plurality of digital / analog conversion units 1 and 52 is configured to convert the digital value into an analog signal. It is characterized by comprising an A conversion circuit 11 and an attenuation section 12 for attenuating the output of the D / A conversion circuit 11.
[0054]
Since it is not necessary to use a high resistance to attenuate at the attenuation section, there is an effect that there is no decrease in accuracy due to leakage current and reliability is not decreased.
[0055]
In the embodiment of the present invention, the digital / analog conversion unit 52 and the D / A conversion circuit 11 having the maximum minimum output value have substantially the same minimum output value, and the attenuation rate of the attenuation unit 12 is adjusted. The minimum output values of the digital-analog converters 1 and 52 are made different.
[0056]
The same reference voltage can be used for the digital-analog converter, and the configuration is simplified. Moreover, there is an effect that an arbitrary attenuation rate can be easily obtained.
[0057]
Further, according to the embodiment of the present invention, among the plurality of digital / analog conversion units 52 and 1, the digital / analog conversion unit 52 having the maximum minimum output value is used as a pulse / width modulation type digital / analog converter, and other digital / analog conversion units are used. 1 is a digital-analog converter having a high conversion speed.
[0058]
Since a digital-analog converter having a high conversion speed is used on the lower side, there is an effect that fine fluctuations can be captured at high speed.
[0059]
In the embodiment of the present invention, the ratio of the minimum output values of the digital-to-analog converters 52 and 1 is set to a multiplier of 2. It is only necessary to divide the data bits and distribute them to the respective digital-analog converters. This eliminates the need for the remainder calculation for calculating the set value, and thus has the effect of enabling a high-speed response.
[0060]
Furthermore, the embodiment of the present invention has a plurality of digital / analog conversion units 1 and 52 having different minimum output values, and a value related to a digital value obtained by converting a physical quantity into the plurality of digital / analog conversion units 1 and 52. A current output transmitter for inputting and converting the analog outputs of the plurality of digital / analog conversion units 1 and 52 to convert them into a current signal, and outputting at least one of the digital / analog conversion units 1 and 52 with a pulse width The digital-analog converter 52 of the modulation system is used, and the other digital-analog converter 1 is configured of a digital-analog converter having a high conversion speed.
[0061]
Since conversion is performed by using two or more digital / analog converters, the period of the output pulse of the pulse-modulation type digital / analog converter can be shortened, so that the response speed can be increased. . In addition, since the pulse modulation type digital-analog converter having a simple configuration is used in combination, the configuration is not complicated.
[0062]
The embodiment of the present invention is characterized in that the digital-analog converter 1 having a high conversion speed is a weight resistance type, ladder resistance type, weight constant current type, or resistance network type digital analog converter. There is an effect that a digital-analog converter having a relatively simple configuration and a high conversion speed can be used.
[0063]
Furthermore, the embodiment of the present invention is characterized in that the digital-analog converter 11 having a high conversion speed is a digital-analog converter built in a microprocessor. Since a separate digital-to-analog converter is unnecessary, there is an effect that the configuration is simplified.
[0064]
In the embodiment of the present invention, the digital / analog conversion unit excluding the digital / analog conversion unit 52 having the maximum minimum output value among the plurality of digital / analog conversion units 1 and 52 converts the digital value into an analog signal. It is characterized by comprising an A conversion circuit 11 and an attenuation section 12 for attenuating the output of the D / A conversion circuit 11.
[0065]
Since it is not necessary to use a high resistance to attenuate at the attenuation section, there is an effect that there is no decrease in accuracy due to leakage current and reliability is not decreased.
[0066]
Further, in the embodiment of the present invention, the digital / analog conversion unit 52 and the D / A conversion circuit 11 having the largest minimum output value have substantially the same minimum output value, and the attenuation rate of the attenuation unit 12 is adjusted. The minimum output value of the digital-analog converter 1 is made different.
[0067]
The same reference voltage can be used for the digital-analog converter, and the configuration is simplified. Moreover, there is an effect that an arbitrary attenuation rate can be easily obtained.
[0068]
In the embodiment of the present invention, among the plurality of digital / analog converters 1 and 52, the digital / analog converter 52 having the maximum minimum output value is a digital analog converter of a pulse width modulation system, and the other digital / analog converters are used. 1 is a digital-analog converter having a high conversion speed.
[0069]
Since a digital-analog converter having a high conversion speed is used on the lower side, there is an effect that fine fluctuations can be captured at high speed.
[0070]
Furthermore, in the embodiment of the present invention, the ratio of the minimum output values of the plurality of digital-analog converters 1 and 52 is set to a multiplier of 2. The data bits can be divided and distributed to the respective digital-analog converters, and the remainder calculation for setting value calculation is not required, so that a high-speed response can be achieved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of the present invention.
FIG. 2 is a table showing an example of settings of each digital-analog converter.
FIG. 3 is a block diagram showing another embodiment of the present invention.
FIG. 4 is a configuration diagram of a conventional two-wire transmitter.
FIG. 5 is a configuration diagram of a conventional two-wire transmitter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Digital analog conversion part 11 D / A conversion circuit 12, 21, 22 Attenuation part 3 Addition part 42, 43 Microprocessor 52 PWM circuit 72 Low pass filter 82 Two-wire voltage-current converter

Claims (5)

A microprocessor that outputs a setting value for coarse adjustment and a setting value for fine adjustment corresponding to the electrical signal input from the sensor;
At least one PWM circuit that outputs a pulse wave having a duty ratio corresponding to one of the input set values;
A low-pass filter for smoothing each pulse wave and converting it to a DC voltage;
At least one D / A converter that outputs an analog voltage corresponding to the other set value inputted;
An attenuation unit for attenuating the output of each of the D / A converters;
A two-wire voltage-current converter that adds the output of the low-pass filter and the output of the attenuation unit, and outputs a current value corresponding to the added voltage ;
The attenuating unit includes a voltage divider composed of a resistor that divides the output of the D / A converter, and a buffer configured by an OP amplifier that outputs based on the divided voltage,
The PWM circuit inputs the setting value for the coarse adjustment,
The current output transmitter, wherein the D / A converter inputs the setting value for fine adjustment . The D / A converter, the current output transmitter according to claim 1, characterized in that the weight resistance type or ladder resistor type or weight constant current or resistor network type digital-to-analog converter. The D / A converter, the current output transmitter according to claim 1, characterized in that a digital-to-analog converter incorporated in the microprocessor. 3. The current output transmitter according to claim 2 , wherein the resistance connected in series to the output of the low-pass filter and the resistance connected in series to the output of the attenuation unit have the same resistance value. Current output transmitter according to claim 1, characterized in that the multiplier multiplying the ratio of 2 between the output of the output and the damping portion of the low-pass filter.

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